py32f0/py32f002a/syscfg/
cfgr2.rs

1///Register `CFGR2` reader
2pub struct R(crate::R<CFGR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFGR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFGR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFGR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CFGR2` writer
17pub struct W(crate::W<CFGR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFGR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFGR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFGR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `LOCKUP_LOCK` reader - Cortex-M0+ LOCKUP bit enable bit
38pub type LOCKUP_LOCK_R = crate::BitReader<LOCKUP_LOCK_A>;
39/**Cortex-M0+ LOCKUP bit enable bit
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum LOCKUP_LOCK_A {
44    ///0: Cortex-M0+ LOCKUP output disconnected from TIM1/16/17 Break input
45    Disconnected = 0,
46    ///1: Cortex-M0+ LOCKUP output connected to TIM1/16/17 Break input
47    Connected = 1,
48}
49impl From<LOCKUP_LOCK_A> for bool {
50    #[inline(always)]
51    fn from(variant: LOCKUP_LOCK_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl LOCKUP_LOCK_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> LOCKUP_LOCK_A {
59        match self.bits {
60            false => LOCKUP_LOCK_A::Disconnected,
61            true => LOCKUP_LOCK_A::Connected,
62        }
63    }
64    ///Checks if the value of the field is `Disconnected`
65    #[inline(always)]
66    pub fn is_disconnected(&self) -> bool {
67        *self == LOCKUP_LOCK_A::Disconnected
68    }
69    ///Checks if the value of the field is `Connected`
70    #[inline(always)]
71    pub fn is_connected(&self) -> bool {
72        *self == LOCKUP_LOCK_A::Connected
73    }
74}
75///Field `LOCKUP_LOCK` writer - Cortex-M0+ LOCKUP bit enable bit
76pub type LOCKUP_LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, LOCKUP_LOCK_A, O>;
77impl<'a, const O: u8> LOCKUP_LOCK_W<'a, O> {
78    ///Cortex-M0+ LOCKUP output disconnected from TIM1/16/17 Break input
79    #[inline(always)]
80    pub fn disconnected(self) -> &'a mut W {
81        self.variant(LOCKUP_LOCK_A::Disconnected)
82    }
83    ///Cortex-M0+ LOCKUP output connected to TIM1/16/17 Break input
84    #[inline(always)]
85    pub fn connected(self) -> &'a mut W {
86        self.variant(LOCKUP_LOCK_A::Connected)
87    }
88}
89///Field `COMP1_BRK_TIM1` reader - COMP1 output connect to TIM1 Break input
90pub type COMP1_BRK_TIM1_R = crate::BitReader<COMP1_BRK_TIM1_A>;
91/**COMP1 output connect to TIM1 Break input
92
93Value on reset: 0*/
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum COMP1_BRK_TIM1_A {
96    ///0: COMP? output not connect to TIM? Break input
97    Disconnected = 0,
98    ///1: COMP? output connected to TIM? Break input
99    Connected = 1,
100}
101impl From<COMP1_BRK_TIM1_A> for bool {
102    #[inline(always)]
103    fn from(variant: COMP1_BRK_TIM1_A) -> Self {
104        variant as u8 != 0
105    }
106}
107impl COMP1_BRK_TIM1_R {
108    ///Get enumerated values variant
109    #[inline(always)]
110    pub fn variant(&self) -> COMP1_BRK_TIM1_A {
111        match self.bits {
112            false => COMP1_BRK_TIM1_A::Disconnected,
113            true => COMP1_BRK_TIM1_A::Connected,
114        }
115    }
116    ///Checks if the value of the field is `Disconnected`
117    #[inline(always)]
118    pub fn is_disconnected(&self) -> bool {
119        *self == COMP1_BRK_TIM1_A::Disconnected
120    }
121    ///Checks if the value of the field is `Connected`
122    #[inline(always)]
123    pub fn is_connected(&self) -> bool {
124        *self == COMP1_BRK_TIM1_A::Connected
125    }
126}
127///Field `COMP1_BRK_TIM1` writer - COMP1 output connect to TIM1 Break input
128pub type COMP1_BRK_TIM1_W<'a, const O: u8> =
129    crate::BitWriter<'a, u32, CFGR2_SPEC, COMP1_BRK_TIM1_A, O>;
130impl<'a, const O: u8> COMP1_BRK_TIM1_W<'a, O> {
131    ///COMP? output not connect to TIM? Break input
132    #[inline(always)]
133    pub fn disconnected(self) -> &'a mut W {
134        self.variant(COMP1_BRK_TIM1_A::Disconnected)
135    }
136    ///COMP? output connected to TIM? Break input
137    #[inline(always)]
138    pub fn connected(self) -> &'a mut W {
139        self.variant(COMP1_BRK_TIM1_A::Connected)
140    }
141}
142///Field `COMP2_BRK_TIM1` reader - COMP2 output connect to TIM1 Break input
143pub use COMP1_BRK_TIM1_R as COMP2_BRK_TIM1_R;
144///Field `COMP1_BRK_TIM16` reader - COMP1 output connect to TIM16 Break input
145pub use COMP1_BRK_TIM1_R as COMP1_BRK_TIM16_R;
146///Field `COMP2_BRK_TIM16` reader - COMP2 output connect to TIM16 Break input
147pub use COMP1_BRK_TIM1_R as COMP2_BRK_TIM16_R;
148///Field `COMP2_BRK_TIM1` writer - COMP2 output connect to TIM1 Break input
149pub use COMP1_BRK_TIM1_W as COMP2_BRK_TIM1_W;
150///Field `COMP1_BRK_TIM16` writer - COMP1 output connect to TIM16 Break input
151pub use COMP1_BRK_TIM1_W as COMP1_BRK_TIM16_W;
152///Field `COMP2_BRK_TIM16` writer - COMP2 output connect to TIM16 Break input
153pub use COMP1_BRK_TIM1_W as COMP2_BRK_TIM16_W;
154///Field `ETR_SRC_TIM1` reader - TIM1 ETR source selection
155pub type ETR_SRC_TIM1_R = crate::FieldReader<u8, ETR_SRC_TIM1_A>;
156/**TIM1 ETR source selection
157
158Value on reset: 0*/
159#[derive(Clone, Copy, Debug, PartialEq, Eq)]
160#[repr(u8)]
161pub enum ETR_SRC_TIM1_A {
162    ///0: TIM1_ETR is connected to GPIO
163    Gpio = 0,
164    ///1: TIM1_ETR is connected to COMP1
165    Comp1 = 1,
166    ///2: TIM1_ETR is connected to COMP2
167    Comp2 = 2,
168    ///3: TIM1_ETR is connected to ADC
169    Adc = 3,
170}
171impl From<ETR_SRC_TIM1_A> for u8 {
172    #[inline(always)]
173    fn from(variant: ETR_SRC_TIM1_A) -> Self {
174        variant as _
175    }
176}
177impl ETR_SRC_TIM1_R {
178    ///Get enumerated values variant
179    #[inline(always)]
180    pub fn variant(&self) -> ETR_SRC_TIM1_A {
181        match self.bits {
182            0 => ETR_SRC_TIM1_A::Gpio,
183            1 => ETR_SRC_TIM1_A::Comp1,
184            2 => ETR_SRC_TIM1_A::Comp2,
185            3 => ETR_SRC_TIM1_A::Adc,
186            _ => unreachable!(),
187        }
188    }
189    ///Checks if the value of the field is `Gpio`
190    #[inline(always)]
191    pub fn is_gpio(&self) -> bool {
192        *self == ETR_SRC_TIM1_A::Gpio
193    }
194    ///Checks if the value of the field is `Comp1`
195    #[inline(always)]
196    pub fn is_comp1(&self) -> bool {
197        *self == ETR_SRC_TIM1_A::Comp1
198    }
199    ///Checks if the value of the field is `Comp2`
200    #[inline(always)]
201    pub fn is_comp2(&self) -> bool {
202        *self == ETR_SRC_TIM1_A::Comp2
203    }
204    ///Checks if the value of the field is `Adc`
205    #[inline(always)]
206    pub fn is_adc(&self) -> bool {
207        *self == ETR_SRC_TIM1_A::Adc
208    }
209}
210///Field `ETR_SRC_TIM1` writer - TIM1 ETR source selection
211pub type ETR_SRC_TIM1_W<'a, const O: u8> =
212    crate::FieldWriterSafe<'a, u32, CFGR2_SPEC, u8, ETR_SRC_TIM1_A, 2, O>;
213impl<'a, const O: u8> ETR_SRC_TIM1_W<'a, O> {
214    ///TIM1_ETR is connected to GPIO
215    #[inline(always)]
216    pub fn gpio(self) -> &'a mut W {
217        self.variant(ETR_SRC_TIM1_A::Gpio)
218    }
219    ///TIM1_ETR is connected to COMP1
220    #[inline(always)]
221    pub fn comp1(self) -> &'a mut W {
222        self.variant(ETR_SRC_TIM1_A::Comp1)
223    }
224    ///TIM1_ETR is connected to COMP2
225    #[inline(always)]
226    pub fn comp2(self) -> &'a mut W {
227        self.variant(ETR_SRC_TIM1_A::Comp2)
228    }
229    ///TIM1_ETR is connected to ADC
230    #[inline(always)]
231    pub fn adc(self) -> &'a mut W {
232        self.variant(ETR_SRC_TIM1_A::Adc)
233    }
234}
235impl R {
236    ///Bit 0 - Cortex-M0+ LOCKUP bit enable bit
237    #[inline(always)]
238    pub fn lockup_lock(&self) -> LOCKUP_LOCK_R {
239        LOCKUP_LOCK_R::new((self.bits & 1) != 0)
240    }
241    ///Bit 3 - COMP1 output connect to TIM1 Break input
242    #[inline(always)]
243    pub fn comp1_brk_tim1(&self) -> COMP1_BRK_TIM1_R {
244        COMP1_BRK_TIM1_R::new(((self.bits >> 3) & 1) != 0)
245    }
246    ///Bit 4 - COMP2 output connect to TIM1 Break input
247    #[inline(always)]
248    pub fn comp2_brk_tim1(&self) -> COMP2_BRK_TIM1_R {
249        COMP2_BRK_TIM1_R::new(((self.bits >> 4) & 1) != 0)
250    }
251    ///Bit 5 - COMP1 output connect to TIM16 Break input
252    #[inline(always)]
253    pub fn comp1_brk_tim16(&self) -> COMP1_BRK_TIM16_R {
254        COMP1_BRK_TIM16_R::new(((self.bits >> 5) & 1) != 0)
255    }
256    ///Bit 6 - COMP2 output connect to TIM16 Break input
257    #[inline(always)]
258    pub fn comp2_brk_tim16(&self) -> COMP2_BRK_TIM16_R {
259        COMP2_BRK_TIM16_R::new(((self.bits >> 6) & 1) != 0)
260    }
261    ///Bits 9:10 - TIM1 ETR source selection
262    #[inline(always)]
263    pub fn etr_src_tim1(&self) -> ETR_SRC_TIM1_R {
264        ETR_SRC_TIM1_R::new(((self.bits >> 9) & 3) as u8)
265    }
266}
267impl W {
268    ///Bit 0 - Cortex-M0+ LOCKUP bit enable bit
269    #[inline(always)]
270    #[must_use]
271    pub fn lockup_lock(&mut self) -> LOCKUP_LOCK_W<0> {
272        LOCKUP_LOCK_W::new(self)
273    }
274    ///Bit 3 - COMP1 output connect to TIM1 Break input
275    #[inline(always)]
276    #[must_use]
277    pub fn comp1_brk_tim1(&mut self) -> COMP1_BRK_TIM1_W<3> {
278        COMP1_BRK_TIM1_W::new(self)
279    }
280    ///Bit 4 - COMP2 output connect to TIM1 Break input
281    #[inline(always)]
282    #[must_use]
283    pub fn comp2_brk_tim1(&mut self) -> COMP2_BRK_TIM1_W<4> {
284        COMP2_BRK_TIM1_W::new(self)
285    }
286    ///Bit 5 - COMP1 output connect to TIM16 Break input
287    #[inline(always)]
288    #[must_use]
289    pub fn comp1_brk_tim16(&mut self) -> COMP1_BRK_TIM16_W<5> {
290        COMP1_BRK_TIM16_W::new(self)
291    }
292    ///Bit 6 - COMP2 output connect to TIM16 Break input
293    #[inline(always)]
294    #[must_use]
295    pub fn comp2_brk_tim16(&mut self) -> COMP2_BRK_TIM16_W<6> {
296        COMP2_BRK_TIM16_W::new(self)
297    }
298    ///Bits 9:10 - TIM1 ETR source selection
299    #[inline(always)]
300    #[must_use]
301    pub fn etr_src_tim1(&mut self) -> ETR_SRC_TIM1_W<9> {
302        ETR_SRC_TIM1_W::new(self)
303    }
304    ///Writes raw bits to the register.
305    #[inline(always)]
306    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
307        self.0.bits(bits);
308        self
309    }
310}
311/**SYSCFG configuration register 2
312
313This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
314
315For information about available fields see [cfgr2](index.html) module*/
316pub struct CFGR2_SPEC;
317impl crate::RegisterSpec for CFGR2_SPEC {
318    type Ux = u32;
319}
320///`read()` method returns [cfgr2::R](R) reader structure
321impl crate::Readable for CFGR2_SPEC {
322    type Reader = R;
323}
324///`write(|w| ..)` method takes [cfgr2::W](W) writer structure
325impl crate::Writable for CFGR2_SPEC {
326    type Writer = W;
327    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
328    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
329}
330///`reset()` method sets CFGR2 to value 0
331impl crate::Resettable for CFGR2_SPEC {
332    const RESET_VALUE: Self::Ux = 0;
333}
py32f0/py32f002a/syscfg/cfgr2.rs

py32f0/py32f002a/syscfg/
cfgr2.rs
