py32f0/py32f002a/exti/
imr.rs

1///Register `IMR` reader
2pub struct R(crate::R<IMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `IMR` writer
17pub struct W(crate::W<IMR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IMR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IMR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IMR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `IM0` reader - CPU wakeup with interrupt mask on event input
38pub type IM0_R = crate::BitReader<IM0_A>;
39/**CPU wakeup with interrupt mask on event input
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum IM0_A {
44    ///0: Interrupt request line is masked
45    Masked = 0,
46    ///1: Interrupt request line is unmasked
47    Unmasked = 1,
48}
49impl From<IM0_A> for bool {
50    #[inline(always)]
51    fn from(variant: IM0_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl IM0_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> IM0_A {
59        match self.bits {
60            false => IM0_A::Masked,
61            true => IM0_A::Unmasked,
62        }
63    }
64    ///Checks if the value of the field is `Masked`
65    #[inline(always)]
66    pub fn is_masked(&self) -> bool {
67        *self == IM0_A::Masked
68    }
69    ///Checks if the value of the field is `Unmasked`
70    #[inline(always)]
71    pub fn is_unmasked(&self) -> bool {
72        *self == IM0_A::Unmasked
73    }
74}
75///Field `IM0` writer - CPU wakeup with interrupt mask on event input
76pub type IM0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, IM0_A, O>;
77impl<'a, const O: u8> IM0_W<'a, O> {
78    ///Interrupt request line is masked
79    #[inline(always)]
80    pub fn masked(self) -> &'a mut W {
81        self.variant(IM0_A::Masked)
82    }
83    ///Interrupt request line is unmasked
84    #[inline(always)]
85    pub fn unmasked(self) -> &'a mut W {
86        self.variant(IM0_A::Unmasked)
87    }
88}
89///Field `IM1` reader - CPU wakeup with interrupt mask on event input
90pub use IM0_R as IM1_R;
91///Field `IM2` reader - CPU wakeup with interrupt mask on event input
92pub use IM0_R as IM2_R;
93///Field `IM3` reader - CPU wakeup with interrupt mask on event input
94pub use IM0_R as IM3_R;
95///Field `IM4` reader - CPU wakeup with interrupt mask on event input
96pub use IM0_R as IM4_R;
97///Field `IM5` reader - CPU wakeup with interrupt mask on event input
98pub use IM0_R as IM5_R;
99///Field `IM6` reader - CPU wakeup with interrupt mask on event input
100pub use IM0_R as IM6_R;
101///Field `IM7` reader - CPU wakeup with interrupt mask on event input
102pub use IM0_R as IM7_R;
103///Field `IM8` reader - CPU wakeup with interrupt mask on event input
104pub use IM0_R as IM8_R;
105///Field `IM9` reader - CPU wakeup with interrupt mask on event input
106pub use IM0_R as IM9_R;
107///Field `IM10` reader - CPU wakeup with interrupt mask on event input
108pub use IM0_R as IM10_R;
109///Field `IM11` reader - CPU wakeup with interrupt mask on event input
110pub use IM0_R as IM11_R;
111///Field `IM12` reader - CPU wakeup with interrupt mask on event input
112pub use IM0_R as IM12_R;
113///Field `IM13` reader - CPU wakeup with interrupt mask on event input
114pub use IM0_R as IM13_R;
115///Field `IM14` reader - CPU wakeup with interrupt mask on event input
116pub use IM0_R as IM14_R;
117///Field `IM15` reader - CPU wakeup with interrupt mask on event input
118pub use IM0_R as IM15_R;
119///Field `IM16` reader - CPU wakeup with interrupt mask on event input
120pub use IM0_R as IM16_R;
121///Field `IM17` reader - CPU wakeup with interrupt mask on event input
122pub use IM0_R as IM17_R;
123///Field `IM18` reader - CPU wakeup with interrupt mask on event input
124pub use IM0_R as IM18_R;
125///Field `IM19` reader - CPU wakeup with interrupt mask on event input
126pub use IM0_R as IM19_R;
127///Field `IM29` reader - CPU wakeup with interrupt mask on event input
128pub use IM0_R as IM29_R;
129///Field `IM1` writer - CPU wakeup with interrupt mask on event input
130pub use IM0_W as IM1_W;
131///Field `IM2` writer - CPU wakeup with interrupt mask on event input
132pub use IM0_W as IM2_W;
133///Field `IM3` writer - CPU wakeup with interrupt mask on event input
134pub use IM0_W as IM3_W;
135///Field `IM4` writer - CPU wakeup with interrupt mask on event input
136pub use IM0_W as IM4_W;
137///Field `IM5` writer - CPU wakeup with interrupt mask on event input
138pub use IM0_W as IM5_W;
139///Field `IM6` writer - CPU wakeup with interrupt mask on event input
140pub use IM0_W as IM6_W;
141///Field `IM7` writer - CPU wakeup with interrupt mask on event input
142pub use IM0_W as IM7_W;
143///Field `IM8` writer - CPU wakeup with interrupt mask on event input
144pub use IM0_W as IM8_W;
145///Field `IM9` writer - CPU wakeup with interrupt mask on event input
146pub use IM0_W as IM9_W;
147///Field `IM10` writer - CPU wakeup with interrupt mask on event input
148pub use IM0_W as IM10_W;
149///Field `IM11` writer - CPU wakeup with interrupt mask on event input
150pub use IM0_W as IM11_W;
151///Field `IM12` writer - CPU wakeup with interrupt mask on event input
152pub use IM0_W as IM12_W;
153///Field `IM13` writer - CPU wakeup with interrupt mask on event input
154pub use IM0_W as IM13_W;
155///Field `IM14` writer - CPU wakeup with interrupt mask on event input
156pub use IM0_W as IM14_W;
157///Field `IM15` writer - CPU wakeup with interrupt mask on event input
158pub use IM0_W as IM15_W;
159///Field `IM16` writer - CPU wakeup with interrupt mask on event input
160pub use IM0_W as IM16_W;
161///Field `IM17` writer - CPU wakeup with interrupt mask on event input
162pub use IM0_W as IM17_W;
163///Field `IM18` writer - CPU wakeup with interrupt mask on event input
164pub use IM0_W as IM18_W;
165///Field `IM19` writer - CPU wakeup with interrupt mask on event input
166pub use IM0_W as IM19_W;
167///Field `IM29` writer - CPU wakeup with interrupt mask on event input
168pub use IM0_W as IM29_W;
169impl R {
170    ///Bit 0 - CPU wakeup with interrupt mask on event input
171    #[inline(always)]
172    pub fn im0(&self) -> IM0_R {
173        IM0_R::new((self.bits & 1) != 0)
174    }
175    ///Bit 1 - CPU wakeup with interrupt mask on event input
176    #[inline(always)]
177    pub fn im1(&self) -> IM1_R {
178        IM1_R::new(((self.bits >> 1) & 1) != 0)
179    }
180    ///Bit 2 - CPU wakeup with interrupt mask on event input
181    #[inline(always)]
182    pub fn im2(&self) -> IM2_R {
183        IM2_R::new(((self.bits >> 2) & 1) != 0)
184    }
185    ///Bit 3 - CPU wakeup with interrupt mask on event input
186    #[inline(always)]
187    pub fn im3(&self) -> IM3_R {
188        IM3_R::new(((self.bits >> 3) & 1) != 0)
189    }
190    ///Bit 4 - CPU wakeup with interrupt mask on event input
191    #[inline(always)]
192    pub fn im4(&self) -> IM4_R {
193        IM4_R::new(((self.bits >> 4) & 1) != 0)
194    }
195    ///Bit 5 - CPU wakeup with interrupt mask on event input
196    #[inline(always)]
197    pub fn im5(&self) -> IM5_R {
198        IM5_R::new(((self.bits >> 5) & 1) != 0)
199    }
200    ///Bit 6 - CPU wakeup with interrupt mask on event input
201    #[inline(always)]
202    pub fn im6(&self) -> IM6_R {
203        IM6_R::new(((self.bits >> 6) & 1) != 0)
204    }
205    ///Bit 7 - CPU wakeup with interrupt mask on event input
206    #[inline(always)]
207    pub fn im7(&self) -> IM7_R {
208        IM7_R::new(((self.bits >> 7) & 1) != 0)
209    }
210    ///Bit 8 - CPU wakeup with interrupt mask on event input
211    #[inline(always)]
212    pub fn im8(&self) -> IM8_R {
213        IM8_R::new(((self.bits >> 8) & 1) != 0)
214    }
215    ///Bit 9 - CPU wakeup with interrupt mask on event input
216    #[inline(always)]
217    pub fn im9(&self) -> IM9_R {
218        IM9_R::new(((self.bits >> 9) & 1) != 0)
219    }
220    ///Bit 10 - CPU wakeup with interrupt mask on event input
221    #[inline(always)]
222    pub fn im10(&self) -> IM10_R {
223        IM10_R::new(((self.bits >> 10) & 1) != 0)
224    }
225    ///Bit 11 - CPU wakeup with interrupt mask on event input
226    #[inline(always)]
227    pub fn im11(&self) -> IM11_R {
228        IM11_R::new(((self.bits >> 11) & 1) != 0)
229    }
230    ///Bit 12 - CPU wakeup with interrupt mask on event input
231    #[inline(always)]
232    pub fn im12(&self) -> IM12_R {
233        IM12_R::new(((self.bits >> 12) & 1) != 0)
234    }
235    ///Bit 13 - CPU wakeup with interrupt mask on event input
236    #[inline(always)]
237    pub fn im13(&self) -> IM13_R {
238        IM13_R::new(((self.bits >> 13) & 1) != 0)
239    }
240    ///Bit 14 - CPU wakeup with interrupt mask on event input
241    #[inline(always)]
242    pub fn im14(&self) -> IM14_R {
243        IM14_R::new(((self.bits >> 14) & 1) != 0)
244    }
245    ///Bit 15 - CPU wakeup with interrupt mask on event input
246    #[inline(always)]
247    pub fn im15(&self) -> IM15_R {
248        IM15_R::new(((self.bits >> 15) & 1) != 0)
249    }
250    ///Bit 16 - CPU wakeup with interrupt mask on event input
251    #[inline(always)]
252    pub fn im16(&self) -> IM16_R {
253        IM16_R::new(((self.bits >> 16) & 1) != 0)
254    }
255    ///Bit 17 - CPU wakeup with interrupt mask on event input
256    #[inline(always)]
257    pub fn im17(&self) -> IM17_R {
258        IM17_R::new(((self.bits >> 17) & 1) != 0)
259    }
260    ///Bit 18 - CPU wakeup with interrupt mask on event input
261    #[inline(always)]
262    pub fn im18(&self) -> IM18_R {
263        IM18_R::new(((self.bits >> 18) & 1) != 0)
264    }
265    ///Bit 19 - CPU wakeup with interrupt mask on event input
266    #[inline(always)]
267    pub fn im19(&self) -> IM19_R {
268        IM19_R::new(((self.bits >> 19) & 1) != 0)
269    }
270    ///Bit 29 - CPU wakeup with interrupt mask on event input
271    #[inline(always)]
272    pub fn im29(&self) -> IM29_R {
273        IM29_R::new(((self.bits >> 29) & 1) != 0)
274    }
275}
276impl W {
277    ///Bit 0 - CPU wakeup with interrupt mask on event input
278    #[inline(always)]
279    #[must_use]
280    pub fn im0(&mut self) -> IM0_W<0> {
281        IM0_W::new(self)
282    }
283    ///Bit 1 - CPU wakeup with interrupt mask on event input
284    #[inline(always)]
285    #[must_use]
286    pub fn im1(&mut self) -> IM1_W<1> {
287        IM1_W::new(self)
288    }
289    ///Bit 2 - CPU wakeup with interrupt mask on event input
290    #[inline(always)]
291    #[must_use]
292    pub fn im2(&mut self) -> IM2_W<2> {
293        IM2_W::new(self)
294    }
295    ///Bit 3 - CPU wakeup with interrupt mask on event input
296    #[inline(always)]
297    #[must_use]
298    pub fn im3(&mut self) -> IM3_W<3> {
299        IM3_W::new(self)
300    }
301    ///Bit 4 - CPU wakeup with interrupt mask on event input
302    #[inline(always)]
303    #[must_use]
304    pub fn im4(&mut self) -> IM4_W<4> {
305        IM4_W::new(self)
306    }
307    ///Bit 5 - CPU wakeup with interrupt mask on event input
308    #[inline(always)]
309    #[must_use]
310    pub fn im5(&mut self) -> IM5_W<5> {
311        IM5_W::new(self)
312    }
313    ///Bit 6 - CPU wakeup with interrupt mask on event input
314    #[inline(always)]
315    #[must_use]
316    pub fn im6(&mut self) -> IM6_W<6> {
317        IM6_W::new(self)
318    }
319    ///Bit 7 - CPU wakeup with interrupt mask on event input
320    #[inline(always)]
321    #[must_use]
322    pub fn im7(&mut self) -> IM7_W<7> {
323        IM7_W::new(self)
324    }
325    ///Bit 8 - CPU wakeup with interrupt mask on event input
326    #[inline(always)]
327    #[must_use]
328    pub fn im8(&mut self) -> IM8_W<8> {
329        IM8_W::new(self)
330    }
331    ///Bit 9 - CPU wakeup with interrupt mask on event input
332    #[inline(always)]
333    #[must_use]
334    pub fn im9(&mut self) -> IM9_W<9> {
335        IM9_W::new(self)
336    }
337    ///Bit 10 - CPU wakeup with interrupt mask on event input
338    #[inline(always)]
339    #[must_use]
340    pub fn im10(&mut self) -> IM10_W<10> {
341        IM10_W::new(self)
342    }
343    ///Bit 11 - CPU wakeup with interrupt mask on event input
344    #[inline(always)]
345    #[must_use]
346    pub fn im11(&mut self) -> IM11_W<11> {
347        IM11_W::new(self)
348    }
349    ///Bit 12 - CPU wakeup with interrupt mask on event input
350    #[inline(always)]
351    #[must_use]
352    pub fn im12(&mut self) -> IM12_W<12> {
353        IM12_W::new(self)
354    }
355    ///Bit 13 - CPU wakeup with interrupt mask on event input
356    #[inline(always)]
357    #[must_use]
358    pub fn im13(&mut self) -> IM13_W<13> {
359        IM13_W::new(self)
360    }
361    ///Bit 14 - CPU wakeup with interrupt mask on event input
362    #[inline(always)]
363    #[must_use]
364    pub fn im14(&mut self) -> IM14_W<14> {
365        IM14_W::new(self)
366    }
367    ///Bit 15 - CPU wakeup with interrupt mask on event input
368    #[inline(always)]
369    #[must_use]
370    pub fn im15(&mut self) -> IM15_W<15> {
371        IM15_W::new(self)
372    }
373    ///Bit 16 - CPU wakeup with interrupt mask on event input
374    #[inline(always)]
375    #[must_use]
376    pub fn im16(&mut self) -> IM16_W<16> {
377        IM16_W::new(self)
378    }
379    ///Bit 17 - CPU wakeup with interrupt mask on event input
380    #[inline(always)]
381    #[must_use]
382    pub fn im17(&mut self) -> IM17_W<17> {
383        IM17_W::new(self)
384    }
385    ///Bit 18 - CPU wakeup with interrupt mask on event input
386    #[inline(always)]
387    #[must_use]
388    pub fn im18(&mut self) -> IM18_W<18> {
389        IM18_W::new(self)
390    }
391    ///Bit 19 - CPU wakeup with interrupt mask on event input
392    #[inline(always)]
393    #[must_use]
394    pub fn im19(&mut self) -> IM19_W<19> {
395        IM19_W::new(self)
396    }
397    ///Bit 29 - CPU wakeup with interrupt mask on event input
398    #[inline(always)]
399    #[must_use]
400    pub fn im29(&mut self) -> IM29_W<29> {
401        IM29_W::new(self)
402    }
403    ///Writes raw bits to the register.
404    #[inline(always)]
405    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
406        self.0.bits(bits);
407        self
408    }
409}
410/**EXTI CPU wakeup with interrupt mask register
411
412This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
413
414For information about available fields see [imr](index.html) module*/
415pub struct IMR_SPEC;
416impl crate::RegisterSpec for IMR_SPEC {
417    type Ux = u32;
418}
419///`read()` method returns [imr::R](R) reader structure
420impl crate::Readable for IMR_SPEC {
421    type Reader = R;
422}
423///`write(|w| ..)` method takes [imr::W](W) writer structure
424impl crate::Writable for IMR_SPEC {
425    type Writer = W;
426    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
427    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
428}
429///`reset()` method sets IMR to value 0xfff8_0000
430impl crate::Resettable for IMR_SPEC {
431    const RESET_VALUE: Self::Ux = 0xfff8_0000;
432}
py32f0/py32f002a/exti/imr.rs

py32f0/py32f002a/exti/
imr.rs
