py32f0/py32f030/rcc/
icscr.rs

///Register `ICSCR` reader
pub struct R(crate::R<ICSCR_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<ICSCR_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<ICSCR_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<ICSCR_SPEC>) -> Self {
        R(reader)
    }
}
///Register `ICSCR` writer
pub struct W(crate::W<ICSCR_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<ICSCR_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<ICSCR_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<ICSCR_SPEC>) -> Self {
        W(writer)
    }
}
///Field `HSI_TRIM` reader - HSI clock trimming
pub type HSI_TRIM_R = crate::FieldReader<u16, u16>;
///Field `HSI_TRIM` writer - HSI clock trimming
pub type HSI_TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ICSCR_SPEC, u16, u16, 13, O>;
///Field `HSI_FS` reader - HSI frequency selection
pub type HSI_FS_R = crate::FieldReader<u8, HSI_FS_A>;
/**HSI frequency selection

Value on reset: 0*/
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum HSI_FS_A {
    ///0: Select internal 4 MHz oscilator
    Freq4mhz = 0,
    ///1: Select internal 8 MHz oscilator
    Freq8mhz = 1,
    ///2: Select internal 16 MHz oscilator
    Freq16mhz = 2,
    ///3: Select internal 22.12 MHz oscilator
    Freq2212mhz = 3,
    ///4: Select internal 24 MHz oscilator
    Freq24mhz = 4,
}
impl From<HSI_FS_A> for u8 {
    #[inline(always)]
    fn from(variant: HSI_FS_A) -> Self {
        variant as _
    }
}
impl HSI_FS_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub fn variant(&self) -> Option<HSI_FS_A> {
        match self.bits {
            0 => Some(HSI_FS_A::Freq4mhz),
            1 => Some(HSI_FS_A::Freq8mhz),
            2 => Some(HSI_FS_A::Freq16mhz),
            3 => Some(HSI_FS_A::Freq2212mhz),
            4 => Some(HSI_FS_A::Freq24mhz),
            _ => None,
        }
    }
    ///Checks if the value of the field is `Freq4mhz`
    #[inline(always)]
    pub fn is_freq4mhz(&self) -> bool {
        *self == HSI_FS_A::Freq4mhz
    }
    ///Checks if the value of the field is `Freq8mhz`
    #[inline(always)]
    pub fn is_freq8mhz(&self) -> bool {
        *self == HSI_FS_A::Freq8mhz
    }
    ///Checks if the value of the field is `Freq16mhz`
    #[inline(always)]
    pub fn is_freq16mhz(&self) -> bool {
        *self == HSI_FS_A::Freq16mhz
    }
    ///Checks if the value of the field is `Freq2212mhz`
    #[inline(always)]
    pub fn is_freq22_12mhz(&self) -> bool {
        *self == HSI_FS_A::Freq2212mhz
    }
    ///Checks if the value of the field is `Freq24mhz`
    #[inline(always)]
    pub fn is_freq24mhz(&self) -> bool {
        *self == HSI_FS_A::Freq24mhz
    }
}
///Field `HSI_FS` writer - HSI frequency selection
pub type HSI_FS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ICSCR_SPEC, u8, HSI_FS_A, 3, O>;
impl<'a, const O: u8> HSI_FS_W<'a, O> {
    ///Select internal 4 MHz oscilator
    #[inline(always)]
    pub fn freq4mhz(self) -> &'a mut W {
        self.variant(HSI_FS_A::Freq4mhz)
    }
    ///Select internal 8 MHz oscilator
    #[inline(always)]
    pub fn freq8mhz(self) -> &'a mut W {
        self.variant(HSI_FS_A::Freq8mhz)
    }
    ///Select internal 16 MHz oscilator
    #[inline(always)]
    pub fn freq16mhz(self) -> &'a mut W {
        self.variant(HSI_FS_A::Freq16mhz)
    }
    ///Select internal 22.12 MHz oscilator
    #[inline(always)]
    pub fn freq22_12mhz(self) -> &'a mut W {
        self.variant(HSI_FS_A::Freq2212mhz)
    }
    ///Select internal 24 MHz oscilator
    #[inline(always)]
    pub fn freq24mhz(self) -> &'a mut W {
        self.variant(HSI_FS_A::Freq24mhz)
    }
}
///Field `LSI_TRIM` reader - LSI clock trimming
pub type LSI_TRIM_R = crate::FieldReader<u16, u16>;
///Field `LSI_TRIM` writer - LSI clock trimming
pub type LSI_TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ICSCR_SPEC, u16, u16, 9, O>;
///Field `LSI_STARTUP` reader - LSI startup time
pub type LSI_STARTUP_R = crate::FieldReader<u8, LSI_STARTUP_A>;
/**LSI startup time

Value on reset: 0*/
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum LSI_STARTUP_A {
    ///0: 4 LSI cycles for startup
    Cycles4 = 0,
    ///1: 16 LSI cycles for startup
    Cycles16 = 1,
    ///2: 64 LSI cycles for startup
    Cycles64 = 2,
    ///3: 256 LSI cycles for startup
    Cycles256 = 3,
}
impl From<LSI_STARTUP_A> for u8 {
    #[inline(always)]
    fn from(variant: LSI_STARTUP_A) -> Self {
        variant as _
    }
}
impl LSI_STARTUP_R {
    ///Get enumerated values variant
    #[inline(always)]
    pub fn variant(&self) -> LSI_STARTUP_A {
        match self.bits {
            0 => LSI_STARTUP_A::Cycles4,
            1 => LSI_STARTUP_A::Cycles16,
            2 => LSI_STARTUP_A::Cycles64,
            3 => LSI_STARTUP_A::Cycles256,
            _ => unreachable!(),
        }
    }
    ///Checks if the value of the field is `Cycles4`
    #[inline(always)]
    pub fn is_cycles4(&self) -> bool {
        *self == LSI_STARTUP_A::Cycles4
    }
    ///Checks if the value of the field is `Cycles16`
    #[inline(always)]
    pub fn is_cycles16(&self) -> bool {
        *self == LSI_STARTUP_A::Cycles16
    }
    ///Checks if the value of the field is `Cycles64`
    #[inline(always)]
    pub fn is_cycles64(&self) -> bool {
        *self == LSI_STARTUP_A::Cycles64
    }
    ///Checks if the value of the field is `Cycles256`
    #[inline(always)]
    pub fn is_cycles256(&self) -> bool {
        *self == LSI_STARTUP_A::Cycles256
    }
}
///Field `LSI_STARTUP` writer - LSI startup time
pub type LSI_STARTUP_W<'a, const O: u8> =
    crate::FieldWriterSafe<'a, u32, ICSCR_SPEC, u8, LSI_STARTUP_A, 2, O>;
impl<'a, const O: u8> LSI_STARTUP_W<'a, O> {
    ///4 LSI cycles for startup
    #[inline(always)]
    pub fn cycles4(self) -> &'a mut W {
        self.variant(LSI_STARTUP_A::Cycles4)
    }
    ///16 LSI cycles for startup
    #[inline(always)]
    pub fn cycles16(self) -> &'a mut W {
        self.variant(LSI_STARTUP_A::Cycles16)
    }
    ///64 LSI cycles for startup
    #[inline(always)]
    pub fn cycles64(self) -> &'a mut W {
        self.variant(LSI_STARTUP_A::Cycles64)
    }
    ///256 LSI cycles for startup
    #[inline(always)]
    pub fn cycles256(self) -> &'a mut W {
        self.variant(LSI_STARTUP_A::Cycles256)
    }
}
impl R {
    ///Bits 0:12 - HSI clock trimming
    #[inline(always)]
    pub fn hsi_trim(&self) -> HSI_TRIM_R {
        HSI_TRIM_R::new((self.bits & 0x1fff) as u16)
    }
    ///Bits 13:15 - HSI frequency selection
    #[inline(always)]
    pub fn hsi_fs(&self) -> HSI_FS_R {
        HSI_FS_R::new(((self.bits >> 13) & 7) as u8)
    }
    ///Bits 16:24 - LSI clock trimming
    #[inline(always)]
    pub fn lsi_trim(&self) -> LSI_TRIM_R {
        LSI_TRIM_R::new(((self.bits >> 16) & 0x01ff) as u16)
    }
    ///Bits 26:27 - LSI startup time
    #[inline(always)]
    pub fn lsi_startup(&self) -> LSI_STARTUP_R {
        LSI_STARTUP_R::new(((self.bits >> 26) & 3) as u8)
    }
}
impl W {
    ///Bits 0:12 - HSI clock trimming
    #[inline(always)]
    #[must_use]
    pub fn hsi_trim(&mut self) -> HSI_TRIM_W<0> {
        HSI_TRIM_W::new(self)
    }
    ///Bits 13:15 - HSI frequency selection
    #[inline(always)]
    #[must_use]
    pub fn hsi_fs(&mut self) -> HSI_FS_W<13> {
        HSI_FS_W::new(self)
    }
    ///Bits 16:24 - LSI clock trimming
    #[inline(always)]
    #[must_use]
    pub fn lsi_trim(&mut self) -> LSI_TRIM_W<16> {
        LSI_TRIM_W::new(self)
    }
    ///Bits 26:27 - LSI startup time
    #[inline(always)]
    #[must_use]
    pub fn lsi_startup(&mut self) -> LSI_STARTUP_W<26> {
        LSI_STARTUP_W::new(self)
    }
    ///Writes raw bits to the register.
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
/**Internal clock sources calibration register

This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).

For information about available fields see [icscr](index.html) module*/
pub struct ICSCR_SPEC;
impl crate::RegisterSpec for ICSCR_SPEC {
    type Ux = u32;
}
///`read()` method returns [icscr::R](R) reader structure
impl crate::Readable for ICSCR_SPEC {
    type Reader = R;
}
///`write(|w| ..)` method takes [icscr::W](W) writer structure
impl crate::Writable for ICSCR_SPEC {
    type Writer = W;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
///`reset()` method sets ICSCR to value 0x1000_0000
impl crate::Resettable for ICSCR_SPEC {
    const RESET_VALUE: Self::Ux = 0x1000_0000;
}
py32f0/py32f030/rcc/icscr.rs

py32f0/py32f030/rcc/
icscr.rs
