Re-exports§
pub use self::FlagStatus as ITStatus;
Modules§
Structs§
- ADC_
AnalogWDG Conf Type Def - @brief Structure definition of ADC analog watchdog @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group.
- ADC_
Channel Conf Type Def - @brief Structure definition of ADC channel for regular group @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC state can be either: - For all parameters: ADC disabled or enabled without conversion on going on regular group. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
- ADC_
Common_ Type Def - ADC_
Init Type Def - @brief Structure definition of ADC initialization and regular group @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. ADC state can be either: - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter ‘ClockPrescaler’) - For all parameters except ‘ClockPrescaler’ and ‘resolution’: ADC enabled without conversion on going on regular group. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
- ADC_
Type Def - @brief Analog to Digital Converter
- APSR_
Type__ bindgen_ ty_ 1 - COMP_
Common_ Type Def - COMP_
Type Def - @brief Comparator
- CONTROL_
Type__ bindgen_ ty_ 1 - CRC_
Handle Type Def - @brief CRC Handle Structure definition
- CRC_
Type Def - @brief CRC calculation unit
- DBGMCU_
Type Def - @brief Debug MCU
- DMA_
Channel_ Type Def - DMA_
Init Type Def - @brief DMA Configuration Structure definition
- DMA_
Type Def - @brief DMA Controller
- EXTI_
Config Type Def - @brief EXTI Configuration structure definition
- EXTI_
Handle Type Def - @brief EXTI Handle structure definition
- EXTI_
Type Def - @brief Asynch Interrupt/Event Controller (EXTI)
- FLASH_
Erase Init Type Def - @brief FLASH Erase structure definition
- FLASH_
OBProgram Init Type Def - @brief FLASH Option Bytes PROGRAM structure definition
- FLASH_
Process Type Def - @brief FLASH handle Structure definition
- FLASH_
Type Def - @brief FLASH Registers
- GPIO_
Init Type Def - @defgroup GPIO_Exported_Types GPIO Exported Types @{ / /** @brief GPIO Init structure definition
- GPIO_
Type Def - @brief General Purpose I/O
- I2C_
Init Type Def - @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition @brief I2C Configuration Structure definition @{
- I2C_
Type Def - @brief Inter-integrated Circuit Interface
- IPSR_
Type__ bindgen_ ty_ 1 - IWDG_
Handle Type Def - @brief IWDG Handle Structure definition
- IWDG_
Init Type Def - @brief IWDG Init structure definition
- IWDG_
Type Def - @brief Independent WATCHDOG
- LED_
Handle Type Def - LED_
Init Type Def - @brief LED Init Structure definition
- LED_
Type Def - LPTIM_
Handle Type Def - LPTIM_
Init Type Def - @brief LPTIM Initialization Structure definition
- LPTIM_
Type Def - @brief LPTIMER
- NVIC_
Type - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- OB_
Type Def - @brief Option Bytes
- PWR_
BIAS Config Type Def - @brief PWR BIAS configuration structure definition
- PWR_
PVDType Def - @brief PWR PVD configuration structure definition
- PWR_
Stop Mode Config Type Def - @brief PWR Stop configuration structure definition
- PWR_
Type Def - @brief Power Control
- RCC_
ClkInit Type Def - @brief RCC System, AHB and APB busses clock configuration structure definition
- RCC_
OscInit Type Def - @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
- RCC_
PLLInit Type Def - @brief RCC PLL configuration structure definition
- RCC_
PeriphCLK Init Type Def - @brief RCC extended clocks structure definition
- RCC_
Type Def - @brief Reset and Clock Control
- RTC_
Alarm Type Def - @brief RTC Alarm structure definition
- RTC_
Date Type Def - @brief RTC Date structure definition
- RTC_
Handle Type Def - RTC_
Init Type Def - @brief RTC Configuration Structure definition
- RTC_
Time Type Def - @defgroup RTC_Exported_Types RTC Exported Types @{ / /** @brief RTC Time structure definition
- RTC_
Type Def - @brief Real-Time Clock
- SCB_
Type - \brief Structure type to access the System Control Block (SCB).
- SPI_
Init Type Def - @brief SPI Configuration Structure definition
- SPI_
Type Def - @brief Serial Peripheral Interface
- SYSCFG_
Type Def - @brief System configuration controller
- SysTick_
Type - \brief Structure type to access the System Timer (SysTick).
- TIM_
Base_ Init Type Def - @brief TIM Time base Configuration Structure definition
- TIM_
Break Dead Time Config Type Def - @brief TIM Break input(s) and Dead time configuration Structure definition @note 2 break inputs can be configured (BKIN and BKIN2) with configurable filter and polarity.
- TIM_
Clear Input Config Type Def - @brief TIM Clear Input Configuration Handle Structure definition
- TIM_
Clock Config Type Def - @brief Clock Configuration Handle Structure definition
- TIM_
Encoder_ Init Type Def - @brief TIM Encoder Configuration Structure definition
- TIM_
Hall Sensor_ Init Type Def - @brief TIM Hall sensor Configuration Structure definition
- TIM_
Handle Type Def - TIM_
IC_ Init Type Def - @brief TIM Input Capture Configuration Structure definition
- TIM_
Master Config Type Def - @brief TIM Master configuration Structure definition
- TIM_
OC_ Init Type Def - @brief TIM Output Compare Configuration Structure definition
- TIM_
OnePulse_ Init Type Def - @brief TIM One Pulse Mode Configuration Structure definition
- TIM_
Slave Config Type Def - @brief TIM Slave configuration Structure definition
- TIM_
Type Def - @brief TIM
- UART_
AdvFeature Init Type Def - UART_
Init Type Def - @brief UART Init Structure definition
- USART_
Type Def - @brief Universal Synchronous Asynchronous Receiver Transmitter
- WWDG_
Handle Type Def - WWDG_
Init Type Def - @brief WWDG Init structure definition
- WWDG_
Type Def - @brief Window WATCHDOG
- __
ADC_ Handle Type Def - @brief ADC handle Structure definition
- __
Bindgen Bitfield Unit - __
DMA_ Handle Type Def - @brief DMA handle Structure definition
- __
I2C_ Handle Type Def - @defgroup I2C_handle_Structure_definition I2C handle Structure definition @brief I2C handle Structure definition @{
- __
SPI_ Handle Type Def - @brief SPI handle Structure definition
- __
UART_ Handle Type Def - @brief UART handle Structure definition
- xPSR_
Type__ bindgen_ ty_ 1
Constants§
- ADC
- ADC1
- ADC1_
2_ EXTERNALTRIG_ T1_ CC4 - ADC1_
2_ EXTERNALTRIG_ T1_ TRGO - ADC1_
2_ EXTERNALTRIG_ T3_ TRGO - ADC1_
BASE - ADC1_
COMMON - ADC_
ANALOGWATCHDOG_ ALL_ REG - ADC_
ANALOGWATCHDOG_ NONE - ADC_
ANALOGWATCHDOG_ SINGLE_ REG - ADC_
AWD_ EVENT - ADC_
BASE - ADC_
CALIBSAMPLETIME_ 1CYCLE - ADC_
CALIBSAMPLETIME_ 2CYCLES - ADC_
CALIBSAMPLETIME_ 4CYCLES - ADC_
CALIBSAMPLETIME_ 8CYCLES - ADC_
CALIBSELECTION_ OFFSET_ LINEARITY - ADC_
CALIBSELECTION_ ONLYOFFSET - ADC_
CALIBSTATUS_ FAIL - ADC_
CALIBSTATUS_ INVALID - ADC_
CALIBSTATUS_ ONGOING - ADC_
CALIBSTATUS_ SUCCESS - ADC_
CCR_ ALL - ADC_
CCR_ TSEN - ADC_
CCR_ TSEN_ Msk - ADC_
CCR_ TSEN_ Pos - ADC_
CCR_ VREFEN - ADC_
CCR_ VREFEN_ Msk - ADC_
CCR_ VREFEN_ Pos - ADC_
CCSR_ CALFAIL - ADC_
CCSR_ CALFAIL_ Msk - ADC_
CCSR_ CALFAIL_ Pos - ADC_
CCSR_ CALON - ADC_
CCSR_ CALON_ Msk - ADC_
CCSR_ CALON_ Pos - ADC_
CCSR_ CALSEL - ADC_
CCSR_ CALSEL_ Msk - ADC_
CCSR_ CALSEL_ Pos - ADC_
CCSR_ CALSMP - ADC_
CCSR_ CALSMP_ 0 - ADC_
CCSR_ CALSMP_ 1 - ADC_
CCSR_ CALSMP_ Msk - ADC_
CCSR_ CALSMP_ Pos - ADC_
CFGR1_ ALIGN - ADC_
CFGR1_ ALIGN_ Msk - ADC_
CFGR1_ ALIGN_ Pos - ADC_
CFGR1_ AWDCH - ADC_
CFGR1_ AWDCH_ 0 - ADC_
CFGR1_ AWDCH_ 1 - ADC_
CFGR1_ AWDCH_ 2 - ADC_
CFGR1_ AWDCH_ 3 - ADC_
CFGR1_ AWDCH_ Msk - ADC_
CFGR1_ AWDCH_ Pos - ADC_
CFGR1_ AWDEN - ADC_
CFGR1_ AWDEN_ Msk - ADC_
CFGR1_ AWDEN_ Pos - ADC_
CFGR1_ AWDSGL - ADC_
CFGR1_ AWDSGL_ Msk - ADC_
CFGR1_ AWDSGL_ Pos - ADC_
CFGR1_ CONT - ADC_
CFGR1_ CONT_ Msk - ADC_
CFGR1_ CONT_ Pos - ADC_
CFGR1_ DISCEN - ADC_
CFGR1_ DISCEN_ Msk - ADC_
CFGR1_ DISCEN_ Pos - ADC_
CFGR1_ DMACFG - ADC_
CFGR1_ DMACFG_ Msk - ADC_
CFGR1_ DMACFG_ Pos - ADC_
CFGR1_ DMAEN - ADC_
CFGR1_ DMAEN_ Msk - ADC_
CFGR1_ DMAEN_ Pos - ADC_
CFGR1_ EXTEN - ADC_
CFGR1_ EXTEN_ 0 - ADC_
CFGR1_ EXTEN_ 1 - ADC_
CFGR1_ EXTEN_ Msk - ADC_
CFGR1_ EXTEN_ Pos - ADC_
CFGR1_ EXTSEL - ADC_
CFGR1_ EXTSEL_ 0 - ADC_
CFGR1_ EXTSEL_ 1 - ADC_
CFGR1_ EXTSEL_ 2 - ADC_
CFGR1_ EXTSEL_ Msk - ADC_
CFGR1_ EXTSEL_ Pos - ADC_
CFGR1_ OVRMOD - ADC_
CFGR1_ OVRMOD_ Msk - ADC_
CFGR1_ OVRMOD_ Pos - ADC_
CFGR1_ RESSEL - ADC_
CFGR1_ RESSEL_ 0 - ADC_
CFGR1_ RESSEL_ 1 - ADC_
CFGR1_ RESSEL_ Msk - ADC_
CFGR1_ RESSEL_ Pos - ADC_
CFGR1_ SCANDIR - ADC_
CFGR1_ SCANDIR_ Msk - ADC_
CFGR1_ SCANDIR_ Pos - ADC_
CFGR1_ WAIT - ADC_
CFGR1_ WAIT_ Msk - ADC_
CFGR1_ WAIT_ Pos - ADC_
CFGR2_ CKMODE - ADC_
CFGR2_ CKMODE_ 0 - ADC_
CFGR2_ CKMODE_ 1 - ADC_
CFGR2_ CKMODE_ 2 - ADC_
CFGR2_ CKMODE_ 3 - ADC_
CFGR2_ CKMODE_ Msk - ADC_
CFGR2_ CKMODE_ Pos - ADC_
CHANNEL_ 0 - ADC_
CHANNEL_ 1 - ADC_
CHANNEL_ 2 - ADC_
CHANNEL_ 3 - ADC_
CHANNEL_ 4 - ADC_
CHANNEL_ 5 - ADC_
CHANNEL_ 6 - ADC_
CHANNEL_ 7 - ADC_
CHANNEL_ 8 - ADC_
CHANNEL_ 9 - ADC_
CHANNEL_ 11 - ADC_
CHANNEL_ 12 - ADC_
CHANNEL_ TEMPSENSOR - ADC_
CHANNEL_ VREFINT - ADC_
CHSELR_ CHSEL - ADC_
CHSELR_ CHSE L0 - ADC_
CHSELR_ CHSE L0_ Msk - ADC_
CHSELR_ CHSE L0_ Pos - ADC_
CHSELR_ CHSE L1 - ADC_
CHSELR_ CHSE L2 - ADC_
CHSELR_ CHSE L3 - ADC_
CHSELR_ CHSE L4 - ADC_
CHSELR_ CHSE L5 - ADC_
CHSELR_ CHSE L6 - ADC_
CHSELR_ CHSE L7 - ADC_
CHSELR_ CHSE L8 - ADC_
CHSELR_ CHSE L9 - ADC_
CHSELR_ CHSE L1_ Msk - ADC_
CHSELR_ CHSE L1_ Pos - ADC_
CHSELR_ CHSE L2_ Msk - ADC_
CHSELR_ CHSE L2_ Pos - ADC_
CHSELR_ CHSE L3_ Msk - ADC_
CHSELR_ CHSE L3_ Pos - ADC_
CHSELR_ CHSE L4_ Msk - ADC_
CHSELR_ CHSE L4_ Pos - ADC_
CHSELR_ CHSE L5_ Msk - ADC_
CHSELR_ CHSE L5_ Pos - ADC_
CHSELR_ CHSE L6_ Msk - ADC_
CHSELR_ CHSE L6_ Pos - ADC_
CHSELR_ CHSE L7_ Msk - ADC_
CHSELR_ CHSE L7_ Pos - ADC_
CHSELR_ CHSE L8_ Msk - ADC_
CHSELR_ CHSE L8_ Pos - ADC_
CHSELR_ CHSE L9_ Msk - ADC_
CHSELR_ CHSE L9_ Pos - ADC_
CHSELR_ CHSE L11 - ADC_
CHSELR_ CHSE L12 - ADC_
CHSELR_ CHSE L11_ Msk - ADC_
CHSELR_ CHSE L11_ Pos - ADC_
CHSELR_ CHSE L12_ Msk - ADC_
CHSELR_ CHSE L12_ Pos - ADC_
CHSELR_ CHSEL_ Msk - ADC_
CHSELR_ CHSEL_ Pos - ADC_
CLOCK_ ASYNC_ HSI_ DIV1 - ADC_
CLOCK_ ASYNC_ HSI_ DIV2 - ADC_
CLOCK_ ASYNC_ HSI_ DIV4 - ADC_
CLOCK_ ASYNC_ HSI_ DIV8 - ADC_
CLOCK_ ASYNC_ HSI_ DIV16 - ADC_
CLOCK_ ASYNC_ HSI_ DIV32 - ADC_
CLOCK_ ASYNC_ HSI_ DIV64 - ADC_
CLOCK_ SYNC_ PCLK_ DIV1 - ADC_
CLOCK_ SYNC_ PCLK_ DIV2 - ADC_
CLOCK_ SYNC_ PCLK_ DIV4 - ADC_
CLOCK_ SYNC_ PCLK_ DIV8 - ADC_
CLOCK_ SYNC_ PCLK_ DIV16 - ADC_
CLOCK_ SYNC_ PCLK_ DIV32 - ADC_
CLOCK_ SYNC_ PCLK_ DIV64 - ADC_
CR_ ADCAL - ADC_
CR_ ADCAL_ Msk - ADC_
CR_ ADCAL_ Pos - ADC_
CR_ ADEN - ADC_
CR_ ADEN_ Msk - ADC_
CR_ ADEN_ Pos - ADC_
CR_ ADSTART - ADC_
CR_ ADSTART_ Msk - ADC_
CR_ ADSTART_ Pos - ADC_
CR_ ADSTP - ADC_
CR_ ADSTP_ Msk - ADC_
CR_ ADSTP_ Pos - ADC_
DATAALIGN_ LEFT - ADC_
DATAALIGN_ RIGHT - ADC_
DR_ DATA - ADC_
DR_ DATA_ 0 - ADC_
DR_ DATA_ 1 - ADC_
DR_ DATA_ 2 - ADC_
DR_ DATA_ 3 - ADC_
DR_ DATA_ 4 - ADC_
DR_ DATA_ 5 - ADC_
DR_ DATA_ 6 - ADC_
DR_ DATA_ 7 - ADC_
DR_ DATA_ 8 - ADC_
DR_ DATA_ 9 - ADC_
DR_ DATA_ 10 - ADC_
DR_ DATA_ 11 - ADC_
DR_ DATA_ 12 - ADC_
DR_ DATA_ 13 - ADC_
DR_ DATA_ 14 - ADC_
DR_ DATA_ 15 - ADC_
DR_ DATA_ Msk - ADC_
DR_ DATA_ Pos - ADC_
EOC_ SEQ_ CONV - ADC_
EOC_ SINGLE_ CONV - ADC_
EXTERNALTRIGCONVEDGE_ FALLING - ADC_
EXTERNALTRIGCONVEDGE_ NONE - ADC_
EXTERNALTRIGCONVEDGE_ RISING - ADC_
EXTERNALTRIGCONVEDGE_ RISINGFALLING - ADC_
EXTERNALTRIGCONV_ T1_ CC4 - ADC_
EXTERNALTRIGCONV_ T1_ TRGO - ADC_
EXTERNALTRIGCONV_ T3_ TRGO - ADC_
FLAG_ AWD - ADC_
FLAG_ EOC - ADC_
FLAG_ EOS - ADC_
FLAG_ EOSMP - ADC_
FLAG_ OVR - ADC_
FLAG_ POSTCONV_ ALL - ADC_
IER_ AWDIE - ADC_
IER_ AWDIE_ Msk - ADC_
IER_ AWDIE_ Pos - ADC_
IER_ EOCIE - ADC_
IER_ EOCIE_ Msk - ADC_
IER_ EOCIE_ Pos - ADC_
IER_ EOSEQIE - ADC_
IER_ EOSEQIE_ Msk - ADC_
IER_ EOSEQIE_ Pos - ADC_
IER_ EOSMPIE - ADC_
IER_ EOSMPIE_ Msk - ADC_
IER_ EOSMPIE_ Pos - ADC_
IER_ OVRIE - ADC_
IER_ OVRIE_ Msk - ADC_
IER_ OVRIE_ Pos - ADC_
ISR_ AWD - ADC_
ISR_ AWD_ Msk - ADC_
ISR_ AWD_ Pos - ADC_
ISR_ EOC - ADC_
ISR_ EOC_ Msk - ADC_
ISR_ EOC_ Pos - ADC_
ISR_ EOSEQ - ADC_
ISR_ EOSEQ_ Msk - ADC_
ISR_ EOSEQ_ Pos - ADC_
ISR_ EOSMP - ADC_
ISR_ EOSMP_ Msk - ADC_
ISR_ EOSMP_ Pos - ADC_
ISR_ OVR - ADC_
ISR_ OVR_ Msk - ADC_
ISR_ OVR_ Pos - ADC_
IT_ AWD - ADC_
IT_ EOC - ADC_
IT_ EOS - ADC_
IT_ EOSMP - ADC_
IT_ OVR - ADC_
OVR_ DATA_ OVERWRITTEN - ADC_
OVR_ DATA_ PRESERVED - ADC_
OVR_ EVENT - ADC_
RANK_ CHANNEL_ NUMBER - ADC_
RANK_ NONE - ADC_
RESOLUTION_ 6B - ADC_
RESOLUTION_ 8B - ADC_
RESOLUTION_ 10B - ADC_
RESOLUTION_ 12B - ADC_
SAMPLETIME_ 3CYCLES_ 5 - ADC_
SAMPLETIME_ 5CYCLES_ 5 - ADC_
SAMPLETIME_ 7CYCLES_ 5 - ADC_
SAMPLETIME_ 13CYCLES_ 5 - ADC_
SAMPLETIME_ 28CYCLES_ 5 - ADC_
SAMPLETIME_ 41CYCLES_ 5 - ADC_
SAMPLETIME_ 71CYCLES_ 5 - ADC_
SAMPLETIME_ 239CYCLES_ 5 - ADC_
SCAN_ DIRECTION_ BACKWARD - ADC_
SCAN_ DIRECTION_ FORWARD - ADC_
SCAN_ ENABLE - ADC_
SMPR_ SMP - ADC_
SMPR_ SMP_ 0 - ADC_
SMPR_ SMP_ 1 - ADC_
SMPR_ SMP_ 2 - ADC_
SMPR_ SMP_ Msk - ADC_
SMPR_ SMP_ Pos - ADC_
SOFTWARE_ START - ADC_
TR_ HT - ADC_
TR_ HT_ 0 - ADC_
TR_ HT_ 1 - ADC_
TR_ HT_ 2 - ADC_
TR_ HT_ 3 - ADC_
TR_ HT_ 4 - ADC_
TR_ HT_ 5 - ADC_
TR_ HT_ 6 - ADC_
TR_ HT_ 7 - ADC_
TR_ HT_ 8 - ADC_
TR_ HT_ 9 - ADC_
TR_ HT_ 10 - ADC_
TR_ HT_ 11 - ADC_
TR_ HT_ Msk - ADC_
TR_ HT_ Pos - ADC_
TR_ LT - ADC_
TR_ LT_ 0 - ADC_
TR_ LT_ 1 - ADC_
TR_ LT_ 2 - ADC_
TR_ LT_ 3 - ADC_
TR_ LT_ 4 - ADC_
TR_ LT_ 5 - ADC_
TR_ LT_ 6 - ADC_
TR_ LT_ 7 - ADC_
TR_ LT_ 8 - ADC_
TR_ LT_ 9 - ADC_
TR_ LT_ 10 - ADC_
TR_ LT_ 11 - ADC_
TR_ LT_ Msk - ADC_
TR_ LT_ Pos - AHBPERIPH_
BASE - APBPERIPH_
BASE - APSR_
C_ Msk - APSR_
C_ Pos - APSR_
N_ Msk - APSR_
N_ Pos - APSR_
V_ Msk - APSR_
V_ Pos - APSR_
Z_ Msk - APSR_
Z_ Pos - BDCR_
REG_ INDEX - BKP_
RTCCR_ ASOE - BKP_
RTCCR_ ASOE_ Msk - BKP_
RTCCR_ ASOE_ Pos - BKP_
RTCCR_ ASOS - BKP_
RTCCR_ ASOS_ Msk - BKP_
RTCCR_ ASOS_ Pos - BKP_
RTCCR_ CAL - BKP_
RTCCR_ CAL_ 0 - BKP_
RTCCR_ CAL_ 1 - BKP_
RTCCR_ CAL_ 2 - BKP_
RTCCR_ CAL_ 3 - BKP_
RTCCR_ CAL_ 4 - BKP_
RTCCR_ CAL_ 5 - BKP_
RTCCR_ CAL_ 6 - BKP_
RTCCR_ CAL_ Msk - BKP_
RTCCR_ CAL_ Pos - BKP_
RTCCR_ CCO - BKP_
RTCCR_ CCO_ Msk - BKP_
RTCCR_ CCO_ Pos - COMP1
- COMP2
- COMP1_
BASE - COMP2_
BASE - COMP12_
COMMON - COMP_
CSR_ COMP1_ EN - COMP_
CSR_ COMP2_ EN - COMP_
CSR_ COMP_ OUT - COMP_
CSR_ COMP_ OUT_ Msk - COMP_
CSR_ COMP_ OUT_ Pos - COMP_
CSR_ EN - COMP_
CSR_ EN_ Msk - COMP_
CSR_ EN_ Pos - COMP_
CSR_ HYST - COMP_
CSR_ HYST_ Msk - COMP_
CSR_ HYST_ Pos - COMP_
CSR_ INMSEL - COMP_
CSR_ INMSEL_ 0 - COMP_
CSR_ INMSEL_ 1 - COMP_
CSR_ INMSEL_ 2 - COMP_
CSR_ INMSEL_ 3 - COMP_
CSR_ INMSEL_ Msk - COMP_
CSR_ INMSEL_ Pos - COMP_
CSR_ INPSEL - COMP_
CSR_ INPSEL_ 0 - COMP_
CSR_ INPSEL_ 1 - COMP_
CSR_ INPSEL_ Msk - COMP_
CSR_ INPSEL_ Pos - COMP_
CSR_ LOCK - COMP_
CSR_ LOCK_ Msk - COMP_
CSR_ LOCK_ Pos - COMP_
CSR_ POLARITY - COMP_
CSR_ POLARITY_ Msk - COMP_
CSR_ POLARITY_ Pos - COMP_
CSR_ PWRMODE - COMP_
CSR_ PWRMODE_ 0 - COMP_
CSR_ PWRMODE_ 1 - COMP_
CSR_ PWRMODE_ Msk - COMP_
CSR_ PWRMODE_ Pos - COMP_
CSR_ SCALER_ EN - COMP_
CSR_ SCALER_ EN_ Msk - COMP_
CSR_ SCALER_ EN_ Pos - COMP_
CSR_ WINMODE - COMP_
CSR_ WINMODE_ Msk - COMP_
CSR_ WINMODE_ Pos - COMP_
FR_ FLTCNT - COMP_
FR_ FLTCNT_ Msk - COMP_
FR_ FLTCNT_ Pos - COMP_
FR_ FLTEN - COMP_
FR_ FLTEN_ Msk - COMP_
FR_ FLTEN_ Pos - CONTROL_
SPSEL_ Msk - CONTROL_
SPSEL_ Pos - CONTROL_
nPRIV_ Msk - CONTROL_
nPRIV_ Pos - CRC
- CRC_
BASE - CRC_
CR_ RESET - CRC_
CR_ RESET_ Msk - CRC_
CR_ RESET_ Pos - CRC_
DR_ DR - CRC_
DR_ DR_ Msk - CRC_
DR_ DR_ Pos - CRC_
IDR_ IDR - CRC_
IDR_ IDR_ Msk - CRC_
IDR_ IDR_ Pos - CR_
REG_ INDEX - CSR_
REG_ INDEX - DBGMCU
- DBGMCU_
APB_ FZ1_ DBG_ IWDG_ STOP - DBGMCU_
APB_ FZ1_ DBG_ IWDG_ STOP_ Msk - DBGMCU_
APB_ FZ1_ DBG_ IWDG_ STOP_ Pos - DBGMCU_
APB_ FZ1_ DBG_ LPTIM_ STOP - DBGMCU_
APB_ FZ1_ DBG_ LPTIM_ STOP_ Msk - DBGMCU_
APB_ FZ1_ DBG_ LPTIM_ STOP_ Pos - DBGMCU_
APB_ FZ1_ DBG_ RTC_ STOP - DBGMCU_
APB_ FZ1_ DBG_ RTC_ STOP_ Msk - DBGMCU_
APB_ FZ1_ DBG_ RTC_ STOP_ Pos - DBGMCU_
APB_ FZ1_ DBG_ TIM3_ STOP - DBGMCU_
APB_ FZ1_ DBG_ TIM3_ STOP_ Msk - DBGMCU_
APB_ FZ1_ DBG_ TIM3_ STOP_ Pos - DBGMCU_
APB_ FZ1_ DBG_ WWDG_ STOP - DBGMCU_
APB_ FZ1_ DBG_ WWDG_ STOP_ Msk - DBGMCU_
APB_ FZ1_ DBG_ WWDG_ STOP_ Pos - DBGMCU_
APB_ FZ2_ DBG_ TIM1_ STOP - DBGMCU_
APB_ FZ2_ DBG_ TIM1_ STOP_ Msk - DBGMCU_
APB_ FZ2_ DBG_ TIM1_ STOP_ Pos - DBGMCU_
APB_ FZ2_ DBG_ TIM14_ STOP - DBGMCU_
APB_ FZ2_ DBG_ TIM14_ STOP_ Msk - DBGMCU_
APB_ FZ2_ DBG_ TIM14_ STOP_ Pos - DBGMCU_
APB_ FZ2_ DBG_ TIM16_ STOP - DBGMCU_
APB_ FZ2_ DBG_ TIM16_ STOP_ Msk - DBGMCU_
APB_ FZ2_ DBG_ TIM16_ STOP_ Pos - DBGMCU_
APB_ FZ2_ DBG_ TIM17_ STOP - DBGMCU_
APB_ FZ2_ DBG_ TIM17_ STOP_ Msk - DBGMCU_
APB_ FZ2_ DBG_ TIM17_ STOP_ Pos - DBGMCU_
BASE - DBGMCU_
CR_ DBG_ STOP - DBGMCU_
CR_ DBG_ STOP_ Msk - DBGMCU_
CR_ DBG_ STOP_ Pos - DBGMCU_
IDCODE_ DEV_ ID - DBGMCU_
IDCODE_ DEV_ ID_ Msk - DBGMCU_
IDCODE_ DEV_ ID_ Pos - DBGMCU_
IDCODE_ REV_ ID - DBGMCU_
IDCODE_ REV_ ID_ Msk - DBGMCU_
IDCODE_ REV_ ID_ Pos - DMA1
- DMA1_
BASE - DMA1_
Channel1 - DMA1_
Channel2 - DMA1_
Channel3 - DMA1_
Channel1_ BASE - DMA1_
Channel2_ BASE - DMA1_
Channel3_ BASE - DMA_
CCR_ CIRC - DMA_
CCR_ CIRC_ Msk - DMA_
CCR_ CIRC_ Pos - DMA_
CCR_ DIR - DMA_
CCR_ DIR_ Msk - DMA_
CCR_ DIR_ Pos - DMA_
CCR_ EN - DMA_
CCR_ EN_ Msk - DMA_
CCR_ EN_ Pos - DMA_
CCR_ HTIE - DMA_
CCR_ HTIE_ Msk - DMA_
CCR_ HTIE_ Pos - DMA_
CCR_ MEM2MEM - DMA_
CCR_ MEM2MEM_ Msk - DMA_
CCR_ MEM2MEM_ Pos - DMA_
CCR_ MINC - DMA_
CCR_ MINC_ Msk - DMA_
CCR_ MINC_ Pos - DMA_
CCR_ MSIZE - DMA_
CCR_ MSIZE_ 0 - DMA_
CCR_ MSIZE_ 1 - DMA_
CCR_ MSIZE_ Msk - DMA_
CCR_ MSIZE_ Pos - DMA_
CCR_ PINC - DMA_
CCR_ PINC_ Msk - DMA_
CCR_ PINC_ Pos - DMA_
CCR_ PL - DMA_
CCR_ PL_ 0 - DMA_
CCR_ PL_ 1 - DMA_
CCR_ PL_ Msk - DMA_
CCR_ PL_ Pos - DMA_
CCR_ PSIZE - DMA_
CCR_ PSIZE_ 0 - DMA_
CCR_ PSIZE_ 1 - DMA_
CCR_ PSIZE_ Msk - DMA_
CCR_ PSIZE_ Pos - DMA_
CCR_ TCIE - DMA_
CCR_ TCIE_ Msk - DMA_
CCR_ TCIE_ Pos - DMA_
CCR_ TEIE - DMA_
CCR_ TEIE_ Msk - DMA_
CCR_ TEIE_ Pos - DMA_
CHANNEL_ MAP_ ADC - DMA_
CHANNEL_ MAP_ END - DMA_
CHANNEL_ MAP_ I2C_ RX - DMA_
CHANNEL_ MAP_ I2C_ TX - DMA_
CHANNEL_ MAP_ SPI1_ RX - DMA_
CHANNEL_ MAP_ SPI1_ TX - DMA_
CHANNEL_ MAP_ SPI2_ RX - DMA_
CHANNEL_ MAP_ SPI2_ TX - DMA_
CHANNEL_ MAP_ TIM1_ CH1 - DMA_
CHANNEL_ MAP_ TIM1_ CH2 - DMA_
CHANNEL_ MAP_ TIM1_ CH3 - DMA_
CHANNEL_ MAP_ TIM1_ CH4 - DMA_
CHANNEL_ MAP_ TIM1_ COM - DMA_
CHANNEL_ MAP_ TIM1_ TRIG - DMA_
CHANNEL_ MAP_ TIM1_ UP - DMA_
CHANNEL_ MAP_ TIM3_ CH1 - DMA_
CHANNEL_ MAP_ TIM3_ CH3 - DMA_
CHANNEL_ MAP_ TIM3_ CH4 - DMA_
CHANNEL_ MAP_ TIM3_ TRIG - DMA_
CHANNEL_ MAP_ TIM3_ UP - DMA_
CHANNEL_ MAP_ TIM16_ CH1 - DMA_
CHANNEL_ MAP_ TIM16_ UP - DMA_
CHANNEL_ MAP_ TIM17_ CH1 - DMA_
CHANNEL_ MAP_ TIM17_ UP - DMA_
CHANNEL_ MAP_ USAR T1_ RX - DMA_
CHANNEL_ MAP_ USAR T1_ TX - DMA_
CHANNEL_ MAP_ USAR T2_ RX - DMA_
CHANNEL_ MAP_ USAR T2_ TX - DMA_
CIRCULAR - DMA_
CMAR_ MA - DMA_
CMAR_ MA_ Msk - DMA_
CMAR_ MA_ Pos - DMA_
CNDTR_ NDT - DMA_
CNDTR_ NDT_ Msk - DMA_
CNDTR_ NDT_ Pos - DMA_
CPAR_ PA - DMA_
CPAR_ PA_ Msk - DMA_
CPAR_ PA_ Pos - DMA_
FLAG_ GL1 - DMA_
FLAG_ GL2 - DMA_
FLAG_ GL3 - DMA_
FLAG_ HT1 - DMA_
FLAG_ HT2 - DMA_
FLAG_ HT3 - DMA_
FLAG_ TC1 - DMA_
FLAG_ TC2 - DMA_
FLAG_ TC3 - DMA_
FLAG_ TE1 - DMA_
FLAG_ TE2 - DMA_
FLAG_ TE3 - DMA_
IFCR_ CGIF1 - DMA_
IFCR_ CGIF2 - DMA_
IFCR_ CGIF3 - DMA_
IFCR_ CGIF1_ Msk - DMA_
IFCR_ CGIF1_ Pos - DMA_
IFCR_ CGIF2_ Msk - DMA_
IFCR_ CGIF2_ Pos - DMA_
IFCR_ CGIF3_ Msk - DMA_
IFCR_ CGIF3_ Pos - DMA_
IFCR_ CHTI F1 - DMA_
IFCR_ CHTI F2 - DMA_
IFCR_ CHTI F3 - DMA_
IFCR_ CHTI F1_ Msk - DMA_
IFCR_ CHTI F1_ Pos - DMA_
IFCR_ CHTI F2_ Msk - DMA_
IFCR_ CHTI F2_ Pos - DMA_
IFCR_ CHTI F3_ Msk - DMA_
IFCR_ CHTI F3_ Pos - DMA_
IFCR_ CTCI F1 - DMA_
IFCR_ CTCI F2 - DMA_
IFCR_ CTCI F3 - DMA_
IFCR_ CTCI F1_ Msk - DMA_
IFCR_ CTCI F1_ Pos - DMA_
IFCR_ CTCI F2_ Msk - DMA_
IFCR_ CTCI F2_ Pos - DMA_
IFCR_ CTCI F3_ Msk - DMA_
IFCR_ CTCI F3_ Pos - DMA_
IFCR_ CTEI F1 - DMA_
IFCR_ CTEI F2 - DMA_
IFCR_ CTEI F3 - DMA_
IFCR_ CTEI F1_ Msk - DMA_
IFCR_ CTEI F1_ Pos - DMA_
IFCR_ CTEI F2_ Msk - DMA_
IFCR_ CTEI F2_ Pos - DMA_
IFCR_ CTEI F3_ Msk - DMA_
IFCR_ CTEI F3_ Pos - DMA_
ISR_ GIF1 - DMA_
ISR_ GIF2 - DMA_
ISR_ GIF3 - DMA_
ISR_ GIF1_ Msk - DMA_
ISR_ GIF1_ Pos - DMA_
ISR_ GIF2_ Msk - DMA_
ISR_ GIF2_ Pos - DMA_
ISR_ GIF3_ Msk - DMA_
ISR_ GIF3_ Pos - DMA_
ISR_ HTIF1 - DMA_
ISR_ HTIF2 - DMA_
ISR_ HTIF3 - DMA_
ISR_ HTIF1_ Msk - DMA_
ISR_ HTIF1_ Pos - DMA_
ISR_ HTIF2_ Msk - DMA_
ISR_ HTIF2_ Pos - DMA_
ISR_ HTIF3_ Msk - DMA_
ISR_ HTIF3_ Pos - DMA_
ISR_ TCIF1 - DMA_
ISR_ TCIF2 - DMA_
ISR_ TCIF3 - DMA_
ISR_ TCIF1_ Msk - DMA_
ISR_ TCIF1_ Pos - DMA_
ISR_ TCIF2_ Msk - DMA_
ISR_ TCIF2_ Pos - DMA_
ISR_ TCIF3_ Msk - DMA_
ISR_ TCIF3_ Pos - DMA_
ISR_ TEIF1 - DMA_
ISR_ TEIF2 - DMA_
ISR_ TEIF3 - DMA_
ISR_ TEIF1_ Msk - DMA_
ISR_ TEIF1_ Pos - DMA_
ISR_ TEIF2_ Msk - DMA_
ISR_ TEIF2_ Pos - DMA_
ISR_ TEIF3_ Msk - DMA_
ISR_ TEIF3_ Pos - DMA_
IT_ HT - DMA_
IT_ TC - DMA_
IT_ TE - DMA_
MDATAALIGN_ BYTE - DMA_
MDATAALIGN_ HALFWORD - DMA_
MDATAALIGN_ WORD - DMA_
MEMORY_ TO_ MEMORY - DMA_
MEMORY_ TO_ PERIPH - DMA_
MINC_ DISABLE - DMA_
MINC_ ENABLE - DMA_
NORMAL - DMA_
PDATAALIGN_ BYTE - DMA_
PDATAALIGN_ HALFWORD - DMA_
PDATAALIGN_ WORD - DMA_
PERIPH_ TO_ MEMORY - DMA_
PINC_ DISABLE - DMA_
PINC_ ENABLE - DMA_
PRIORITY_ HIGH - DMA_
PRIORITY_ LOW - DMA_
PRIORITY_ MEDIUM - DMA_
PRIORITY_ VERY_ HIGH - EXTI
- EXTI_
BASE - EXTI_
CONFIG - EXTI_
CallbackID Type Def_ HAL_ EXTI_ COMMON_ CB_ ID - EXTI_
DIRECT - EXTI_
EMR_ EM - EXTI_
EMR_ EM0 - EXTI_
EMR_ EM0_ Msk - EXTI_
EMR_ EM0_ Pos - EXTI_
EMR_ EM1 - EXTI_
EMR_ EM2 - EXTI_
EMR_ EM3 - EXTI_
EMR_ EM4 - EXTI_
EMR_ EM5 - EXTI_
EMR_ EM6 - EXTI_
EMR_ EM7 - EXTI_
EMR_ EM8 - EXTI_
EMR_ EM9 - EXTI_
EMR_ EM1_ Msk - EXTI_
EMR_ EM1_ Pos - EXTI_
EMR_ EM2_ Msk - EXTI_
EMR_ EM2_ Pos - EXTI_
EMR_ EM3_ Msk - EXTI_
EMR_ EM3_ Pos - EXTI_
EMR_ EM4_ Msk - EXTI_
EMR_ EM4_ Pos - EXTI_
EMR_ EM5_ Msk - EXTI_
EMR_ EM5_ Pos - EXTI_
EMR_ EM6_ Msk - EXTI_
EMR_ EM6_ Pos - EXTI_
EMR_ EM7_ Msk - EXTI_
EMR_ EM7_ Pos - EXTI_
EMR_ EM8_ Msk - EXTI_
EMR_ EM8_ Pos - EXTI_
EMR_ EM9_ Msk - EXTI_
EMR_ EM9_ Pos - EXTI_
EMR_ EM10 - EXTI_
EMR_ EM11 - EXTI_
EMR_ EM12 - EXTI_
EMR_ EM13 - EXTI_
EMR_ EM14 - EXTI_
EMR_ EM15 - EXTI_
EMR_ EM16 - EXTI_
EMR_ EM17 - EXTI_
EMR_ EM18 - EXTI_
EMR_ EM19 - EXTI_
EMR_ EM29 - EXTI_
EMR_ EM10_ Msk - EXTI_
EMR_ EM10_ Pos - EXTI_
EMR_ EM11_ Msk - EXTI_
EMR_ EM11_ Pos - EXTI_
EMR_ EM12_ Msk - EXTI_
EMR_ EM12_ Pos - EXTI_
EMR_ EM13_ Msk - EXTI_
EMR_ EM13_ Pos - EXTI_
EMR_ EM14_ Msk - EXTI_
EMR_ EM14_ Pos - EXTI_
EMR_ EM15_ Msk - EXTI_
EMR_ EM15_ Pos - EXTI_
EMR_ EM16_ Msk - EXTI_
EMR_ EM16_ Pos - EXTI_
EMR_ EM17_ Msk - EXTI_
EMR_ EM17_ Pos - EXTI_
EMR_ EM18_ Msk - EXTI_
EMR_ EM18_ Pos - EXTI_
EMR_ EM19_ Msk - EXTI_
EMR_ EM19_ Pos - EXTI_
EMR_ EM29_ Msk - EXTI_
EMR_ EM29_ Pos - EXTI_
EMR_ EM_ Msk - EXTI_
EMR_ EM_ Pos - EXTI_
EXTIC R1_ EXTI0 - EXTI_
EXTIC R1_ EXTI0_ 0 - EXTI_
EXTIC R1_ EXTI0_ 1 - EXTI_
EXTIC R1_ EXTI0_ Msk - EXTI_
EXTIC R1_ EXTI0_ Pos - EXTI_
EXTIC R1_ EXTI1 - EXTI_
EXTIC R1_ EXTI2 - EXTI_
EXTIC R1_ EXTI3 - EXTI_
EXTIC R1_ EXTI1_ 0 - EXTI_
EXTIC R1_ EXTI1_ 1 - EXTI_
EXTIC R1_ EXTI1_ Msk - EXTI_
EXTIC R1_ EXTI1_ Pos - EXTI_
EXTIC R1_ EXTI2_ 0 - EXTI_
EXTIC R1_ EXTI2_ 1 - EXTI_
EXTIC R1_ EXTI2_ Msk - EXTI_
EXTIC R1_ EXTI2_ Pos - EXTI_
EXTIC R1_ EXTI3_ 0 - EXTI_
EXTIC R1_ EXTI3_ 1 - EXTI_
EXTIC R1_ EXTI3_ Msk - EXTI_
EXTIC R1_ EXTI3_ Pos - EXTI_
EXTIC R2_ EXTI4 - EXTI_
EXTIC R2_ EXTI5 - EXTI_
EXTIC R2_ EXTI6 - EXTI_
EXTIC R2_ EXTI7 - EXTI_
EXTIC R2_ EXTI4_ 0 - EXTI_
EXTIC R2_ EXTI4_ 1 - EXTI_
EXTIC R2_ EXTI4_ Msk - EXTI_
EXTIC R2_ EXTI4_ Pos - EXTI_
EXTIC R2_ EXTI5_ Msk - EXTI_
EXTIC R2_ EXTI5_ Pos - EXTI_
EXTIC R2_ EXTI6_ Msk - EXTI_
EXTIC R2_ EXTI6_ Pos - EXTI_
EXTIC R2_ EXTI7_ Msk - EXTI_
EXTIC R2_ EXTI7_ Pos - EXTI_
EXTIC R3_ EXTI8 - EXTI_
EXTIC R3_ EXTI8_ Msk - EXTI_
EXTIC R3_ EXTI8_ Pos - EXTI_
FTSR_ FT0 - EXTI_
FTSR_ FT0_ Msk - EXTI_
FTSR_ FT0_ Pos - EXTI_
FTSR_ FT1 - EXTI_
FTSR_ FT2 - EXTI_
FTSR_ FT3 - EXTI_
FTSR_ FT4 - EXTI_
FTSR_ FT5 - EXTI_
FTSR_ FT6 - EXTI_
FTSR_ FT7 - EXTI_
FTSR_ FT8 - EXTI_
FTSR_ FT9 - EXTI_
FTSR_ FT1_ Msk - EXTI_
FTSR_ FT1_ Pos - EXTI_
FTSR_ FT2_ Msk - EXTI_
FTSR_ FT2_ Pos - EXTI_
FTSR_ FT3_ Msk - EXTI_
FTSR_ FT3_ Pos - EXTI_
FTSR_ FT4_ Msk - EXTI_
FTSR_ FT4_ Pos - EXTI_
FTSR_ FT5_ Msk - EXTI_
FTSR_ FT5_ Pos - EXTI_
FTSR_ FT6_ Msk - EXTI_
FTSR_ FT6_ Pos - EXTI_
FTSR_ FT7_ Msk - EXTI_
FTSR_ FT7_ Pos - EXTI_
FTSR_ FT8_ Msk - EXTI_
FTSR_ FT8_ Pos - EXTI_
FTSR_ FT9_ Msk - EXTI_
FTSR_ FT9_ Pos - EXTI_
FTSR_ FT10 - EXTI_
FTSR_ FT11 - EXTI_
FTSR_ FT12 - EXTI_
FTSR_ FT13 - EXTI_
FTSR_ FT14 - EXTI_
FTSR_ FT15 - EXTI_
FTSR_ FT16 - EXTI_
FTSR_ FT17 - EXTI_
FTSR_ FT18 - EXTI_
FTSR_ FT10_ Msk - EXTI_
FTSR_ FT10_ Pos - EXTI_
FTSR_ FT11_ Msk - EXTI_
FTSR_ FT11_ Pos - EXTI_
FTSR_ FT12_ Msk - EXTI_
FTSR_ FT12_ Pos - EXTI_
FTSR_ FT13_ Msk - EXTI_
FTSR_ FT13_ Pos - EXTI_
FTSR_ FT14_ Msk - EXTI_
FTSR_ FT14_ Pos - EXTI_
FTSR_ FT15_ Msk - EXTI_
FTSR_ FT15_ Pos - EXTI_
FTSR_ FT16_ Msk - EXTI_
FTSR_ FT16_ Pos - EXTI_
FTSR_ FT17_ Msk - EXTI_
FTSR_ FT17_ Pos - EXTI_
FTSR_ FT18_ Msk - EXTI_
FTSR_ FT18_ Pos - EXTI_
GPIO - EXTI_
GPIOA - EXTI_
GPIOB - EXTI_
GPIOF - EXTI_
IMR_ IM - EXTI_
IMR_ IM0 - EXTI_
IMR_ IM0_ Msk - EXTI_
IMR_ IM0_ Pos - EXTI_
IMR_ IM1 - EXTI_
IMR_ IM2 - EXTI_
IMR_ IM3 - EXTI_
IMR_ IM4 - EXTI_
IMR_ IM5 - EXTI_
IMR_ IM6 - EXTI_
IMR_ IM7 - EXTI_
IMR_ IM8 - EXTI_
IMR_ IM9 - EXTI_
IMR_ IM1_ Msk - EXTI_
IMR_ IM1_ Pos - EXTI_
IMR_ IM2_ Msk - EXTI_
IMR_ IM2_ Pos - EXTI_
IMR_ IM3_ Msk - EXTI_
IMR_ IM3_ Pos - EXTI_
IMR_ IM4_ Msk - EXTI_
IMR_ IM4_ Pos - EXTI_
IMR_ IM5_ Msk - EXTI_
IMR_ IM5_ Pos - EXTI_
IMR_ IM6_ Msk - EXTI_
IMR_ IM6_ Pos - EXTI_
IMR_ IM7_ Msk - EXTI_
IMR_ IM7_ Pos - EXTI_
IMR_ IM8_ Msk - EXTI_
IMR_ IM8_ Pos - EXTI_
IMR_ IM9_ Msk - EXTI_
IMR_ IM9_ Pos - EXTI_
IMR_ IM10 - EXTI_
IMR_ IM11 - EXTI_
IMR_ IM12 - EXTI_
IMR_ IM13 - EXTI_
IMR_ IM14 - EXTI_
IMR_ IM15 - EXTI_
IMR_ IM16 - EXTI_
IMR_ IM17 - EXTI_
IMR_ IM18 - EXTI_
IMR_ IM19 - EXTI_
IMR_ IM29 - EXTI_
IMR_ IM10_ Msk - EXTI_
IMR_ IM10_ Pos - EXTI_
IMR_ IM11_ Msk - EXTI_
IMR_ IM11_ Pos - EXTI_
IMR_ IM12_ Msk - EXTI_
IMR_ IM12_ Pos - EXTI_
IMR_ IM13_ Msk - EXTI_
IMR_ IM13_ Pos - EXTI_
IMR_ IM14_ Msk - EXTI_
IMR_ IM14_ Pos - EXTI_
IMR_ IM15_ Msk - EXTI_
IMR_ IM15_ Pos - EXTI_
IMR_ IM16_ Msk - EXTI_
IMR_ IM16_ Pos - EXTI_
IMR_ IM17_ Msk - EXTI_
IMR_ IM17_ Pos - EXTI_
IMR_ IM18_ Msk - EXTI_
IMR_ IM18_ Pos - EXTI_
IMR_ IM19_ Msk - EXTI_
IMR_ IM19_ Pos - EXTI_
IMR_ IM29_ Msk - EXTI_
IMR_ IM29_ Pos - EXTI_
IMR_ IM_ Msk - EXTI_
IMR_ IM_ Pos - EXTI_
LINE_ 0 - EXTI_
LINE_ 1 - EXTI_
LINE_ 2 - EXTI_
LINE_ 3 - EXTI_
LINE_ 4 - EXTI_
LINE_ 5 - EXTI_
LINE_ 6 - EXTI_
LINE_ 7 - EXTI_
LINE_ 8 - EXTI_
LINE_ 9 - EXTI_
LINE_ 10 - EXTI_
LINE_ 11 - EXTI_
LINE_ 12 - EXTI_
LINE_ 13 - EXTI_
LINE_ 14 - EXTI_
LINE_ 15 - EXTI_
LINE_ 16 - EXTI_
LINE_ 17 - EXTI_
LINE_ 18 - EXTI_
LINE_ 19 - EXTI_
LINE_ 20 - EXTI_
LINE_ 21 - EXTI_
LINE_ 22 - EXTI_
LINE_ 23 - EXTI_
LINE_ 24 - EXTI_
LINE_ 25 - EXTI_
LINE_ 26 - EXTI_
LINE_ 27 - EXTI_
LINE_ 28 - EXTI_
LINE_ 29 - EXTI_
LINE_ 30 - EXTI_
LINE_ 31 - EXTI_
LINE_ NB - EXTI_
MODE_ EVENT - EXTI_
MODE_ INTERRUPT - EXTI_
MODE_ MASK - EXTI_
MODE_ NONE - EXTI_
PIN_ MASK - EXTI_
PROPERTY_ MASK - EXTI_
PROPERTY_ SHIFT - EXTI_
PR_ PIF0 - EXTI_
PR_ PIF1 - EXTI_
PR_ PIF2 - EXTI_
PR_ PIF3 - EXTI_
PR_ PIF4 - EXTI_
PR_ PIF5 - EXTI_
PR_ PIF6 - EXTI_
PR_ PIF7 - EXTI_
PR_ PIF8 - EXTI_
PR_ PIF9 - EXTI_
PR_ PIF10 - EXTI_
PR_ PIF11 - EXTI_
PR_ PIF12 - EXTI_
PR_ PIF13 - EXTI_
PR_ PIF14 - EXTI_
PR_ PIF15 - EXTI_
PR_ PIF16 - EXTI_
PR_ PIF17 - EXTI_
PR_ PIF18 - EXTI_
PR_ PR0 - EXTI_
PR_ PR0_ Msk - EXTI_
PR_ PR0_ Pos - EXTI_
PR_ PR1 - EXTI_
PR_ PR2 - EXTI_
PR_ PR3 - EXTI_
PR_ PR4 - EXTI_
PR_ PR5 - EXTI_
PR_ PR6 - EXTI_
PR_ PR7 - EXTI_
PR_ PR8 - EXTI_
PR_ PR9 - EXTI_
PR_ PR1_ Msk - EXTI_
PR_ PR1_ Pos - EXTI_
PR_ PR2_ Msk - EXTI_
PR_ PR2_ Pos - EXTI_
PR_ PR3_ Msk - EXTI_
PR_ PR3_ Pos - EXTI_
PR_ PR5_ Msk - EXTI_
PR_ PR5_ Pos - EXTI_
PR_ PR6_ Msk - EXTI_
PR_ PR6_ Pos - EXTI_
PR_ PR7_ Msk - EXTI_
PR_ PR7_ Pos - EXTI_
PR_ PR8_ Msk - EXTI_
PR_ PR8_ Pos - EXTI_
PR_ PR9_ Msk - EXTI_
PR_ PR9_ Pos - EXTI_
PR_ PR10 - EXTI_
PR_ PR11 - EXTI_
PR_ PR12 - EXTI_
PR_ PR13 - EXTI_
PR_ PR14 - EXTI_
PR_ PR15 - EXTI_
PR_ PR16 - EXTI_
PR_ PR17 - EXTI_
PR_ PR18 - EXTI_
PR_ PR10_ Msk - EXTI_
PR_ PR10_ Pos - EXTI_
PR_ PR11_ Msk - EXTI_
PR_ PR11_ Pos - EXTI_
PR_ PR12_ Msk - EXTI_
PR_ PR12_ Pos - EXTI_
PR_ PR13_ Msk - EXTI_
PR_ PR13_ Pos - EXTI_
PR_ PR14_ Msk - EXTI_
PR_ PR14_ Pos - EXTI_
PR_ PR15_ Msk - EXTI_
PR_ PR15_ Pos - EXTI_
PR_ PR16_ Msk - EXTI_
PR_ PR16_ Pos - EXTI_
PR_ PR17_ Msk - EXTI_
PR_ PR17_ Pos - EXTI_
PR_ PR18_ Msk - EXTI_
PR_ PR18_ Pos - EXTI_
PR_ PR_ Msk - EXTI_
PR_ PR_ Pos - EXTI_
REG1 - EXTI_
REG2 - EXTI_
REG_ MASK - EXTI_
REG_ SHIFT - EXTI_
RESERVED - EXTI_
RTSR_ RT0 - EXTI_
RTSR_ RT0_ Msk - EXTI_
RTSR_ RT0_ Pos - EXTI_
RTSR_ RT1 - EXTI_
RTSR_ RT2 - EXTI_
RTSR_ RT3 - EXTI_
RTSR_ RT4 - EXTI_
RTSR_ RT5 - EXTI_
RTSR_ RT6 - EXTI_
RTSR_ RT7 - EXTI_
RTSR_ RT8 - EXTI_
RTSR_ RT9 - EXTI_
RTSR_ RT1_ Msk - EXTI_
RTSR_ RT1_ Pos - EXTI_
RTSR_ RT2_ Msk - EXTI_
RTSR_ RT2_ Pos - EXTI_
RTSR_ RT3_ Msk - EXTI_
RTSR_ RT3_ Pos - EXTI_
RTSR_ RT4_ Msk - EXTI_
RTSR_ RT4_ Pos - EXTI_
RTSR_ RT5_ Msk - EXTI_
RTSR_ RT5_ Pos - EXTI_
RTSR_ RT6_ Msk - EXTI_
RTSR_ RT6_ Pos - EXTI_
RTSR_ RT7_ Msk - EXTI_
RTSR_ RT7_ Pos - EXTI_
RTSR_ RT8_ Msk - EXTI_
RTSR_ RT8_ Pos - EXTI_
RTSR_ RT9_ Msk - EXTI_
RTSR_ RT9_ Pos - EXTI_
RTSR_ RT10 - EXTI_
RTSR_ RT11 - EXTI_
RTSR_ RT12 - EXTI_
RTSR_ RT13 - EXTI_
RTSR_ RT14 - EXTI_
RTSR_ RT15 - EXTI_
RTSR_ RT16 - EXTI_
RTSR_ RT17 - EXTI_
RTSR_ RT18 - EXTI_
RTSR_ RT10_ Msk - EXTI_
RTSR_ RT10_ Pos - EXTI_
RTSR_ RT11_ Msk - EXTI_
RTSR_ RT11_ Pos - EXTI_
RTSR_ RT12_ Msk - EXTI_
RTSR_ RT12_ Pos - EXTI_
RTSR_ RT13_ Msk - EXTI_
RTSR_ RT13_ Pos - EXTI_
RTSR_ RT14_ Msk - EXTI_
RTSR_ RT14_ Pos - EXTI_
RTSR_ RT15_ Msk - EXTI_
RTSR_ RT15_ Pos - EXTI_
RTSR_ RT16_ Msk - EXTI_
RTSR_ RT16_ Pos - EXTI_
RTSR_ RT17_ Msk - EXTI_
RTSR_ RT17_ Pos - EXTI_
RTSR_ RT18_ Msk - EXTI_
RTSR_ RT18_ Pos - EXTI_
SWIER_ SWI0 - EXTI_
SWIER_ SWI0_ Msk - EXTI_
SWIER_ SWI0_ Pos - EXTI_
SWIER_ SWI1 - EXTI_
SWIER_ SWI2 - EXTI_
SWIER_ SWI3 - EXTI_
SWIER_ SWI4 - EXTI_
SWIER_ SWI5 - EXTI_
SWIER_ SWI6 - EXTI_
SWIER_ SWI7 - EXTI_
SWIER_ SWI8 - EXTI_
SWIER_ SWI9 - EXTI_
SWIER_ SWI1_ Msk - EXTI_
SWIER_ SWI1_ Pos - EXTI_
SWIER_ SWI2_ Msk - EXTI_
SWIER_ SWI2_ Pos - EXTI_
SWIER_ SWI3_ Msk - EXTI_
SWIER_ SWI3_ Pos - EXTI_
SWIER_ SWI4_ Msk - EXTI_
SWIER_ SWI4_ Pos - EXTI_
SWIER_ SWI5_ Msk - EXTI_
SWIER_ SWI5_ Pos - EXTI_
SWIER_ SWI6_ Msk - EXTI_
SWIER_ SWI6_ Pos - EXTI_
SWIER_ SWI7_ Msk - EXTI_
SWIER_ SWI7_ Pos - EXTI_
SWIER_ SWI8_ Msk - EXTI_
SWIER_ SWI8_ Pos - EXTI_
SWIER_ SWI9_ Msk - EXTI_
SWIER_ SWI9_ Pos - EXTI_
SWIER_ SWI10 - EXTI_
SWIER_ SWI11 - EXTI_
SWIER_ SWI12 - EXTI_
SWIER_ SWI13 - EXTI_
SWIER_ SWI14 - EXTI_
SWIER_ SWI15 - EXTI_
SWIER_ SWI16 - EXTI_
SWIER_ SWI17 - EXTI_
SWIER_ SWI18 - EXTI_
SWIER_ SWI10_ Msk - EXTI_
SWIER_ SWI10_ Pos - EXTI_
SWIER_ SWI11_ Msk - EXTI_
SWIER_ SWI11_ Pos - EXTI_
SWIER_ SWI12_ Msk - EXTI_
SWIER_ SWI12_ Pos - EXTI_
SWIER_ SWI13_ Msk - EXTI_
SWIER_ SWI13_ Pos - EXTI_
SWIER_ SWI14_ Msk - EXTI_
SWIER_ SWI14_ Pos - EXTI_
SWIER_ SWI15_ Msk - EXTI_
SWIER_ SWI15_ Pos - EXTI_
SWIER_ SWI16_ Msk - EXTI_
SWIER_ SWI16_ Pos - EXTI_
SWIER_ SWI17_ Msk - EXTI_
SWIER_ SWI17_ Pos - EXTI_
SWIER_ SWI18_ Msk - EXTI_
SWIER_ SWI18_ Pos - EXTI_
TRIGGER_ FALLING - EXTI_
TRIGGER_ MASK - EXTI_
TRIGGER_ NONE - EXTI_
TRIGGER_ RISING - EXTI_
TRIGGER_ RISING_ FALLING - Error
Status_ ERROR - Error
Status_ SUCCESS - FLASH
- FLASHSIZE_
BASE - FLASH_
ACR_ LATENCY - FLASH_
ACR_ LATENCY_ Msk - FLASH_
ACR_ LATENCY_ Pos - FLASH_
BASE - FLASH_
CR_ EOPIE - FLASH_
CR_ EOPIE_ Msk - FLASH_
CR_ EOPIE_ Pos - FLASH_
CR_ ERRIE - FLASH_
CR_ ERRIE_ Msk - FLASH_
CR_ ERRIE_ Pos - FLASH_
CR_ LOCK - FLASH_
CR_ LOCK_ Msk - FLASH_
CR_ LOCK_ Pos - FLASH_
CR_ MER - FLASH_
CR_ MER_ Msk - FLASH_
CR_ MER_ Pos - FLASH_
CR_ OBL_ LAUNCH - FLASH_
CR_ OBL_ LAUNCH_ Msk - FLASH_
CR_ OBL_ LAUNCH_ Pos - FLASH_
CR_ OPTLOCK - FLASH_
CR_ OPTLOCK_ Msk - FLASH_
CR_ OPTLOCK_ Pos - FLASH_
CR_ OPTSTRT - FLASH_
CR_ OPTSTRT_ Msk - FLASH_
CR_ OPTSTRT_ Pos - FLASH_
CR_ PER - FLASH_
CR_ PER_ Msk - FLASH_
CR_ PER_ Pos - FLASH_
CR_ PG - FLASH_
CR_ PGSTRT - FLASH_
CR_ PGSTRT_ Msk - FLASH_
CR_ PGSTRT_ Pos - FLASH_
CR_ PG_ Msk - FLASH_
CR_ PG_ Pos - FLASH_
CR_ SER - FLASH_
CR_ SER_ Msk - FLASH_
CR_ SER_ Pos - FLASH_
END - FLASH_
FLAG_ ALL_ ERRORS - FLASH_
FLAG_ BSY - FLASH_
FLAG_ EOP - FLASH_
FLAG_ OPTVERR - FLASH_
FLAG_ SR_ CLEAR - FLASH_
FLAG_ SR_ ERROR - FLASH_
FLAG_ WRPERR - FLASH_
IT_ EOP - FLASH_
IT_ OPERR - FLASH_
KEY1 - FLASH_
KEY2 - FLASH_
KEY1_ Msk - FLASH_
KEY1_ Pos - FLASH_
KEY2_ Msk - FLASH_
KEY2_ Pos - FLASH_
KEYR_ KEY - FLASH_
KEYR_ KEY_ Msk - FLASH_
KEYR_ KEY_ Pos - FLASH_
LATENCY_ 0 - FLASH_
LATENCY_ 1 - FLASH_
OPTKE Y1 - FLASH_
OPTKE Y2 - FLASH_
OPTKE Y1_ Msk - FLASH_
OPTKE Y1_ Pos - FLASH_
OPTKE Y2_ Msk - FLASH_
OPTKE Y2_ Pos - FLASH_
OPTKEYR_ OPTKEY - FLASH_
OPTKEYR_ OPTKEY_ Msk - FLASH_
OPTKEYR_ OPTKEY_ Pos - FLASH_
OPTR_ BOR_ EN - FLASH_
OPTR_ BOR_ EN_ Msk - FLASH_
OPTR_ BOR_ EN_ Pos - FLASH_
OPTR_ BOR_ LEV - FLASH_
OPTR_ BOR_ LEV_ 0 - FLASH_
OPTR_ BOR_ LEV_ 1 - FLASH_
OPTR_ BOR_ LEV_ 2 - FLASH_
OPTR_ BOR_ LEV_ Msk - FLASH_
OPTR_ BOR_ LEV_ Pos - FLASH_
OPTR_ IWDG_ SW - FLASH_
OPTR_ IWDG_ SW_ Msk - FLASH_
OPTR_ IWDG_ SW_ Pos - FLASH_
OPTR_ NRST_ MODE - FLASH_
OPTR_ NRST_ MODE_ Msk - FLASH_
OPTR_ NRST_ MODE_ Pos - FLASH_
OPTR_ RDP - FLASH_
OPTR_ RDP_ LEVEL_ 0 - FLASH_
OPTR_ RDP_ LEVEL_ 1 - FLASH_
OPTR_ RDP_ Msk - FLASH_
OPTR_ RDP_ Pos - FLASH_
OPTR_ WWDG_ SW - FLASH_
OPTR_ WWDG_ SW_ Msk - FLASH_
OPTR_ WWDG_ SW_ Pos - FLASH_
OPTR_ nBOO T1 - FLASH_
OPTR_ nBOO T1_ Msk - FLASH_
OPTR_ nBOO T1_ Pos - FLASH_
PAGE_ NB - FLASH_
PAGE_ SIZE - FLASH_
PERTPE_ PERTPE - FLASH_
PERTPE_ PERTPE_ 0 - FLASH_
PERTPE_ PERTPE_ 1 - FLASH_
PERTPE_ PERTPE_ 2 - FLASH_
PERTPE_ PERTPE_ 3 - FLASH_
PERTPE_ PERTPE_ 4 - FLASH_
PERTPE_ PERTPE_ 5 - FLASH_
PERTPE_ PERTPE_ 6 - FLASH_
PERTPE_ PERTPE_ 7 - FLASH_
PERTPE_ PERTPE_ 8 - FLASH_
PERTPE_ PERTPE_ 9 - FLASH_
PERTPE_ PERTPE_ 10 - FLASH_
PERTPE_ PERTPE_ 11 - FLASH_
PERTPE_ PERTPE_ 12 - FLASH_
PERTPE_ PERTPE_ 13 - FLASH_
PERTPE_ PERTPE_ 14 - FLASH_
PERTPE_ PERTPE_ 15 - FLASH_
PERTPE_ PERTPE_ 16 - FLASH_
PERTPE_ PERTPE_ Msk - FLASH_
PERTPE_ PERTPE_ Pos - FLASH_
PRETPE_ PRETPE - FLASH_
PRETPE_ PRETPE_ 0 - FLASH_
PRETPE_ PRETPE_ 1 - FLASH_
PRETPE_ PRETPE_ 2 - FLASH_
PRETPE_ PRETPE_ 3 - FLASH_
PRETPE_ PRETPE_ 4 - FLASH_
PRETPE_ PRETPE_ 5 - FLASH_
PRETPE_ PRETPE_ 6 - FLASH_
PRETPE_ PRETPE_ 7 - FLASH_
PRETPE_ PRETPE_ 8 - FLASH_
PRETPE_ PRETPE_ 9 - FLASH_
PRETPE_ PRETPE_ 10 - FLASH_
PRETPE_ PRETPE_ 11 - FLASH_
PRETPE_ PRETPE_ 12 - FLASH_
PRETPE_ PRETPE_ 13 - FLASH_
PRETPE_ PRETPE_ Msk - FLASH_
PRETPE_ PRETPE_ Pos - FLASH_
PRGTPE_ PRGTPE - FLASH_
PRGTPE_ PRGTPE_ 0 - FLASH_
PRGTPE_ PRGTPE_ 1 - FLASH_
PRGTPE_ PRGTPE_ 2 - FLASH_
PRGTPE_ PRGTPE_ 3 - FLASH_
PRGTPE_ PRGTPE_ 4 - FLASH_
PRGTPE_ PRGTPE_ 5 - FLASH_
PRGTPE_ PRGTPE_ 6 - FLASH_
PRGTPE_ PRGTPE_ 7 - FLASH_
PRGTPE_ PRGTPE_ 8 - FLASH_
PRGTPE_ PRGTPE_ 9 - FLASH_
PRGTPE_ PRGTPE_ 10 - FLASH_
PRGTPE_ PRGTPE_ 11 - FLASH_
PRGTPE_ PRGTPE_ 12 - FLASH_
PRGTPE_ PRGTPE_ 13 - FLASH_
PRGTPE_ PRGTPE_ 14 - FLASH_
PRGTPE_ PRGTPE_ 15 - FLASH_
PRGTPE_ PRGTPE_ Msk - FLASH_
PRGTPE_ PRGTPE_ Pos - FLASH_
PROGRAM_ ERASE_ CLOCK_ 4MHZ - FLASH_
PROGRAM_ ERASE_ CLOCK_ 8MHZ - FLASH_
PROGRAM_ ERASE_ CLOCK_ 16MHZ - FLASH_
PROGRAM_ ERASE_ CLOCK_ 22p12MHZ - FLASH_
PROGRAM_ ERASE_ CLOCK_ 24MHZ - FLASH_
R_ BASE - FLASH_
SDKR_ SDK_ END - FLASH_
SDKR_ SDK_ END_ 0 - FLASH_
SDKR_ SDK_ END_ 1 - FLASH_
SDKR_ SDK_ END_ 2 - FLASH_
SDKR_ SDK_ END_ 3 - FLASH_
SDKR_ SDK_ END_ 4 - FLASH_
SDKR_ SDK_ END_ Msk - FLASH_
SDKR_ SDK_ END_ Pos - FLASH_
SDKR_ SDK_ STRT - FLASH_
SDKR_ SDK_ STRT_ 0 - FLASH_
SDKR_ SDK_ STRT_ 1 - FLASH_
SDKR_ SDK_ STRT_ 2 - FLASH_
SDKR_ SDK_ STRT_ 3 - FLASH_
SDKR_ SDK_ STRT_ 4 - FLASH_
SDKR_ SDK_ STRT_ Msk - FLASH_
SDKR_ SDK_ STRT_ Pos - FLASH_
SECTOR_ NB - FLASH_
SECTOR_ SIZE - FLASH_
SIZE - FLASH_
SMERTPE_ SMERTPE - FLASH_
SMERTPE_ SMERTPE_ 0 - FLASH_
SMERTPE_ SMERTPE_ 1 - FLASH_
SMERTPE_ SMERTPE_ 2 - FLASH_
SMERTPE_ SMERTPE_ 3 - FLASH_
SMERTPE_ SMERTPE_ 4 - FLASH_
SMERTPE_ SMERTPE_ 5 - FLASH_
SMERTPE_ SMERTPE_ 6 - FLASH_
SMERTPE_ SMERTPE_ 7 - FLASH_
SMERTPE_ SMERTPE_ 8 - FLASH_
SMERTPE_ SMERTPE_ 9 - FLASH_
SMERTPE_ SMERTPE_ 10 - FLASH_
SMERTPE_ SMERTPE_ 11 - FLASH_
SMERTPE_ SMERTPE_ 12 - FLASH_
SMERTPE_ SMERTPE_ 13 - FLASH_
SMERTPE_ SMERTPE_ 14 - FLASH_
SMERTPE_ SMERTPE_ 15 - FLASH_
SMERTPE_ SMERTPE_ 16 - FLASH_
SMERTPE_ SMERTPE_ Msk - FLASH_
SMERTPE_ SMERTPE_ Pos - FLASH_
SR_ BSY - FLASH_
SR_ BSY_ Msk - FLASH_
SR_ BSY_ Pos - FLASH_
SR_ EOP - FLASH_
SR_ EOP_ Msk - FLASH_
SR_ EOP_ Pos - FLASH_
SR_ OPTVERR - FLASH_
SR_ OPTVERR_ Msk - FLASH_
SR_ OPTVERR_ Pos - FLASH_
SR_ WRPERR - FLASH_
SR_ WRPERR_ Msk - FLASH_
SR_ WRPERR_ Pos - FLASH_
STCR_ SLEEP_ EN - FLASH_
STCR_ SLEEP_ EN_ Msk - FLASH_
STCR_ SLEEP_ EN_ Pos - FLASH_
STCR_ SLEEP_ TIME - FLASH_
STCR_ SLEEP_ TIME_ Msk - FLASH_
STCR_ SLEEP_ TIME_ Pos - FLASH_
TIMEOUT_ VALUE - FLASH_
TPS3_ TPS3 - FLASH_
TPS3_ TPS3_ 0 - FLASH_
TPS3_ TPS3_ 1 - FLASH_
TPS3_ TPS3_ 2 - FLASH_
TPS3_ TPS3_ 3 - FLASH_
TPS3_ TPS3_ 4 - FLASH_
TPS3_ TPS3_ 5 - FLASH_
TPS3_ TPS3_ 6 - FLASH_
TPS3_ TPS3_ 7 - FLASH_
TPS3_ TPS3_ 8 - FLASH_
TPS3_ TPS3_ 9 - FLASH_
TPS3_ TPS3_ 10 - FLASH_
TPS3_ TPS3_ Msk - FLASH_
TPS3_ TPS3_ Pos - FLASH_
TS0_ TS0 - FLASH_
TS0_ TS0_ 0 - FLASH_
TS0_ TS0_ 1 - FLASH_
TS0_ TS0_ 2 - FLASH_
TS0_ TS0_ 3 - FLASH_
TS0_ TS0_ 4 - FLASH_
TS0_ TS0_ 5 - FLASH_
TS0_ TS0_ 6 - FLASH_
TS0_ TS0_ 7 - FLASH_
TS0_ TS0_ Msk - FLASH_
TS0_ TS0_ Pos - FLASH_
TS1_ TS1 - FLASH_
TS1_ TS1_ 0 - FLASH_
TS1_ TS1_ 1 - FLASH_
TS1_ TS1_ 2 - FLASH_
TS1_ TS1_ 3 - FLASH_
TS1_ TS1_ 4 - FLASH_
TS1_ TS1_ 5 - FLASH_
TS1_ TS1_ 6 - FLASH_
TS1_ TS1_ 7 - FLASH_
TS1_ TS1_ Msk - FLASH_
TS1_ TS1_ Pos - FLASH_
TS2P_ TS2P - FLASH_
TS2P_ TS2P_ 0 - FLASH_
TS2P_ TS2P_ 1 - FLASH_
TS2P_ TS2P_ 2 - FLASH_
TS2P_ TS2P_ 3 - FLASH_
TS2P_ TS2P_ 4 - FLASH_
TS2P_ TS2P_ 5 - FLASH_
TS2P_ TS2P_ 6 - FLASH_
TS2P_ TS2P_ 7 - FLASH_
TS2P_ TS2P_ Msk - FLASH_
TS2P_ TS2P_ Pos - FLASH_
TS3_ TS3 - FLASH_
TS3_ TS3_ 0 - FLASH_
TS3_ TS3_ 1 - FLASH_
TS3_ TS3_ 2 - FLASH_
TS3_ TS3_ 3 - FLASH_
TS3_ TS3_ 4 - FLASH_
TS3_ TS3_ 5 - FLASH_
TS3_ TS3_ 6 - FLASH_
TS3_ TS3_ 7 - FLASH_
TS3_ TS3_ Msk - FLASH_
TS3_ TS3_ Pos - FLASH_
TYPEERASE_ MASSERASE - FLASH_
TYPEERASE_ PAGEERASE - FLASH_
TYPEERASE_ SECTORERASE - FLASH_
TYPENONE - FLASH_
TYPEPROGRAM_ PAGE - FLASH_
WRPR_ WRP - FLASH_
WRPR_ WRP_ 0 - FLASH_
WRPR_ WRP_ 1 - FLASH_
WRPR_ WRP_ 2 - FLASH_
WRPR_ WRP_ 3 - FLASH_
WRPR_ WRP_ 4 - FLASH_
WRPR_ WRP_ 5 - FLASH_
WRPR_ WRP_ 6 - FLASH_
WRPR_ WRP_ 7 - FLASH_
WRPR_ WRP_ 8 - FLASH_
WRPR_ WRP_ 9 - FLASH_
WRPR_ WRP_ 10 - FLASH_
WRPR_ WRP_ 11 - FLASH_
WRPR_ WRP_ 12 - FLASH_
WRPR_ WRP_ 13 - FLASH_
WRPR_ WRP_ 14 - FLASH_
WRPR_ WRP_ 15 - FLASH_
WRPR_ WRP_ Msk - FLASH_
WRPR_ WRP_ Pos - Flag
Status_ RESET - Flag
Status_ SET - Functional
State_ DISABLE - Functional
State_ ENABLE - GPIOA
- GPIOA_
BASE - GPIOB
- GPIOB_
BASE - GPIOF
- GPIOF_
BASE - GPIO_
AF0_ SPI1 - GPIO_
AF0_ SPI2 - GPIO_
AF0_ SWJ - GPIO_
AF0_ TIM14 - GPIO_
AF0_ USAR T1 - GPIO_
AF1_ IR - GPIO_
AF1_ SPI2 - GPIO_
AF1_ TIM1 - GPIO_
AF1_ TIM3 - GPIO_
AF1_ USAR T1 - GPIO_
AF2_ SPI2 - GPIO_
AF2_ TIM1 - GPIO_
AF2_ TIM14 - GPIO_
AF2_ TIM16 - GPIO_
AF2_ TIM17 - GPIO_
AF3_ LED - GPIO_
AF3_ SPI2 - GPIO_
AF3_ USAR T1 - GPIO_
AF3_ USAR T2 - GPIO_
AF4_ TIM14 - GPIO_
AF4_ USAR T2 - GPIO_
AF5_ EVENTOUT - GPIO_
AF5_ LPTIM - GPIO_
AF5_ MCO - GPIO_
AF5_ TIM16 - GPIO_
AF5_ TIM17 - GPIO_
AF5_ USAR T2 - GPIO_
AF6_ EVENTOUT - GPIO_
AF6_ I2C - GPIO_
AF6_ LED - GPIO_
AF6_ MCO - GPIO_
AF7_ COMP1 - GPIO_
AF7_ COMP2 - GPIO_
AF7_ EVENTOUT - GPIO_
AF8_ USAR T1 - GPIO_
AF9_ USAR T2 - GPIO_
AF10_ SPI1 - GPIO_
AF11_ SPI2 - GPIO_
AF12_ I2C - GPIO_
AF13_ TIM1 - GPIO_
AF13_ TIM3 - GPIO_
AF13_ TIM14 - GPIO_
AF13_ TIM17 - GPIO_
AF14_ TIM1 - GPIO_
AF15_ IR - GPIO_
AF15_ MCO - GPIO_
AF15_ RTCOUT - GPIO_
AFRH_ AFSE L8 - GPIO_
AFRH_ AFSE L9 - GPIO_
AFRH_ AFSE L8_ 0 - GPIO_
AFRH_ AFSE L8_ 1 - GPIO_
AFRH_ AFSE L8_ 2 - GPIO_
AFRH_ AFSE L8_ 3 - GPIO_
AFRH_ AFSE L8_ Msk - GPIO_
AFRH_ AFSE L8_ Pos - GPIO_
AFRH_ AFSE L9_ 0 - GPIO_
AFRH_ AFSE L9_ 1 - GPIO_
AFRH_ AFSE L9_ 2 - GPIO_
AFRH_ AFSE L9_ 3 - GPIO_
AFRH_ AFSE L9_ Msk - GPIO_
AFRH_ AFSE L9_ Pos - GPIO_
AFRH_ AFSE L10 - GPIO_
AFRH_ AFSE L11 - GPIO_
AFRH_ AFSE L12 - GPIO_
AFRH_ AFSE L13 - GPIO_
AFRH_ AFSE L14 - GPIO_
AFRH_ AFSE L15 - GPIO_
AFRH_ AFSE L10_ 0 - GPIO_
AFRH_ AFSE L10_ 1 - GPIO_
AFRH_ AFSE L10_ 2 - GPIO_
AFRH_ AFSE L10_ 3 - GPIO_
AFRH_ AFSE L10_ Msk - GPIO_
AFRH_ AFSE L10_ Pos - GPIO_
AFRH_ AFSE L11_ 0 - GPIO_
AFRH_ AFSE L11_ 1 - GPIO_
AFRH_ AFSE L11_ 2 - GPIO_
AFRH_ AFSE L11_ 3 - GPIO_
AFRH_ AFSE L11_ Msk - GPIO_
AFRH_ AFSE L11_ Pos - GPIO_
AFRH_ AFSE L12_ 0 - GPIO_
AFRH_ AFSE L12_ 1 - GPIO_
AFRH_ AFSE L12_ 2 - GPIO_
AFRH_ AFSE L12_ 3 - GPIO_
AFRH_ AFSE L12_ Msk - GPIO_
AFRH_ AFSE L12_ Pos - GPIO_
AFRH_ AFSE L13_ 0 - GPIO_
AFRH_ AFSE L13_ 1 - GPIO_
AFRH_ AFSE L13_ 2 - GPIO_
AFRH_ AFSE L13_ 3 - GPIO_
AFRH_ AFSE L13_ Msk - GPIO_
AFRH_ AFSE L13_ Pos - GPIO_
AFRH_ AFSE L14_ 0 - GPIO_
AFRH_ AFSE L14_ 1 - GPIO_
AFRH_ AFSE L14_ 2 - GPIO_
AFRH_ AFSE L14_ 3 - GPIO_
AFRH_ AFSE L14_ Msk - GPIO_
AFRH_ AFSE L14_ Pos - GPIO_
AFRH_ AFSE L15_ 0 - GPIO_
AFRH_ AFSE L15_ 1 - GPIO_
AFRH_ AFSE L15_ 2 - GPIO_
AFRH_ AFSE L15_ 3 - GPIO_
AFRH_ AFSE L15_ Msk - GPIO_
AFRH_ AFSE L15_ Pos - GPIO_
AFRL_ AFSE L0 - GPIO_
AFRL_ AFSE L0_ 0 - GPIO_
AFRL_ AFSE L0_ 1 - GPIO_
AFRL_ AFSE L0_ 2 - GPIO_
AFRL_ AFSE L0_ 3 - GPIO_
AFRL_ AFSE L0_ Msk - GPIO_
AFRL_ AFSE L0_ Pos - GPIO_
AFRL_ AFSE L1 - GPIO_
AFRL_ AFSE L2 - GPIO_
AFRL_ AFSE L3 - GPIO_
AFRL_ AFSE L4 - GPIO_
AFRL_ AFSE L5 - GPIO_
AFRL_ AFSE L6 - GPIO_
AFRL_ AFSE L7 - GPIO_
AFRL_ AFSE L1_ 0 - GPIO_
AFRL_ AFSE L1_ 1 - GPIO_
AFRL_ AFSE L1_ 2 - GPIO_
AFRL_ AFSE L1_ 3 - GPIO_
AFRL_ AFSE L1_ Msk - GPIO_
AFRL_ AFSE L1_ Pos - GPIO_
AFRL_ AFSE L2_ 0 - GPIO_
AFRL_ AFSE L2_ 1 - GPIO_
AFRL_ AFSE L2_ 2 - GPIO_
AFRL_ AFSE L2_ 3 - GPIO_
AFRL_ AFSE L2_ Msk - GPIO_
AFRL_ AFSE L2_ Pos - GPIO_
AFRL_ AFSE L3_ 0 - GPIO_
AFRL_ AFSE L3_ 1 - GPIO_
AFRL_ AFSE L3_ 2 - GPIO_
AFRL_ AFSE L3_ 3 - GPIO_
AFRL_ AFSE L3_ Msk - GPIO_
AFRL_ AFSE L3_ Pos - GPIO_
AFRL_ AFSE L4_ 0 - GPIO_
AFRL_ AFSE L4_ 1 - GPIO_
AFRL_ AFSE L4_ 2 - GPIO_
AFRL_ AFSE L4_ 3 - GPIO_
AFRL_ AFSE L4_ Msk - GPIO_
AFRL_ AFSE L4_ Pos - GPIO_
AFRL_ AFSE L5_ 0 - GPIO_
AFRL_ AFSE L5_ 1 - GPIO_
AFRL_ AFSE L5_ 2 - GPIO_
AFRL_ AFSE L5_ 3 - GPIO_
AFRL_ AFSE L5_ Msk - GPIO_
AFRL_ AFSE L5_ Pos - GPIO_
AFRL_ AFSE L6_ 0 - GPIO_
AFRL_ AFSE L6_ 1 - GPIO_
AFRL_ AFSE L6_ 2 - GPIO_
AFRL_ AFSE L6_ 3 - GPIO_
AFRL_ AFSE L6_ Msk - GPIO_
AFRL_ AFSE L6_ Pos - GPIO_
AFRL_ AFSE L7_ 0 - GPIO_
AFRL_ AFSE L7_ 1 - GPIO_
AFRL_ AFSE L7_ 2 - GPIO_
AFRL_ AFSE L7_ 3 - GPIO_
AFRL_ AFSE L7_ Msk - GPIO_
AFRL_ AFSE L7_ Pos - GPIO_
BRR_ BR0 - GPIO_
BRR_ BR0_ Msk - GPIO_
BRR_ BR0_ Pos - GPIO_
BRR_ BR1 - GPIO_
BRR_ BR2 - GPIO_
BRR_ BR3 - GPIO_
BRR_ BR4 - GPIO_
BRR_ BR5 - GPIO_
BRR_ BR6 - GPIO_
BRR_ BR7 - GPIO_
BRR_ BR8 - GPIO_
BRR_ BR9 - GPIO_
BRR_ BR1_ Msk - GPIO_
BRR_ BR1_ Pos - GPIO_
BRR_ BR2_ Msk - GPIO_
BRR_ BR2_ Pos - GPIO_
BRR_ BR3_ Msk - GPIO_
BRR_ BR3_ Pos - GPIO_
BRR_ BR4_ Msk - GPIO_
BRR_ BR4_ Pos - GPIO_
BRR_ BR5_ Msk - GPIO_
BRR_ BR5_ Pos - GPIO_
BRR_ BR6_ Msk - GPIO_
BRR_ BR6_ Pos - GPIO_
BRR_ BR7_ Msk - GPIO_
BRR_ BR7_ Pos - GPIO_
BRR_ BR8_ Msk - GPIO_
BRR_ BR8_ Pos - GPIO_
BRR_ BR9_ Msk - GPIO_
BRR_ BR9_ Pos - GPIO_
BRR_ BR10 - GPIO_
BRR_ BR11 - GPIO_
BRR_ BR12 - GPIO_
BRR_ BR13 - GPIO_
BRR_ BR14 - GPIO_
BRR_ BR15 - GPIO_
BRR_ BR10_ Msk - GPIO_
BRR_ BR10_ Pos - GPIO_
BRR_ BR11_ Msk - GPIO_
BRR_ BR11_ Pos - GPIO_
BRR_ BR12_ Msk - GPIO_
BRR_ BR12_ Pos - GPIO_
BRR_ BR13_ Msk - GPIO_
BRR_ BR13_ Pos - GPIO_
BRR_ BR14_ Msk - GPIO_
BRR_ BR14_ Pos - GPIO_
BRR_ BR15_ Msk - GPIO_
BRR_ BR15_ Pos - GPIO_
BSRR_ BR0 - GPIO_
BSRR_ BR0_ Msk - GPIO_
BSRR_ BR0_ Pos - GPIO_
BSRR_ BR1 - GPIO_
BSRR_ BR2 - GPIO_
BSRR_ BR3 - GPIO_
BSRR_ BR4 - GPIO_
BSRR_ BR5 - GPIO_
BSRR_ BR6 - GPIO_
BSRR_ BR7 - GPIO_
BSRR_ BR8 - GPIO_
BSRR_ BR9 - GPIO_
BSRR_ BR1_ Msk - GPIO_
BSRR_ BR1_ Pos - GPIO_
BSRR_ BR2_ Msk - GPIO_
BSRR_ BR2_ Pos - GPIO_
BSRR_ BR3_ Msk - GPIO_
BSRR_ BR3_ Pos - GPIO_
BSRR_ BR4_ Msk - GPIO_
BSRR_ BR4_ Pos - GPIO_
BSRR_ BR5_ Msk - GPIO_
BSRR_ BR5_ Pos - GPIO_
BSRR_ BR6_ Msk - GPIO_
BSRR_ BR6_ Pos - GPIO_
BSRR_ BR7_ Msk - GPIO_
BSRR_ BR7_ Pos - GPIO_
BSRR_ BR8_ Msk - GPIO_
BSRR_ BR8_ Pos - GPIO_
BSRR_ BR9_ Msk - GPIO_
BSRR_ BR9_ Pos - GPIO_
BSRR_ BR10 - GPIO_
BSRR_ BR11 - GPIO_
BSRR_ BR12 - GPIO_
BSRR_ BR13 - GPIO_
BSRR_ BR14 - GPIO_
BSRR_ BR15 - GPIO_
BSRR_ BR10_ Msk - GPIO_
BSRR_ BR10_ Pos - GPIO_
BSRR_ BR11_ Msk - GPIO_
BSRR_ BR11_ Pos - GPIO_
BSRR_ BR12_ Msk - GPIO_
BSRR_ BR12_ Pos - GPIO_
BSRR_ BR13_ Msk - GPIO_
BSRR_ BR13_ Pos - GPIO_
BSRR_ BR14_ Msk - GPIO_
BSRR_ BR14_ Pos - GPIO_
BSRR_ BR15_ Msk - GPIO_
BSRR_ BR15_ Pos - GPIO_
BSRR_ BS0 - GPIO_
BSRR_ BS0_ Msk - GPIO_
BSRR_ BS0_ Pos - GPIO_
BSRR_ BS1 - GPIO_
BSRR_ BS2 - GPIO_
BSRR_ BS3 - GPIO_
BSRR_ BS4 - GPIO_
BSRR_ BS5 - GPIO_
BSRR_ BS6 - GPIO_
BSRR_ BS7 - GPIO_
BSRR_ BS8 - GPIO_
BSRR_ BS9 - GPIO_
BSRR_ BS1_ Msk - GPIO_
BSRR_ BS1_ Pos - GPIO_
BSRR_ BS2_ Msk - GPIO_
BSRR_ BS2_ Pos - GPIO_
BSRR_ BS3_ Msk - GPIO_
BSRR_ BS3_ Pos - GPIO_
BSRR_ BS4_ Msk - GPIO_
BSRR_ BS4_ Pos - GPIO_
BSRR_ BS5_ Msk - GPIO_
BSRR_ BS5_ Pos - GPIO_
BSRR_ BS6_ Msk - GPIO_
BSRR_ BS6_ Pos - GPIO_
BSRR_ BS7_ Msk - GPIO_
BSRR_ BS7_ Pos - GPIO_
BSRR_ BS8_ Msk - GPIO_
BSRR_ BS8_ Pos - GPIO_
BSRR_ BS9_ Msk - GPIO_
BSRR_ BS9_ Pos - GPIO_
BSRR_ BS10 - GPIO_
BSRR_ BS11 - GPIO_
BSRR_ BS12 - GPIO_
BSRR_ BS13 - GPIO_
BSRR_ BS14 - GPIO_
BSRR_ BS15 - GPIO_
BSRR_ BS10_ Msk - GPIO_
BSRR_ BS10_ Pos - GPIO_
BSRR_ BS11_ Msk - GPIO_
BSRR_ BS11_ Pos - GPIO_
BSRR_ BS12_ Msk - GPIO_
BSRR_ BS12_ Pos - GPIO_
BSRR_ BS13_ Msk - GPIO_
BSRR_ BS13_ Pos - GPIO_
BSRR_ BS14_ Msk - GPIO_
BSRR_ BS14_ Pos - GPIO_
BSRR_ BS15_ Msk - GPIO_
BSRR_ BS15_ Pos - GPIO_
IDR_ ID0 - GPIO_
IDR_ ID0_ Msk - GPIO_
IDR_ ID0_ Pos - GPIO_
IDR_ ID1 - GPIO_
IDR_ ID2 - GPIO_
IDR_ ID3 - GPIO_
IDR_ ID4 - GPIO_
IDR_ ID5 - GPIO_
IDR_ ID6 - GPIO_
IDR_ ID7 - GPIO_
IDR_ ID8 - GPIO_
IDR_ ID9 - GPIO_
IDR_ ID1_ Msk - GPIO_
IDR_ ID1_ Pos - GPIO_
IDR_ ID2_ Msk - GPIO_
IDR_ ID2_ Pos - GPIO_
IDR_ ID3_ Msk - GPIO_
IDR_ ID3_ Pos - GPIO_
IDR_ ID4_ Msk - GPIO_
IDR_ ID4_ Pos - GPIO_
IDR_ ID5_ Msk - GPIO_
IDR_ ID5_ Pos - GPIO_
IDR_ ID6_ Msk - GPIO_
IDR_ ID6_ Pos - GPIO_
IDR_ ID7_ Msk - GPIO_
IDR_ ID7_ Pos - GPIO_
IDR_ ID8_ Msk - GPIO_
IDR_ ID8_ Pos - GPIO_
IDR_ ID9_ Msk - GPIO_
IDR_ ID9_ Pos - GPIO_
IDR_ ID10 - GPIO_
IDR_ ID11 - GPIO_
IDR_ ID12 - GPIO_
IDR_ ID13 - GPIO_
IDR_ ID14 - GPIO_
IDR_ ID15 - GPIO_
IDR_ ID10_ Msk - GPIO_
IDR_ ID10_ Pos - GPIO_
IDR_ ID11_ Msk - GPIO_
IDR_ ID11_ Pos - GPIO_
IDR_ ID12_ Msk - GPIO_
IDR_ ID12_ Pos - GPIO_
IDR_ ID13_ Msk - GPIO_
IDR_ ID13_ Pos - GPIO_
IDR_ ID14_ Msk - GPIO_
IDR_ ID14_ Pos - GPIO_
IDR_ ID15_ Msk - GPIO_
IDR_ ID15_ Pos - GPIO_
LCKR_ LCK0 - GPIO_
LCKR_ LCK0_ Msk - GPIO_
LCKR_ LCK0_ Pos - GPIO_
LCKR_ LCK1 - GPIO_
LCKR_ LCK2 - GPIO_
LCKR_ LCK3 - GPIO_
LCKR_ LCK4 - GPIO_
LCKR_ LCK5 - GPIO_
LCKR_ LCK6 - GPIO_
LCKR_ LCK7 - GPIO_
LCKR_ LCK8 - GPIO_
LCKR_ LCK9 - GPIO_
LCKR_ LCK1_ Msk - GPIO_
LCKR_ LCK1_ Pos - GPIO_
LCKR_ LCK2_ Msk - GPIO_
LCKR_ LCK2_ Pos - GPIO_
LCKR_ LCK3_ Msk - GPIO_
LCKR_ LCK3_ Pos - GPIO_
LCKR_ LCK4_ Msk - GPIO_
LCKR_ LCK4_ Pos - GPIO_
LCKR_ LCK5_ Msk - GPIO_
LCKR_ LCK5_ Pos - GPIO_
LCKR_ LCK6_ Msk - GPIO_
LCKR_ LCK6_ Pos - GPIO_
LCKR_ LCK7_ Msk - GPIO_
LCKR_ LCK7_ Pos - GPIO_
LCKR_ LCK8_ Msk - GPIO_
LCKR_ LCK8_ Pos - GPIO_
LCKR_ LCK9_ Msk - GPIO_
LCKR_ LCK9_ Pos - GPIO_
LCKR_ LCK10 - GPIO_
LCKR_ LCK11 - GPIO_
LCKR_ LCK12 - GPIO_
LCKR_ LCK13 - GPIO_
LCKR_ LCK14 - GPIO_
LCKR_ LCK15 - GPIO_
LCKR_ LCK10_ Msk - GPIO_
LCKR_ LCK10_ Pos - GPIO_
LCKR_ LCK11_ Msk - GPIO_
LCKR_ LCK11_ Pos - GPIO_
LCKR_ LCK12_ Msk - GPIO_
LCKR_ LCK12_ Pos - GPIO_
LCKR_ LCK13_ Msk - GPIO_
LCKR_ LCK13_ Pos - GPIO_
LCKR_ LCK14_ Msk - GPIO_
LCKR_ LCK14_ Pos - GPIO_
LCKR_ LCK15_ Msk - GPIO_
LCKR_ LCK15_ Pos - GPIO_
LCKR_ LCKK - GPIO_
LCKR_ LCKK_ Msk - GPIO_
LCKR_ LCKK_ Pos - GPIO_
MODER_ MODE0 - GPIO_
MODER_ MODE0_ 0 - GPIO_
MODER_ MODE0_ 1 - GPIO_
MODER_ MODE0_ Msk - GPIO_
MODER_ MODE0_ Pos - GPIO_
MODER_ MODE1 - GPIO_
MODER_ MODE2 - GPIO_
MODER_ MODE3 - GPIO_
MODER_ MODE4 - GPIO_
MODER_ MODE5 - GPIO_
MODER_ MODE6 - GPIO_
MODER_ MODE7 - GPIO_
MODER_ MODE8 - GPIO_
MODER_ MODE9 - GPIO_
MODER_ MODE1_ 0 - GPIO_
MODER_ MODE1_ 1 - GPIO_
MODER_ MODE1_ Msk - GPIO_
MODER_ MODE1_ Pos - GPIO_
MODER_ MODE2_ 0 - GPIO_
MODER_ MODE2_ 1 - GPIO_
MODER_ MODE2_ Msk - GPIO_
MODER_ MODE2_ Pos - GPIO_
MODER_ MODE3_ 0 - GPIO_
MODER_ MODE3_ 1 - GPIO_
MODER_ MODE3_ Msk - GPIO_
MODER_ MODE3_ Pos - GPIO_
MODER_ MODE4_ 0 - GPIO_
MODER_ MODE4_ 1 - GPIO_
MODER_ MODE4_ Msk - GPIO_
MODER_ MODE4_ Pos - GPIO_
MODER_ MODE5_ 0 - GPIO_
MODER_ MODE5_ 1 - GPIO_
MODER_ MODE5_ Msk - GPIO_
MODER_ MODE5_ Pos - GPIO_
MODER_ MODE6_ 0 - GPIO_
MODER_ MODE6_ 1 - GPIO_
MODER_ MODE6_ Msk - GPIO_
MODER_ MODE6_ Pos - GPIO_
MODER_ MODE7_ 0 - GPIO_
MODER_ MODE7_ 1 - GPIO_
MODER_ MODE7_ Msk - GPIO_
MODER_ MODE7_ Pos - GPIO_
MODER_ MODE8_ 0 - GPIO_
MODER_ MODE8_ 1 - GPIO_
MODER_ MODE8_ Msk - GPIO_
MODER_ MODE8_ Pos - GPIO_
MODER_ MODE9_ 0 - GPIO_
MODER_ MODE9_ 1 - GPIO_
MODER_ MODE9_ Msk - GPIO_
MODER_ MODE9_ Pos - GPIO_
MODER_ MODE10 - GPIO_
MODER_ MODE11 - GPIO_
MODER_ MODE12 - GPIO_
MODER_ MODE13 - GPIO_
MODER_ MODE14 - GPIO_
MODER_ MODE15 - GPIO_
MODER_ MODE10_ 0 - GPIO_
MODER_ MODE10_ 1 - GPIO_
MODER_ MODE10_ Msk - GPIO_
MODER_ MODE10_ Pos - GPIO_
MODER_ MODE11_ 0 - GPIO_
MODER_ MODE11_ 1 - GPIO_
MODER_ MODE11_ Msk - GPIO_
MODER_ MODE11_ Pos - GPIO_
MODER_ MODE12_ 0 - GPIO_
MODER_ MODE12_ 1 - GPIO_
MODER_ MODE12_ Msk - GPIO_
MODER_ MODE12_ Pos - GPIO_
MODER_ MODE13_ 0 - GPIO_
MODER_ MODE13_ 1 - GPIO_
MODER_ MODE13_ Msk - GPIO_
MODER_ MODE13_ Pos - GPIO_
MODER_ MODE14_ 0 - GPIO_
MODER_ MODE14_ 1 - GPIO_
MODER_ MODE14_ Msk - GPIO_
MODER_ MODE14_ Pos - GPIO_
MODER_ MODE15_ 0 - GPIO_
MODER_ MODE15_ 1 - GPIO_
MODER_ MODE15_ Msk - GPIO_
MODER_ MODE15_ Pos - GPIO_
MODE_ AF_ OD - GPIO_
MODE_ AF_ PP - GPIO_
MODE_ ANALOG - GPIO_
MODE_ EVT_ FALLING - GPIO_
MODE_ EVT_ RISING - GPIO_
MODE_ EVT_ RISING_ FALLING - GPIO_
MODE_ INPUT - GPIO_
MODE_ IT_ FALLING - GPIO_
MODE_ IT_ RISING - GPIO_
MODE_ IT_ RISING_ FALLING - GPIO_
MODE_ OUTPUT_ OD - GPIO_
MODE_ OUTPUT_ PP - GPIO_
NOPULL - GPIO_
ODR_ OD0 - GPIO_
ODR_ OD0_ Msk - GPIO_
ODR_ OD0_ Pos - GPIO_
ODR_ OD1 - GPIO_
ODR_ OD2 - GPIO_
ODR_ OD3 - GPIO_
ODR_ OD4 - GPIO_
ODR_ OD5 - GPIO_
ODR_ OD6 - GPIO_
ODR_ OD7 - GPIO_
ODR_ OD8 - GPIO_
ODR_ OD9 - GPIO_
ODR_ OD1_ Msk - GPIO_
ODR_ OD1_ Pos - GPIO_
ODR_ OD2_ Msk - GPIO_
ODR_ OD2_ Pos - GPIO_
ODR_ OD3_ Msk - GPIO_
ODR_ OD3_ Pos - GPIO_
ODR_ OD4_ Msk - GPIO_
ODR_ OD4_ Pos - GPIO_
ODR_ OD5_ Msk - GPIO_
ODR_ OD5_ Pos - GPIO_
ODR_ OD6_ Msk - GPIO_
ODR_ OD6_ Pos - GPIO_
ODR_ OD7_ Msk - GPIO_
ODR_ OD7_ Pos - GPIO_
ODR_ OD8_ Msk - GPIO_
ODR_ OD8_ Pos - GPIO_
ODR_ OD9_ Msk - GPIO_
ODR_ OD9_ Pos - GPIO_
ODR_ OD10 - GPIO_
ODR_ OD11 - GPIO_
ODR_ OD12 - GPIO_
ODR_ OD13 - GPIO_
ODR_ OD14 - GPIO_
ODR_ OD15 - GPIO_
ODR_ OD10_ Msk - GPIO_
ODR_ OD10_ Pos - GPIO_
ODR_ OD11_ Msk - GPIO_
ODR_ OD11_ Pos - GPIO_
ODR_ OD12_ Msk - GPIO_
ODR_ OD12_ Pos - GPIO_
ODR_ OD13_ Msk - GPIO_
ODR_ OD13_ Pos - GPIO_
ODR_ OD14_ Msk - GPIO_
ODR_ OD14_ Pos - GPIO_
ODR_ OD15_ Msk - GPIO_
ODR_ OD15_ Pos - GPIO_
OSPEEDR_ OSPEE D0 - GPIO_
OSPEEDR_ OSPEE D0_ 0 - GPIO_
OSPEEDR_ OSPEE D0_ 1 - GPIO_
OSPEEDR_ OSPEE D0_ Msk - GPIO_
OSPEEDR_ OSPEE D0_ Pos - GPIO_
OSPEEDR_ OSPEE D1 - GPIO_
OSPEEDR_ OSPEE D2 - GPIO_
OSPEEDR_ OSPEE D3 - GPIO_
OSPEEDR_ OSPEE D4 - GPIO_
OSPEEDR_ OSPEE D5 - GPIO_
OSPEEDR_ OSPEE D6 - GPIO_
OSPEEDR_ OSPEE D7 - GPIO_
OSPEEDR_ OSPEE D8 - GPIO_
OSPEEDR_ OSPEE D9 - GPIO_
OSPEEDR_ OSPEE D1_ 0 - GPIO_
OSPEEDR_ OSPEE D1_ 1 - GPIO_
OSPEEDR_ OSPEE D1_ Msk - GPIO_
OSPEEDR_ OSPEE D1_ Pos - GPIO_
OSPEEDR_ OSPEE D2_ 0 - GPIO_
OSPEEDR_ OSPEE D2_ 1 - GPIO_
OSPEEDR_ OSPEE D2_ Msk - GPIO_
OSPEEDR_ OSPEE D2_ Pos - GPIO_
OSPEEDR_ OSPEE D3_ 0 - GPIO_
OSPEEDR_ OSPEE D3_ 1 - GPIO_
OSPEEDR_ OSPEE D3_ Msk - GPIO_
OSPEEDR_ OSPEE D3_ Pos - GPIO_
OSPEEDR_ OSPEE D4_ 0 - GPIO_
OSPEEDR_ OSPEE D4_ 1 - GPIO_
OSPEEDR_ OSPEE D4_ Msk - GPIO_
OSPEEDR_ OSPEE D4_ Pos - GPIO_
OSPEEDR_ OSPEE D5_ 0 - GPIO_
OSPEEDR_ OSPEE D5_ 1 - GPIO_
OSPEEDR_ OSPEE D5_ Msk - GPIO_
OSPEEDR_ OSPEE D5_ Pos - GPIO_
OSPEEDR_ OSPEE D6_ 0 - GPIO_
OSPEEDR_ OSPEE D6_ 1 - GPIO_
OSPEEDR_ OSPEE D6_ Msk - GPIO_
OSPEEDR_ OSPEE D6_ Pos - GPIO_
OSPEEDR_ OSPEE D7_ 0 - GPIO_
OSPEEDR_ OSPEE D7_ 1 - GPIO_
OSPEEDR_ OSPEE D7_ Msk - GPIO_
OSPEEDR_ OSPEE D7_ Pos - GPIO_
OSPEEDR_ OSPEE D8_ 0 - GPIO_
OSPEEDR_ OSPEE D8_ 1 - GPIO_
OSPEEDR_ OSPEE D8_ Msk - GPIO_
OSPEEDR_ OSPEE D8_ Pos - GPIO_
OSPEEDR_ OSPEE D9_ 0 - GPIO_
OSPEEDR_ OSPEE D9_ 1 - GPIO_
OSPEEDR_ OSPEE D9_ Msk - GPIO_
OSPEEDR_ OSPEE D9_ Pos - GPIO_
OSPEEDR_ OSPEE D10 - GPIO_
OSPEEDR_ OSPEE D11 - GPIO_
OSPEEDR_ OSPEE D12 - GPIO_
OSPEEDR_ OSPEE D13 - GPIO_
OSPEEDR_ OSPEE D14 - GPIO_
OSPEEDR_ OSPEE D15 - GPIO_
OSPEEDR_ OSPEE D10_ 0 - GPIO_
OSPEEDR_ OSPEE D10_ 1 - GPIO_
OSPEEDR_ OSPEE D10_ Msk - GPIO_
OSPEEDR_ OSPEE D10_ Pos - GPIO_
OSPEEDR_ OSPEE D11_ 0 - GPIO_
OSPEEDR_ OSPEE D11_ 1 - GPIO_
OSPEEDR_ OSPEE D11_ Msk - GPIO_
OSPEEDR_ OSPEE D11_ Pos - GPIO_
OSPEEDR_ OSPEE D12_ 0 - GPIO_
OSPEEDR_ OSPEE D12_ 1 - GPIO_
OSPEEDR_ OSPEE D12_ Msk - GPIO_
OSPEEDR_ OSPEE D12_ Pos - GPIO_
OSPEEDR_ OSPEE D13_ 0 - GPIO_
OSPEEDR_ OSPEE D13_ 1 - GPIO_
OSPEEDR_ OSPEE D13_ Msk - GPIO_
OSPEEDR_ OSPEE D13_ Pos - GPIO_
OSPEEDR_ OSPEE D14_ 0 - GPIO_
OSPEEDR_ OSPEE D14_ 1 - GPIO_
OSPEEDR_ OSPEE D14_ Msk - GPIO_
OSPEEDR_ OSPEE D14_ Pos - GPIO_
OSPEEDR_ OSPEE D15_ 0 - GPIO_
OSPEEDR_ OSPEE D15_ 1 - GPIO_
OSPEEDR_ OSPEE D15_ Msk - GPIO_
OSPEEDR_ OSPEE D15_ Pos - GPIO_
OTYPER_ OT0 - GPIO_
OTYPER_ OT0_ Msk - GPIO_
OTYPER_ OT0_ Pos - GPIO_
OTYPER_ OT1 - GPIO_
OTYPER_ OT2 - GPIO_
OTYPER_ OT3 - GPIO_
OTYPER_ OT4 - GPIO_
OTYPER_ OT5 - GPIO_
OTYPER_ OT6 - GPIO_
OTYPER_ OT7 - GPIO_
OTYPER_ OT8 - GPIO_
OTYPER_ OT9 - GPIO_
OTYPER_ OT1_ Msk - GPIO_
OTYPER_ OT1_ Pos - GPIO_
OTYPER_ OT2_ Msk - GPIO_
OTYPER_ OT2_ Pos - GPIO_
OTYPER_ OT3_ Msk - GPIO_
OTYPER_ OT3_ Pos - GPIO_
OTYPER_ OT4_ Msk - GPIO_
OTYPER_ OT4_ Pos - GPIO_
OTYPER_ OT5_ Msk - GPIO_
OTYPER_ OT5_ Pos - GPIO_
OTYPER_ OT6_ Msk - GPIO_
OTYPER_ OT6_ Pos - GPIO_
OTYPER_ OT7_ Msk - GPIO_
OTYPER_ OT7_ Pos - GPIO_
OTYPER_ OT8_ Msk - GPIO_
OTYPER_ OT8_ Pos - GPIO_
OTYPER_ OT9_ Msk - GPIO_
OTYPER_ OT9_ Pos - GPIO_
OTYPER_ OT10 - GPIO_
OTYPER_ OT11 - GPIO_
OTYPER_ OT12 - GPIO_
OTYPER_ OT13 - GPIO_
OTYPER_ OT14 - GPIO_
OTYPER_ OT15 - GPIO_
OTYPER_ OT10_ Msk - GPIO_
OTYPER_ OT10_ Pos - GPIO_
OTYPER_ OT11_ Msk - GPIO_
OTYPER_ OT11_ Pos - GPIO_
OTYPER_ OT12_ Msk - GPIO_
OTYPER_ OT12_ Pos - GPIO_
OTYPER_ OT13_ Msk - GPIO_
OTYPER_ OT13_ Pos - GPIO_
OTYPER_ OT14_ Msk - GPIO_
OTYPER_ OT14_ Pos - GPIO_
OTYPER_ OT15_ Msk - GPIO_
OTYPER_ OT15_ Pos - GPIO_
PIN_ 0 - GPIO_
PIN_ 1 - GPIO_
PIN_ 2 - GPIO_
PIN_ 3 - GPIO_
PIN_ 4 - GPIO_
PIN_ 5 - GPIO_
PIN_ 6 - GPIO_
PIN_ 7 - GPIO_
PIN_ 8 - GPIO_
PIN_ 9 - GPIO_
PIN_ 10 - GPIO_
PIN_ 11 - GPIO_
PIN_ 12 - GPIO_
PIN_ 13 - GPIO_
PIN_ 14 - GPIO_
PIN_ 15 - GPIO_
PIN_ All - GPIO_
PIN_ MASK - GPIO_
PULLDOWN - GPIO_
PULLUP - GPIO_
PUPDR_ PUPD0 - GPIO_
PUPDR_ PUPD0_ 0 - GPIO_
PUPDR_ PUPD0_ 1 - GPIO_
PUPDR_ PUPD0_ Msk - GPIO_
PUPDR_ PUPD0_ Pos - GPIO_
PUPDR_ PUPD1 - GPIO_
PUPDR_ PUPD2 - GPIO_
PUPDR_ PUPD3 - GPIO_
PUPDR_ PUPD4 - GPIO_
PUPDR_ PUPD5 - GPIO_
PUPDR_ PUPD6 - GPIO_
PUPDR_ PUPD7 - GPIO_
PUPDR_ PUPD8 - GPIO_
PUPDR_ PUPD9 - GPIO_
PUPDR_ PUPD1_ 0 - GPIO_
PUPDR_ PUPD1_ 1 - GPIO_
PUPDR_ PUPD1_ Msk - GPIO_
PUPDR_ PUPD1_ Pos - GPIO_
PUPDR_ PUPD2_ 0 - GPIO_
PUPDR_ PUPD2_ 1 - GPIO_
PUPDR_ PUPD2_ Msk - GPIO_
PUPDR_ PUPD2_ Pos - GPIO_
PUPDR_ PUPD3_ 0 - GPIO_
PUPDR_ PUPD3_ 1 - GPIO_
PUPDR_ PUPD3_ Msk - GPIO_
PUPDR_ PUPD3_ Pos - GPIO_
PUPDR_ PUPD4_ 0 - GPIO_
PUPDR_ PUPD4_ 1 - GPIO_
PUPDR_ PUPD4_ Msk - GPIO_
PUPDR_ PUPD4_ Pos - GPIO_
PUPDR_ PUPD5_ 0 - GPIO_
PUPDR_ PUPD5_ 1 - GPIO_
PUPDR_ PUPD5_ Msk - GPIO_
PUPDR_ PUPD5_ Pos - GPIO_
PUPDR_ PUPD6_ 0 - GPIO_
PUPDR_ PUPD6_ 1 - GPIO_
PUPDR_ PUPD6_ Msk - GPIO_
PUPDR_ PUPD6_ Pos - GPIO_
PUPDR_ PUPD7_ 0 - GPIO_
PUPDR_ PUPD7_ 1 - GPIO_
PUPDR_ PUPD7_ Msk - GPIO_
PUPDR_ PUPD7_ Pos - GPIO_
PUPDR_ PUPD8_ 0 - GPIO_
PUPDR_ PUPD8_ 1 - GPIO_
PUPDR_ PUPD8_ Msk - GPIO_
PUPDR_ PUPD8_ Pos - GPIO_
PUPDR_ PUPD9_ 0 - GPIO_
PUPDR_ PUPD9_ 1 - GPIO_
PUPDR_ PUPD9_ Msk - GPIO_
PUPDR_ PUPD9_ Pos - GPIO_
PUPDR_ PUPD10 - GPIO_
PUPDR_ PUPD11 - GPIO_
PUPDR_ PUPD12 - GPIO_
PUPDR_ PUPD13 - GPIO_
PUPDR_ PUPD14 - GPIO_
PUPDR_ PUPD15 - GPIO_
PUPDR_ PUPD10_ 0 - GPIO_
PUPDR_ PUPD10_ 1 - GPIO_
PUPDR_ PUPD10_ Msk - GPIO_
PUPDR_ PUPD10_ Pos - GPIO_
PUPDR_ PUPD11_ 0 - GPIO_
PUPDR_ PUPD11_ 1 - GPIO_
PUPDR_ PUPD11_ Msk - GPIO_
PUPDR_ PUPD11_ Pos - GPIO_
PUPDR_ PUPD12_ 0 - GPIO_
PUPDR_ PUPD12_ 1 - GPIO_
PUPDR_ PUPD12_ Msk - GPIO_
PUPDR_ PUPD12_ Pos - GPIO_
PUPDR_ PUPD13_ 0 - GPIO_
PUPDR_ PUPD13_ 1 - GPIO_
PUPDR_ PUPD13_ Msk - GPIO_
PUPDR_ PUPD13_ Pos - GPIO_
PUPDR_ PUPD14_ 0 - GPIO_
PUPDR_ PUPD14_ 1 - GPIO_
PUPDR_ PUPD14_ Msk - GPIO_
PUPDR_ PUPD14_ Pos - GPIO_
PUPDR_ PUPD15_ 0 - GPIO_
PUPDR_ PUPD15_ 1 - GPIO_
PUPDR_ PUPD15_ Msk - GPIO_
PUPDR_ PUPD15_ Pos - GPIO_
PinState_ GPIO_ PIN_ RESET - GPIO_
PinState_ GPIO_ PIN_ SET - GPIO_
SPEED_ FREQ_ HIGH - GPIO_
SPEED_ FREQ_ LOW - GPIO_
SPEED_ FREQ_ MEDIUM - GPIO_
SPEED_ FREQ_ VERY_ HIGH - HAL_
ADC_ ERROR_ DMA - HAL_
ADC_ ERROR_ INTERNAL - HAL_
ADC_ ERROR_ NONE - HAL_
ADC_ ERROR_ OVR - HAL_
ADC_ STATE_ AWD1 - HAL_
ADC_ STATE_ AWD2 - HAL_
ADC_ STATE_ AWD3 - HAL_
ADC_ STATE_ BUSY_ INTERNAL - HAL_
ADC_ STATE_ ERROR_ CONFIG - HAL_
ADC_ STATE_ ERROR_ DMA - HAL_
ADC_ STATE_ ERROR_ INTERNAL - HAL_
ADC_ STATE_ INJ_ BUSY - HAL_
ADC_ STATE_ INJ_ EOC - HAL_
ADC_ STATE_ INJ_ JQOVF - HAL_
ADC_ STATE_ MULTIMODE_ SLAVE - HAL_
ADC_ STATE_ READY - HAL_
ADC_ STATE_ REG_ BUSY - HAL_
ADC_ STATE_ REG_ EOC - HAL_
ADC_ STATE_ REG_ EOSMP - HAL_
ADC_ STATE_ REG_ OVR - HAL_
ADC_ STATE_ RESET - HAL_
ADC_ STATE_ TIMEOUT - HAL_
CRC_ State Type Def_ HAL_ CRC_ STATE_ BUSY - < CRC internal process is ongoing
- HAL_
CRC_ State Type Def_ HAL_ CRC_ STATE_ ERROR - < CRC error state
- HAL_
CRC_ State Type Def_ HAL_ CRC_ STATE_ READY - < CRC initialized and ready for use
- HAL_
CRC_ State Type Def_ HAL_ CRC_ STATE_ RESET - < CRC not yet initialized or disabled
- HAL_
CRC_ State Type Def_ HAL_ CRC_ STATE_ TIMEOUT - < CRC timeout state
- HAL_
DMA_ CallbackID Type Def_ HAL_ DMA_ XFER_ ABORT_ CB_ ID - < Abort
- HAL_
DMA_ CallbackID Type Def_ HAL_ DMA_ XFER_ ALL_ CB_ ID - < All
- HAL_
DMA_ CallbackID Type Def_ HAL_ DMA_ XFER_ CPLT_ CB_ ID - < Full transfer
- HAL_
DMA_ CallbackID Type Def_ HAL_ DMA_ XFER_ ERROR_ CB_ ID - < Error
- HAL_
DMA_ CallbackID Type Def_ HAL_ DMA_ XFER_ HALFCPLT_ CB_ ID - < Half transfer
- HAL_
DMA_ ERROR_ NONE - HAL_
DMA_ ERROR_ NOT_ SUPPORTED - HAL_
DMA_ ERROR_ NO_ XFER - HAL_
DMA_ ERROR_ TE - HAL_
DMA_ ERROR_ TIMEOUT - HAL_
DMA_ Level Complete Type Def_ HAL_ DMA_ FULL_ TRANSFER - < Full transfer
- HAL_
DMA_ Level Complete Type Def_ HAL_ DMA_ HALF_ TRANSFER - < Half Transfer
- HAL_
DMA_ State Type Def_ HAL_ DMA_ STATE_ BUSY - < DMA process is ongoing
- HAL_
DMA_ State Type Def_ HAL_ DMA_ STATE_ READY - < DMA initialized and ready for use
- HAL_
DMA_ State Type Def_ HAL_ DMA_ STATE_ RESET - < DMA not yet initialized or disabled
- HAL_
DMA_ State Type Def_ HAL_ DMA_ STATE_ TIMEOUT - < DMA timeout state
- HAL_
FLASH_ ERROR_ NONE - HAL_
FLASH_ ERROR_ OPTV - HAL_
FLASH_ ERROR_ WRP - HAL_
I2C_ ERROR_ AF - HAL_
I2C_ ERROR_ ARLO - HAL_
I2C_ ERROR_ BERR - HAL_
I2C_ ERROR_ DMA - HAL_
I2C_ ERROR_ DMA_ PARAM - HAL_
I2C_ ERROR_ NONE - HAL_
I2C_ ERROR_ OVR - HAL_
I2C_ ERROR_ SIZE - HAL_
I2C_ ERROR_ TIMEOUT - HAL_
I2C_ Mode Type Def_ HAL_ I2C_ MODE_ MASTER - < I2C communication is in Master Mode
- HAL_
I2C_ Mode Type Def_ HAL_ I2C_ MODE_ MEM - < I2C communication is in Memory Mode
- HAL_
I2C_ Mode Type Def_ HAL_ I2C_ MODE_ NONE - < No I2C communication on going
- HAL_
I2C_ Mode Type Def_ HAL_ I2C_ MODE_ SLAVE - < I2C communication is in Slave Mode
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ ABORT - < Abort user request ongoing
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ BUSY - < An internal process is ongoing
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ BUSY_ RX - < Data Reception process is ongoing
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ BUSY_ RX_ LISTEN - < Address Listen Mode and Data Reception process is ongoing
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ BUSY_ TX - < Data Transmission process is ongoing
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ BUSY_ TX_ LISTEN - < Address Listen Mode and Data Transmission process is ongoing
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ ERROR - < Error
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ LISTEN - < Address Listen Mode is ongoing
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ READY - < Peripheral Initialized and ready for use
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ RESET - < Peripheral is not yet Initialized
- HAL_
I2C_ State Type Def_ HAL_ I2C_ STATE_ TIMEOUT - < Timeout state
- HAL_
LED_ State Type Def_ HAL_ LED_ STATE_ BUSY - < an internal process is ongoing
- HAL_
LED_ State Type Def_ HAL_ LED_ STATE_ ERROR - < Error
- HAL_
LED_ State Type Def_ HAL_ LED_ STATE_ READY - < Peripheral Initialized and ready for use
- HAL_
LED_ State Type Def_ HAL_ LED_ STATE_ RESET - < Peripheral is not yet Initialized
- HAL_
LED_ State Type Def_ HAL_ LED_ STATE_ TIMEOUT - < Timeout state
- HAL_
LPTIM_ State Type Def_ HAL_ LPTIM_ STATE_ BUSY - < An internal process is ongoing
- HAL_
LPTIM_ State Type Def_ HAL_ LPTIM_ STATE_ ERROR - < Internal Process is ongoing
- HAL_
LPTIM_ State Type Def_ HAL_ LPTIM_ STATE_ READY - < Peripheral Initialized and ready for use
- HAL_
LPTIM_ State Type Def_ HAL_ LPTIM_ STATE_ RESET - < Peripheral not yet initialized or disabled
- HAL_
LPTIM_ State Type Def_ HAL_ LPTIM_ STATE_ TIMEOUT - < Timeout state
- HAL_
Lock Type Def_ HAL_ LOCKED - HAL_
Lock Type Def_ HAL_ UNLOCKED - HAL_
MAX_ DELAY - HAL_
RTCState Type Def_ HAL_ RTC_ STATE_ BUSY - < RTC process is ongoing
- HAL_
RTCState Type Def_ HAL_ RTC_ STATE_ ERROR - < RTC error state
- HAL_
RTCState Type Def_ HAL_ RTC_ STATE_ READY - < RTC initialized and ready for use
- HAL_
RTCState Type Def_ HAL_ RTC_ STATE_ RESET - < RTC not yet initialized or disabled
- HAL_
RTCState Type Def_ HAL_ RTC_ STATE_ TIMEOUT - < RTC timeout state
- HAL_
SPI_ ERROR_ ABORT - HAL_
SPI_ ERROR_ DMA - HAL_
SPI_ ERROR_ FLAG - HAL_
SPI_ ERROR_ FRE - HAL_
SPI_ ERROR_ MODF - HAL_
SPI_ ERROR_ NONE - HAL_
SPI_ ERROR_ OVR - HAL_
SPI_ State Type Def_ HAL_ SPI_ STATE_ ABORT - < SPI abort is ongoing
- HAL_
SPI_ State Type Def_ HAL_ SPI_ STATE_ BUSY - < an internal process is ongoing
- HAL_
SPI_ State Type Def_ HAL_ SPI_ STATE_ BUSY_ RX - < Data Reception process is ongoing
- HAL_
SPI_ State Type Def_ HAL_ SPI_ STATE_ BUSY_ TX - < Data Transmission process is ongoing
- HAL_
SPI_ State Type Def_ HAL_ SPI_ STATE_ BUSY_ TX_ RX - < Data Transmission and Reception process is ongoing
- HAL_
SPI_ State Type Def_ HAL_ SPI_ STATE_ ERROR - < SPI error state
- HAL_
SPI_ State Type Def_ HAL_ SPI_ STATE_ READY - < Peripheral Initialized and ready for use
- HAL_
SPI_ State Type Def_ HAL_ SPI_ STATE_ RESET - < Peripheral not Initialized
- HAL_
Status Type Def_ HAL_ BUSY - HAL_
Status Type Def_ HAL_ ERROR - HAL_
Status Type Def_ HAL_ OK - HAL_
Status Type Def_ HAL_ TIMEOUT - HAL_
TIM_ Active Channel_ HAL_ TIM_ ACTIVE_ CHANNEL_ 1 - < The active channel is 1
- HAL_
TIM_ Active Channel_ HAL_ TIM_ ACTIVE_ CHANNEL_ 2 - < The active channel is 2
- HAL_
TIM_ Active Channel_ HAL_ TIM_ ACTIVE_ CHANNEL_ 3 - < The active channel is 3
- HAL_
TIM_ Active Channel_ HAL_ TIM_ ACTIVE_ CHANNEL_ 4 - < The active channel is 4
- HAL_
TIM_ Active Channel_ HAL_ TIM_ ACTIVE_ CHANNEL_ CLEARED - < All active channels cleared
- HAL_
TIM_ State Type Def_ HAL_ TIM_ STATE_ BUSY - < An internal process is ongoing
- HAL_
TIM_ State Type Def_ HAL_ TIM_ STATE_ ERROR - < Reception process is ongoing
- HAL_
TIM_ State Type Def_ HAL_ TIM_ STATE_ READY - < Peripheral Initialized and ready for use
- HAL_
TIM_ State Type Def_ HAL_ TIM_ STATE_ RESET - < Peripheral not yet initialized or disabled
- HAL_
TIM_ State Type Def_ HAL_ TIM_ STATE_ TIMEOUT - < Timeout state
- HAL_
Tick Freq Type Def_ HAL_ TICK_ FREQ_ 1KHZ - HAL_
Tick Freq Type Def_ HAL_ TICK_ FREQ_ 10HZ - HAL_
Tick Freq Type Def_ HAL_ TICK_ FREQ_ 100HZ - HAL_
Tick Freq Type Def_ HAL_ TICK_ FREQ_ DEFAULT - HAL_
UART_ ERROR_ DMA - HAL_
UART_ ERROR_ FE - HAL_
UART_ ERROR_ NE - HAL_
UART_ ERROR_ NONE - HAL_
UART_ ERROR_ ORE - HAL_
UART_ ERROR_ PE - HAL_
UART_ State Type Def_ HAL_ UART_ STATE_ BUSY - < an internal process is ongoing Value is allowed for gState only
- HAL_
UART_ State Type Def_ HAL_ UART_ STATE_ BUSY_ RX - < Data Reception process is ongoing Value is allowed for RxState only
- HAL_
UART_ State Type Def_ HAL_ UART_ STATE_ BUSY_ TX - < Data Transmission process is ongoing Value is allowed for gState only
- HAL_
UART_ State Type Def_ HAL_ UART_ STATE_ BUSY_ TX_ RX - < Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values
- HAL_
UART_ State Type Def_ HAL_ UART_ STATE_ ERROR - < Error Value is allowed for gState only
- HAL_
UART_ State Type Def_ HAL_ UART_ STATE_ READY - < Peripheral Initialized and ready for use Value is allowed for gState and RxState
- HAL_
UART_ State Type Def_ HAL_ UART_ STATE_ RESET - < Peripheral is not yet Initialized Value is allowed for gState and RxState
- HAL_
UART_ State Type Def_ HAL_ UART_ STATE_ TIMEOUT - < Timeout state Value is allowed for gState only
- HSE_
STARTUP_ TIMEOUT - HSE_
VALUE - HSI_
VALUE - I2C
- I2C1
- I2C_
BASE - I2C_
CCR_ CCR - I2C_
CCR_ CCR_ Msk - I2C_
CCR_ CCR_ Pos - I2C_
CCR_ DUTY - I2C_
CCR_ DUTY_ Msk - I2C_
CCR_ DUTY_ Pos - I2C_
CCR_ FS - I2C_
CCR_ FS_ Msk - I2C_
CCR_ FS_ Pos - I2C_
CR1_ ACK - I2C_
CR1_ ACK_ Msk - I2C_
CR1_ ACK_ Pos - I2C_
CR1_ ENGC - I2C_
CR1_ ENGC_ Msk - I2C_
CR1_ ENGC_ Pos - I2C_
CR1_ NOSTRETCH - I2C_
CR1_ NOSTRETCH_ Msk - I2C_
CR1_ NOSTRETCH_ Pos - I2C_
CR1_ PE - I2C_
CR1_ PE_ Msk - I2C_
CR1_ PE_ Pos - I2C_
CR1_ POS - I2C_
CR1_ POS_ Msk - I2C_
CR1_ POS_ Pos - I2C_
CR1_ START - I2C_
CR1_ START_ Msk - I2C_
CR1_ START_ Pos - I2C_
CR1_ STOP - I2C_
CR1_ STOP_ Msk - I2C_
CR1_ STOP_ Pos - I2C_
CR1_ SWRST - I2C_
CR1_ SWRST_ Msk - I2C_
CR1_ SWRST_ Pos - I2C_
CR2_ DMAEN - I2C_
CR2_ DMAEN_ Msk - I2C_
CR2_ DMAEN_ Pos - I2C_
CR2_ FREQ - I2C_
CR2_ FREQ_ 0 - I2C_
CR2_ FREQ_ 1 - I2C_
CR2_ FREQ_ 2 - I2C_
CR2_ FREQ_ 3 - I2C_
CR2_ FREQ_ 4 - I2C_
CR2_ FREQ_ 5 - I2C_
CR2_ FREQ_ Msk - I2C_
CR2_ FREQ_ Pos - I2C_
CR2_ ITBUFEN - I2C_
CR2_ ITBUFEN_ Msk - I2C_
CR2_ ITBUFEN_ Pos - I2C_
CR2_ ITERREN - I2C_
CR2_ ITERREN_ Msk - I2C_
CR2_ ITERREN_ Pos - I2C_
CR2_ ITEVTEN - I2C_
CR2_ ITEVTEN_ Msk - I2C_
CR2_ ITEVTEN_ Pos - I2C_
CR2_ LAST - I2C_
CR2_ LAST_ Msk - I2C_
CR2_ LAST_ Pos - I2C_
DIRECTION_ RECEIVE - I2C_
DIRECTION_ TRANSMIT - I2C_
DR_ DR - I2C_
DR_ DR_ 0 - I2C_
DR_ DR_ 1 - I2C_
DR_ DR_ 2 - I2C_
DR_ DR_ 3 - I2C_
DR_ DR_ 4 - I2C_
DR_ DR_ 5 - I2C_
DR_ DR_ 6 - I2C_
DR_ DR_ 7 - I2C_
DR_ DR_ Msk - I2C_
DR_ DR_ Pos - I2C_
DUTYCYCLE_ 2 - I2C_
DUTYCYCLE_ 16_ 9 - I2C_
FIRST_ AND_ LAST_ FRAME - I2C_
FIRST_ AND_ NEXT_ FRAME - I2C_
FIRST_ FRAME - I2C_
FLAG_ ADD10 - I2C_
FLAG_ ADDR - I2C_
FLAG_ AF - I2C_
FLAG_ ARLO - I2C_
FLAG_ BERR - I2C_
FLAG_ BTF - I2C_
FLAG_ BUSY - I2C_
FLAG_ DUALF - I2C_
FLAG_ GENCALL - I2C_
FLAG_ MASK - I2C_
FLAG_ MSL - I2C_
FLAG_ OVR - I2C_
FLAG_ RXNE - I2C_
FLAG_ SB - I2C_
FLAG_ STOPF - I2C_
FLAG_ TRA - I2C_
FLAG_ TXE - I2C_
GENERALCALL_ DISABLE - I2C_
GENERALCALL_ ENABLE - I2C_
IT_ BUF - I2C_
IT_ ERR - I2C_
IT_ EVT - I2C_
LAST_ FRAME - I2C_
LAST_ FRAME_ NO_ STOP - I2C_
MEMADD_ SIZE_ 8BIT - I2C_
MEMADD_ SIZE_ 16BIT - I2C_
MIN_ PCLK_ FREQ_ FAST - I2C_
MIN_ PCLK_ FREQ_ STANDARD - I2C_
NEXT_ FRAME - I2C_
NOSTRETCH_ DISABLE - I2C_
NOSTRETCH_ ENABLE - I2C_
OAR1_ ADD1 - I2C_
OAR1_ ADD2 - I2C_
OAR1_ ADD3 - I2C_
OAR1_ ADD4 - I2C_
OAR1_ ADD5 - I2C_
OAR1_ ADD6 - I2C_
OAR1_ ADD7 - I2C_
OAR1_ ADD1_ 7 - I2C_
OAR1_ ADD1_ Msk - I2C_
OAR1_ ADD1_ Pos - I2C_
OAR1_ ADD2_ Msk - I2C_
OAR1_ ADD2_ Pos - I2C_
OAR1_ ADD3_ Msk - I2C_
OAR1_ ADD3_ Pos - I2C_
OAR1_ ADD4_ Msk - I2C_
OAR1_ ADD4_ Pos - I2C_
OAR1_ ADD5_ Msk - I2C_
OAR1_ ADD5_ Pos - I2C_
OAR1_ ADD6_ Msk - I2C_
OAR1_ ADD6_ Pos - I2C_
OAR1_ ADD7_ Msk - I2C_
OAR1_ ADD7_ Pos - I2C_
OTHER_ AND_ LAST_ FRAME - I2C_
OTHER_ FRAME - I2C_
SR1_ ADDR - I2C_
SR1_ ADDR_ Msk - I2C_
SR1_ ADDR_ Pos - I2C_
SR1_ AF - I2C_
SR1_ AF_ Msk - I2C_
SR1_ AF_ Pos - I2C_
SR1_ ARLO - I2C_
SR1_ ARLO_ Msk - I2C_
SR1_ ARLO_ Pos - I2C_
SR1_ BERR - I2C_
SR1_ BERR_ Msk - I2C_
SR1_ BERR_ Pos - I2C_
SR1_ BTF - I2C_
SR1_ BTF_ Msk - I2C_
SR1_ BTF_ Pos - I2C_
SR1_ OVR - I2C_
SR1_ OVR_ Msk - I2C_
SR1_ OVR_ Pos - I2C_
SR1_ PECERR - I2C_
SR1_ PECERR_ Msk - I2C_
SR1_ PECERR_ Pos - I2C_
SR1_ RXNE - I2C_
SR1_ RXNE_ Msk - I2C_
SR1_ RXNE_ Pos - I2C_
SR1_ SB - I2C_
SR1_ SB_ Msk - I2C_
SR1_ SB_ Pos - I2C_
SR1_ STOPF - I2C_
SR1_ STOPF_ Msk - I2C_
SR1_ STOPF_ Pos - I2C_
SR1_ TXE - I2C_
SR1_ TXE_ Msk - I2C_
SR1_ TXE_ Pos - I2C_
SR2_ BUSY - I2C_
SR2_ BUSY_ Msk - I2C_
SR2_ BUSY_ Pos - I2C_
SR2_ GENCALL - I2C_
SR2_ GENCALL_ Msk - I2C_
SR2_ GENCALL_ Pos - I2C_
SR2_ MSL - I2C_
SR2_ MSL_ Msk - I2C_
SR2_ MSL_ Pos - I2C_
SR2_ PEC - I2C_
SR2_ PEC_ Msk - I2C_
SR2_ PEC_ Pos - I2C_
SR2_ TRA - I2C_
SR2_ TRA_ Msk - I2C_
SR2_ TRA_ Pos - I2C_
TRISE_ TRISE - I2C_
TRISE_ TRISE_ Msk - I2C_
TRISE_ TRISE_ Pos - IOPORT_
BASE - IPSR_
ISR_ Msk - IPSR_
ISR_ Pos - IRQn_
Type_ ADC_ COMP_ IRQn - < ADC&COMP Interrupts
- IRQn_
Type_ DMA1_ Channel1_ IRQn - < DMA1 Channel 1 Interrupt
- IRQn_
Type_ DMA1_ Channel2_ 3_ IRQn - < DMA1 Channel 2 and Channel 3 Interrupts
- IRQn_
Type_ EXTI0_ 1_ IRQn - < EXTI 0 and 1 Interrupts
- IRQn_
Type_ EXTI2_ 3_ IRQn - < EXTI Line 2 and 3 Interrupts
- IRQn_
Type_ EXTI4_ 15_ IRQn - < EXTI Line 4 to 15 Interrupts
- IRQn_
Type_ FLASH_ IRQn - < FLASH global Interrupt
- IRQn_
Type_ Hard Fault_ IRQn - < 3 Cortex-M Hard Fault Interrupt
- IRQn_
Type_ I2C1_ IRQn - < I2C1 Interrupt (combined with EXTI 23)
- IRQn_
Type_ LED_ IRQn - < LED global Interrupt
- IRQn_
Type_ LPTI M1_ IRQn - < LPTIM1 global Interrupts
- IRQn_
Type_ NonMaskable Int_ IRQn - < 2 Non Maskable Interrupt
- IRQn_
Type_ PVD_ IRQn - < PVD through EXTI Line detection Interrupt(EXTI line 16)
- IRQn_
Type_ PendSV_ IRQn - < 14 Cortex-M Pend SV Interrupt
- IRQn_
Type_ RCC_ IRQn - < RCC global Interrupt
- IRQn_
Type_ RTC_ IRQn - < RTC interrupt through the EXTI line 19
- IRQn_
Type_ SPI1_ IRQn - < SPI1 Interrupt
- IRQn_
Type_ SPI2_ IRQn - < SPI2 Interrupt
- IRQn_
Type_ SVC_ IRQn - < 11 Cortex-M SV Call Interrupt
- IRQn_
Type_ SysTick_ IRQn - < 15 Cortex-M System Tick Interrupt
- IRQn_
Type_ TIM1_ BRK_ UP_ TRG_ COM_ IRQn - < TIM1 Break, Update, Trigger and Commutation Interrupts
- IRQn_
Type_ TIM1_ CC_ IRQn - < TIM1 Capture Compare Interrupt
- IRQn_
Type_ TIM3_ IRQn - < TIM3 global Interrupt
- IRQn_
Type_ TIM14_ IRQn - < TIM14 global Interrupt
- IRQn_
Type_ TIM16_ IRQn - < TIM16 global Interrupt
- IRQn_
Type_ TIM17_ IRQn - < TIM17 global Interrupt
- IRQn_
Type_ USAR T1_ IRQn - < USART1 Interrupt
- IRQn_
Type_ USAR T2_ IRQn - < USART2 Interrupt
- IRQn_
Type_ WWDG_ IRQn - < Window WatchDog Interrupt
- IWDG
- IWDG_
BASE - IWDG_
KEY_ ENABLE - IWDG_
KEY_ RELOAD - IWDG_
KEY_ WRITE_ ACCESS_ DISABLE - IWDG_
KEY_ WRITE_ ACCESS_ ENABLE - IWDG_
KR_ KEY - IWDG_
KR_ KEY_ Msk - IWDG_
KR_ KEY_ Pos - IWDG_
PRESCALER_ 4 - IWDG_
PRESCALER_ 8 - IWDG_
PRESCALER_ 16 - IWDG_
PRESCALER_ 32 - IWDG_
PRESCALER_ 64 - IWDG_
PRESCALER_ 128 - IWDG_
PRESCALER_ 256 - IWDG_
PR_ PR - IWDG_
PR_ PR_ 0 - IWDG_
PR_ PR_ 1 - IWDG_
PR_ PR_ 2 - IWDG_
PR_ PR_ Msk - IWDG_
PR_ PR_ Pos - IWDG_
RLR_ RL - IWDG_
RLR_ RL_ Msk - IWDG_
RLR_ RL_ Pos - IWDG_
SR_ PVU - IWDG_
SR_ PVU_ Msk - IWDG_
SR_ PVU_ Pos - IWDG_
SR_ RVU - IWDG_
SR_ RVU_ Msk - IWDG_
SR_ RVU_ Pos - LED
- LED_
BASE - LED_
COM0 - LED_
COM1 - LED_
COM2 - LED_
COM3 - LED_
COMDRIVE_ HIGH - LED_
COMDRIVE_ LOW - LED_
COM_ ALL - LED_
CR_ EHS - LED_
CR_ EHS_ Msk - LED_
CR_ EHS_ Pos - LED_
CR_ IE - LED_
CR_ IE_ Msk - LED_
CR_ IE_ Pos - LED_
CR_ LEDON - LED_
CR_ LEDON_ Msk - LED_
CR_ LEDON_ Pos - LED_
CR_ LED_ COM_ SEL - LED_
CR_ LED_ COM_ SEL_ 0 - LED_
CR_ LED_ COM_ SEL_ 1 - LED_
CR_ LED_ COM_ SEL_ Msk - LED_
CR_ LED_ COM_ SEL_ Pos - LED_
DISP_ 0 - LED_
DISP_ 1 - LED_
DISP_ 2 - LED_
DISP_ 3 - LED_
DISP_ 4 - LED_
DISP_ 5 - LED_
DISP_ 6 - LED_
DISP_ 7 - LED_
DISP_ 8 - LED_
DISP_ 9 - LED_
DISP_ A - LED_
DISP_ B - LED_
DISP_ C - LED_
DISP_ D - LED_
DISP_ DOT - LED_
DISP_ E - LED_
DISP_ F - LED_
DISP_ FULL - LED_
DISP_ H - LED_
DISP_ NONE - LED_
DISP_ P - LED_
DISP_ U - LED_
DR0_ DATA0 - LED_
DR0_ DATA0_ A - LED_
DR0_ DATA0_ B - LED_
DR0_ DATA0_ C - LED_
DR0_ DATA0_ D - LED_
DR0_ DATA0_ DP - LED_
DR0_ DATA0_ E - LED_
DR0_ DATA0_ F - LED_
DR0_ DATA0_ G - LED_
DR0_ DATA0_ Msk - LED_
DR0_ DATA0_ Pos - LED_
DR1_ DATA1 - LED_
DR1_ DATA1_ A - LED_
DR1_ DATA1_ B - LED_
DR1_ DATA1_ C - LED_
DR1_ DATA1_ D - LED_
DR1_ DATA1_ DP - LED_
DR1_ DATA1_ E - LED_
DR1_ DATA1_ F - LED_
DR1_ DATA1_ G - LED_
DR1_ DATA1_ Msk - LED_
DR1_ DATA1_ Pos - LED_
DR2_ DATA2 - LED_
DR2_ DATA2_ A - LED_
DR2_ DATA2_ B - LED_
DR2_ DATA2_ C - LED_
DR2_ DATA2_ D - LED_
DR2_ DATA2_ DP - LED_
DR2_ DATA2_ E - LED_
DR2_ DATA2_ F - LED_
DR2_ DATA2_ G - LED_
DR2_ DATA2_ Msk - LED_
DR2_ DATA2_ Pos - LED_
DR3_ DATA3 - LED_
DR3_ DATA3_ A - LED_
DR3_ DATA3_ B - LED_
DR3_ DATA3_ C - LED_
DR3_ DATA3_ D - LED_
DR3_ DATA3_ DP - LED_
DR3_ DATA3_ E - LED_
DR3_ DATA3_ F - LED_
DR3_ DATA3_ G - LED_
DR3_ DATA3_ Msk - LED_
DR3_ DATA3_ Pos - LED_
IR_ FLAG - LED_
IR_ FLAG_ Msk - LED_
IR_ FLAG_ Pos - LED_
PR_ PR - LED_
PR_ PR_ 0 - LED_
PR_ PR_ 1 - LED_
PR_ PR_ 2 - LED_
PR_ PR_ 3 - LED_
PR_ PR_ 4 - LED_
PR_ PR_ 5 - LED_
PR_ PR_ 6 - LED_
PR_ PR_ 7 - LED_
PR_ PR_ Msk - LED_
PR_ PR_ Pos - LED_
TR_ T1 - LED_
TR_ T2 - LED_
TR_ T1_ 0 - LED_
TR_ T1_ 1 - LED_
TR_ T1_ 2 - LED_
TR_ T1_ 3 - LED_
TR_ T1_ 4 - LED_
TR_ T1_ 5 - LED_
TR_ T1_ 6 - LED_
TR_ T1_ 7 - LED_
TR_ T1_ Msk - LED_
TR_ T1_ Pos - LED_
TR_ T2_ 0 - LED_
TR_ T2_ 1 - LED_
TR_ T2_ 2 - LED_
TR_ T2_ 3 - LED_
TR_ T2_ 4 - LED_
TR_ T2_ 5 - LED_
TR_ T2_ 6 - LED_
TR_ T2_ 7 - LED_
TR_ T2_ Msk - LED_
TR_ T2_ Pos - LPTIM
- LPTIM1
- LPTIM_
ARR_ ARR - LPTIM_
ARR_ ARR_ Msk - LPTIM_
ARR_ ARR_ Pos - LPTIM_
BASE - LPTIM_
CFGR_ PRELOAD - LPTIM_
CFGR_ PRELOAD_ Msk - LPTIM_
CFGR_ PRELOAD_ Pos - LPTIM_
CFGR_ PRESC - LPTIM_
CFGR_ PRESC_ 0 - LPTIM_
CFGR_ PRESC_ 1 - LPTIM_
CFGR_ PRESC_ 2 - LPTIM_
CFGR_ PRESC_ Msk - LPTIM_
CFGR_ PRESC_ Pos - LPTIM_
CNT_ CNT - LPTIM_
CNT_ CNT_ Msk - LPTIM_
CNT_ CNT_ Pos - LPTIM_
CR_ ENABLE - LPTIM_
CR_ ENABLE_ Msk - LPTIM_
CR_ ENABLE_ Pos - LPTIM_
CR_ RSTARE - LPTIM_
CR_ RSTARE_ Msk - LPTIM_
CR_ RSTARE_ Pos - LPTIM_
CR_ SNGSTRT - LPTIM_
CR_ SNGSTRT_ Msk - LPTIM_
CR_ SNGSTRT_ Pos - LPTIM_
FLAG_ ARRM - LPTIM_
ICR_ ARRMCF - LPTIM_
ICR_ ARRMCF_ Msk - LPTIM_
ICR_ ARRMCF_ Pos - LPTIM_
IER_ ARRMIE - LPTIM_
IER_ ARRMIE_ Msk - LPTIM_
IER_ ARRMIE_ Pos - LPTIM_
ISR_ ARRM - LPTIM_
ISR_ ARRM_ Msk - LPTIM_
ISR_ ARRM_ Pos - LPTIM_
IT_ ARRM - LPTIM_
PRESCALER_ DIV1 - LPTIM_
PRESCALER_ DIV2 - LPTIM_
PRESCALER_ DIV4 - LPTIM_
PRESCALER_ DIV8 - LPTIM_
PRESCALER_ DIV16 - LPTIM_
PRESCALER_ DIV32 - LPTIM_
PRESCALER_ DIV64 - LPTIM_
PRESCALER_ DIV128 - LPTIM_
UPDATE_ ENDOFPERIOD - LPTIM_
UPDATE_ IMMEDIATE - LSE_
STARTUP_ TIMEOUT - LSE_
VALUE - LSI_
VALUE - NVIC
- NVIC_
BASE - OB
- OB_BASE
- OB_
BOOT1_ SRAM - OB_
BOOT1_ SYSTEM - OB_
BOR_ DISABLE - OB_
BOR_ ENABLE - OB_
BOR_ LEVEL_ 1p7_ 1p8 - OB_
BOR_ LEVEL_ 1p9_ 2p0 - OB_
BOR_ LEVEL_ 2p1_ 2p2 - OB_
BOR_ LEVEL_ 2p3_ 2p4 - OB_
BOR_ LEVEL_ 2p5_ 2p6 - OB_
BOR_ LEVEL_ 2p7_ 2p8 - OB_
BOR_ LEVEL_ 2p9_ 3p0 - OB_
BOR_ LEVEL_ 3p1_ 3p2 - OB_
IWDG_ HW - OB_
IWDG_ SW - OB_
RDP_ LEVEL_ 0 - OB_
RDP_ LEVEL_ 1 - OB_
RESET_ MODE_ GPIO - OB_
RESET_ MODE_ RESET - OB_
USER_ ALL - OB_
USER_ BOR_ EN - OB_
USER_ BOR_ LEV - OB_
USER_ IWDG_ SW - OB_
USER_ NRST_ MODE - OB_
USER_ WWDG_ SW - OB_
USER_ nBOO T1 - OB_
WRPSTATE_ DISABLE - OB_
WRPSTATE_ ENABLE - OB_
WRP_ AllPages - OB_
WRP_ Pages0to31 - OB_
WRP_ Pages32to63 - OB_
WRP_ Pages64to95 - OB_
WRP_ Pages96to127 - OB_
WRP_ Pages128to159 - OB_
WRP_ Pages160to191 - OB_
WRP_ Pages192to223 - OB_
WRP_ Pages224to255 - OB_
WRP_ Pages256to287 - OB_
WRP_ Pages288to319 - OB_
WRP_ Pages320to351 - OB_
WRP_ Pages352to383 - OB_
WRP_ Pages384to415 - OB_
WRP_ Pages416to447 - OB_
WRP_ Pages448to479 - OB_
WRP_ Pages480to511 - OB_
WRP_ SECTOR_ 0 - OB_
WRP_ SECTOR_ 1 - OB_
WRP_ SECTOR_ 2 - OB_
WRP_ SECTOR_ 3 - OB_
WRP_ SECTOR_ 4 - OB_
WRP_ SECTOR_ 5 - OB_
WRP_ SECTOR_ 6 - OB_
WRP_ SECTOR_ 7 - OB_
WRP_ SECTOR_ 8 - OB_
WRP_ SECTOR_ 9 - OB_
WRP_ SECTOR_ 10 - OB_
WRP_ SECTOR_ 11 - OB_
WRP_ SECTOR_ 12 - OB_
WRP_ SECTOR_ 13 - OB_
WRP_ SECTOR_ 14 - OB_
WRP_ SECTOR_ 15 - OB_
WWDG_ HW - OB_
WWDG_ SW - OPTIONBYTE_
ALL - OPTIONBYTE_
RDP - OPTIONBYTE_
SDK - OPTIONBYTE_
USER - OPTIONBYTE_
WRP - PERIPH_
BASE - PREFETCH_
ENABLE - PRIORITY_
HIGH - PRIORITY_
HIGHEST - PRIORITY_
LOW - PRIORITY_
LOWEST - PWR
- PWR_
BASE - PWR_
BIAS_ CURRENTS_ FROM_ BIAS_ CR - PWR_
BIAS_ CURRENTS_ FROM_ FACTORY_ BYTES - PWR_
CR1_ BIAS_ CR - PWR_
CR1_ BIAS_ CR_ 0 - PWR_
CR1_ BIAS_ CR_ 1 - PWR_
CR1_ BIAS_ CR_ 2 - PWR_
CR1_ BIAS_ CR_ 3 - PWR_
CR1_ BIAS_ CR_ Msk - PWR_
CR1_ BIAS_ CR_ Pos - PWR_
CR1_ BIAS_ CR_ SEL - PWR_
CR1_ BIAS_ CR_ SEL_ Msk - PWR_
CR1_ BIAS_ CR_ SEL_ Pos - PWR_
CR1_ DBP - PWR_
CR1_ DBP_ Msk - PWR_
CR1_ DBP_ Pos - PWR_
CR1_ FLS_ SLPTIME - PWR_
CR1_ FLS_ SLPTIME_ 0 - PWR_
CR1_ FLS_ SLPTIME_ 1 - PWR_
CR1_ FLS_ SLPTIME_ Msk - PWR_
CR1_ FLS_ SLPTIME_ Pos - PWR_
CR1_ HSION_ CTRL - PWR_
CR1_ HSION_ CTRL_ Msk - PWR_
CR1_ HSION_ CTRL_ Pos - PWR_
CR1_ LPR - PWR_
CR1_ LPR_ Msk - PWR_
CR1_ LPR_ Pos - PWR_
CR1_ MRRDY_ TIME - PWR_
CR1_ MRRDY_ TIME_ 0 - PWR_
CR1_ MRRDY_ TIME_ 1 - PWR_
CR1_ MRRDY_ TIME_ Msk - PWR_
CR1_ MRRDY_ TIME_ Pos - PWR_
CR1_ SRAM_ RETV - PWR_
CR1_ SRAM_ RETV_ 0 - PWR_
CR1_ SRAM_ RETV_ 1 - PWR_
CR1_ SRAM_ RETV_ 2 - PWR_
CR1_ SRAM_ RETV_ Msk - PWR_
CR1_ SRAM_ RETV_ Pos - PWR_
CR1_ VOS - PWR_
CR1_ VOS_ Msk - PWR_
CR1_ VOS_ Pos - PWR_
CR2_ FLTEN - PWR_
CR2_ FLTEN_ Msk - PWR_
CR2_ FLTEN_ Pos - PWR_
CR2_ FLT_ TIME - PWR_
CR2_ FLT_ TIME_ 0 - PWR_
CR2_ FLT_ TIME_ 1 - PWR_
CR2_ FLT_ TIME_ 2 - PWR_
CR2_ FLT_ TIME_ Msk - PWR_
CR2_ FLT_ TIME_ Pos - PWR_
CR2_ PVDE - PWR_
CR2_ PVDE_ Msk - PWR_
CR2_ PVDE_ Pos - PWR_
CR2_ PVDT - PWR_
CR2_ PVDT_ 0 - PWR_
CR2_ PVDT_ 1 - PWR_
CR2_ PVDT_ 2 - PWR_
CR2_ PVDT_ Msk - PWR_
CR2_ PVDT_ Pos - PWR_
CR2_ SRCSEL - PWR_
CR2_ SRCSEL_ Msk - PWR_
CR2_ SRCSEL_ Pos - PWR_
EVENT_ LINE_ PVD - PWR_
EXTI_ LINE_ PVD - PWR_
FLAG_ PVDO - PWR_
LOWPOWERREGULATOR_ ON - PWR_
MAINREGULATOR_ ON - PWR_
PVDLEVEL_ 0 - PWR_
PVDLEVEL_ 1 - PWR_
PVDLEVEL_ 2 - PWR_
PVDLEVEL_ 3 - PWR_
PVDLEVEL_ 4 - PWR_
PVDLEVEL_ 5 - PWR_
PVDLEVEL_ 6 - PWR_
PVDLEVEL_ 7 - PWR_
PVD_ FILTER_ 1CLOCK - PWR_
PVD_ FILTER_ 2CLOCK - PWR_
PVD_ FILTER_ 4CLOCK - PWR_
PVD_ FILTER_ 16CLOCK - PWR_
PVD_ FILTER_ 64CLOCK - PWR_
PVD_ FILTER_ 128CLOCK - PWR_
PVD_ FILTER_ 1024CLOCK - PWR_
PVD_ FILTER_ NONE - PWR_
PVD_ MODE_ EVENT_ FALLING - PWR_
PVD_ MODE_ EVENT_ RISING - PWR_
PVD_ MODE_ EVENT_ RISING_ FALLING - PWR_
PVD_ MODE_ IT_ FALLING - PWR_
PVD_ MODE_ IT_ RISING - PWR_
PVD_ MODE_ IT_ RISING_ FALLING - PWR_
PVD_ MODE_ NORMAL - PWR_
PVD_ SOURCE_ PB07 - PWR_
PVD_ SOURCE_ VCC - PWR_
SLEEPENTRY_ WFE - PWR_
SLEEPENTRY_ WFI - PWR_
SRAM_ RETENTION_ VOLT_ 0p9 - PWR_
SRAM_ RETENTION_ VOLT_ VOS - PWR_
SR_ PVDO - PWR_
SR_ PVDO_ Msk - PWR_
SR_ PVDO_ Pos - PWR_
STOPENTRY_ WFE - PWR_
STOPENTRY_ WFI - PWR_
STOPMOD_ LPR_ VOLT_ SCAL E1 - PWR_
STOPMOD_ LPR_ VOLT_ SCAL E2 - PWR_
WAKEUP_ FLASH_ DELAY_ 0US - PWR_
WAKEUP_ FLASH_ DELAY_ 2US - PWR_
WAKEUP_ FLASH_ DELAY_ 3US - PWR_
WAKEUP_ FLASH_ DELAY_ 5US - PWR_
WAKEUP_ HSIEN_ AFTER_ MR - PWR_
WAKEUP_ HSIEN_ IMMEDIATE - PWR_
WAKEUP_ LPR_ TO_ MR_ DELAY_ 2US - PWR_
WAKEUP_ LPR_ TO_ MR_ DELAY_ 3US - PWR_
WAKEUP_ LPR_ TO_ MR_ DELAY_ 4US - PWR_
WAKEUP_ LPR_ TO_ MR_ DELAY_ 5US - PWR_
WUP_ POLARITY_ SHIFT - RCC
- RCC_
AHBENR_ CRCEN - RCC_
AHBENR_ CRCEN_ Msk - RCC_
AHBENR_ CRCEN_ Pos - RCC_
AHBENR_ DMAEN - RCC_
AHBENR_ DMAEN_ Msk - RCC_
AHBENR_ DMAEN_ Pos - RCC_
AHBENR_ FLASHEN - RCC_
AHBENR_ FLASHEN_ Msk - RCC_
AHBENR_ FLASHEN_ Pos - RCC_
AHBENR_ SRAMEN - RCC_
AHBENR_ SRAMEN_ Msk - RCC_
AHBENR_ SRAMEN_ Pos - RCC_
AHBRSTR_ CRCRST - RCC_
AHBRSTR_ CRCRST_ Msk - RCC_
AHBRSTR_ CRCRST_ Pos - RCC_
AHBRSTR_ DMARST - RCC_
AHBRSTR_ DMARST_ Msk - RCC_
AHBRSTR_ DMARST_ Pos - RCC_
APBEN R1_ DBGEN - RCC_
APBEN R1_ DBGEN_ Msk - RCC_
APBEN R1_ DBGEN_ Pos - RCC_
APBEN R1_ I2CEN - RCC_
APBEN R1_ I2CEN_ Msk - RCC_
APBEN R1_ I2CEN_ Pos - RCC_
APBEN R1_ LPTIMEN - RCC_
APBEN R1_ LPTIMEN_ Msk - RCC_
APBEN R1_ LPTIMEN_ Pos - RCC_
APBEN R1_ PWREN - RCC_
APBEN R1_ PWREN_ Msk - RCC_
APBEN R1_ PWREN_ Pos - RCC_
APBEN R1_ RTCAPBEN - RCC_
APBEN R1_ RTCAPBEN_ Msk - RCC_
APBEN R1_ RTCAPBEN_ Pos - RCC_
APBEN R1_ SPI2EN - RCC_
APBEN R1_ SPI2EN_ Msk - RCC_
APBEN R1_ SPI2EN_ Pos - RCC_
APBEN R1_ TIM3EN - RCC_
APBEN R1_ TIM3EN_ Msk - RCC_
APBEN R1_ TIM3EN_ Pos - RCC_
APBEN R1_ USAR T2EN - RCC_
APBEN R1_ USAR T2EN_ Msk - RCC_
APBEN R1_ USAR T2EN_ Pos - RCC_
APBEN R1_ WWDGEN - RCC_
APBEN R1_ WWDGEN_ Msk - RCC_
APBEN R1_ WWDGEN_ Pos - RCC_
APBEN R2_ ADCEN - RCC_
APBEN R2_ ADCEN_ Msk - RCC_
APBEN R2_ ADCEN_ Pos - RCC_
APBEN R2_ COMP1EN - RCC_
APBEN R2_ COMP1EN_ Msk - RCC_
APBEN R2_ COMP1EN_ Pos - RCC_
APBEN R2_ COMP2EN - RCC_
APBEN R2_ COMP2EN_ Msk - RCC_
APBEN R2_ COMP2EN_ Pos - RCC_
APBEN R2_ LEDEN - RCC_
APBEN R2_ LEDEN_ Msk - RCC_
APBEN R2_ LEDEN_ Pos - RCC_
APBEN R2_ SPI1EN - RCC_
APBEN R2_ SPI1EN_ Msk - RCC_
APBEN R2_ SPI1EN_ Pos - RCC_
APBEN R2_ SYSCFGEN - RCC_
APBEN R2_ SYSCFGEN_ Msk - RCC_
APBEN R2_ SYSCFGEN_ Pos - RCC_
APBEN R2_ TIM1EN - RCC_
APBEN R2_ TIM1EN_ Msk - RCC_
APBEN R2_ TIM1EN_ Pos - RCC_
APBEN R2_ TIM14EN - RCC_
APBEN R2_ TIM14EN_ Msk - RCC_
APBEN R2_ TIM14EN_ Pos - RCC_
APBEN R2_ TIM16EN - RCC_
APBEN R2_ TIM16EN_ Msk - RCC_
APBEN R2_ TIM16EN_ Pos - RCC_
APBEN R2_ TIM17EN - RCC_
APBEN R2_ TIM17EN_ Msk - RCC_
APBEN R2_ TIM17EN_ Pos - RCC_
APBEN R2_ USAR T1EN - RCC_
APBEN R2_ USAR T1EN_ Msk - RCC_
APBEN R2_ USAR T1EN_ Pos - RCC_
APBRST R1_ DBGRST - RCC_
APBRST R1_ DBGRST_ Msk - RCC_
APBRST R1_ DBGRST_ Pos - RCC_
APBRST R1_ I2CRST - RCC_
APBRST R1_ I2CRST_ Msk - RCC_
APBRST R1_ I2CRST_ Pos - RCC_
APBRST R1_ LPTIMRST - RCC_
APBRST R1_ LPTIMRST_ Msk - RCC_
APBRST R1_ LPTIMRST_ Pos - RCC_
APBRST R1_ PWRRST - RCC_
APBRST R1_ PWRRST_ Msk - RCC_
APBRST R1_ PWRRST_ Pos - RCC_
APBRST R1_ SPI2RST - RCC_
APBRST R1_ SPI2RST_ Msk - RCC_
APBRST R1_ SPI2RST_ Pos - RCC_
APBRST R1_ TIM3RST - RCC_
APBRST R1_ TIM3RST_ Msk - RCC_
APBRST R1_ TIM3RST_ Pos - RCC_
APBRST R1_ USAR T2RST - RCC_
APBRST R1_ USAR T2RST_ Msk - RCC_
APBRST R1_ USAR T2RST_ Pos - RCC_
APBRST R2_ ADCRST - RCC_
APBRST R2_ ADCRST_ Msk - RCC_
APBRST R2_ ADCRST_ Pos - RCC_
APBRST R2_ COMP1RST - RCC_
APBRST R2_ COMP1RST_ Msk - RCC_
APBRST R2_ COMP1RST_ Pos - RCC_
APBRST R2_ COMP2RST - RCC_
APBRST R2_ COMP2RST_ Msk - RCC_
APBRST R2_ COMP2RST_ Pos - RCC_
APBRST R2_ LEDRST - RCC_
APBRST R2_ LEDRST_ Msk - RCC_
APBRST R2_ LEDRST_ Pos - RCC_
APBRST R2_ SPI1RST - RCC_
APBRST R2_ SPI1RST_ Msk - RCC_
APBRST R2_ SPI1RST_ Pos - RCC_
APBRST R2_ SYSCFGRST - RCC_
APBRST R2_ SYSCFGRST_ Msk - RCC_
APBRST R2_ SYSCFGRST_ Pos - RCC_
APBRST R2_ TIM1RST - RCC_
APBRST R2_ TIM1RST_ Msk - RCC_
APBRST R2_ TIM1RST_ Pos - RCC_
APBRST R2_ TIM14RST - RCC_
APBRST R2_ TIM14RST_ Msk - RCC_
APBRST R2_ TIM14RST_ Pos - RCC_
APBRST R2_ TIM16RST - RCC_
APBRST R2_ TIM16RST_ Msk - RCC_
APBRST R2_ TIM16RST_ Pos - RCC_
APBRST R2_ TIM17RST - RCC_
APBRST R2_ TIM17RST_ Msk - RCC_
APBRST R2_ TIM17RST_ Pos - RCC_
APBRST R2_ USAR T1RST - RCC_
APBRST R2_ USAR T1RST_ Msk - RCC_
APBRST R2_ USAR T1RST_ Pos - RCC_
BASE - RCC_
BDCR_ BDRST - RCC_
BDCR_ BDRST_ Msk - RCC_
BDCR_ BDRST_ Pos - RCC_
BDCR_ LSCOEN - RCC_
BDCR_ LSCOEN_ Msk - RCC_
BDCR_ LSCOEN_ Pos - RCC_
BDCR_ LSCOSEL - RCC_
BDCR_ LSCOSEL_ Msk - RCC_
BDCR_ LSCOSEL_ Pos - RCC_
BDCR_ LSEBYP - RCC_
BDCR_ LSEBYP_ Msk - RCC_
BDCR_ LSEBYP_ Pos - RCC_
BDCR_ LSECSSD - RCC_
BDCR_ LSECSSD_ Msk - RCC_
BDCR_ LSECSSD_ Pos - RCC_
BDCR_ LSECSSON - RCC_
BDCR_ LSECSSON_ Msk - RCC_
BDCR_ LSECSSON_ Pos - RCC_
BDCR_ LSEON - RCC_
BDCR_ LSEON_ Msk - RCC_
BDCR_ LSEON_ Pos - RCC_
BDCR_ LSERDY - RCC_
BDCR_ LSERDY_ Msk - RCC_
BDCR_ LSERDY_ Pos - RCC_
BDCR_ RTCEN - RCC_
BDCR_ RTCEN_ Msk - RCC_
BDCR_ RTCEN_ Pos - RCC_
BDCR_ RTCSEL - RCC_
BDCR_ RTCSEL_ 0 - RCC_
BDCR_ RTCSEL_ 1 - RCC_
BDCR_ RTCSEL_ Msk - RCC_
BDCR_ RTCSEL_ Pos - RCC_
CCIPR_ COMP1SEL - RCC_
CCIPR_ COMP1SEL_ Msk - RCC_
CCIPR_ COMP1SEL_ Pos - RCC_
CCIPR_ COMP2SEL - RCC_
CCIPR_ COMP2SEL_ Msk - RCC_
CCIPR_ COMP2SEL_ Pos - RCC_
CCIPR_ LPTIMSEL - RCC_
CCIPR_ LPTIMSEL_ 0 - RCC_
CCIPR_ LPTIMSEL_ 1 - RCC_
CCIPR_ LPTIMSEL_ Msk - RCC_
CCIPR_ LPTIMSEL_ Pos - RCC_
CCIPR_ PVDSEL - RCC_
CCIPR_ PVDSEL_ Msk - RCC_
CCIPR_ PVDSEL_ Pos - RCC_
CFGR_ HPRE - RCC_
CFGR_ HPRE_ 0 - RCC_
CFGR_ HPRE_ 1 - RCC_
CFGR_ HPRE_ 2 - RCC_
CFGR_ HPRE_ 3 - RCC_
CFGR_ HPRE_ Msk - RCC_
CFGR_ HPRE_ Pos - RCC_
CFGR_ MCOPRE - RCC_
CFGR_ MCOPRE_ 0 - RCC_
CFGR_ MCOPRE_ 1 - RCC_
CFGR_ MCOPRE_ 2 - RCC_
CFGR_ MCOPRE_ Msk - RCC_
CFGR_ MCOPRE_ Pos - RCC_
CFGR_ MCOSEL - RCC_
CFGR_ MCOSEL_ 0 - RCC_
CFGR_ MCOSEL_ 1 - RCC_
CFGR_ MCOSEL_ 2 - RCC_
CFGR_ MCOSEL_ Msk - RCC_
CFGR_ MCOSEL_ Pos - RCC_
CFGR_ PPRE - RCC_
CFGR_ PPRE_ 0 - RCC_
CFGR_ PPRE_ 1 - RCC_
CFGR_ PPRE_ 2 - RCC_
CFGR_ PPRE_ Msk - RCC_
CFGR_ PPRE_ Pos - RCC_
CFGR_ SW - RCC_
CFGR_ SWS - RCC_
CFGR_ SWS_ 0 - RCC_
CFGR_ SWS_ 1 - RCC_
CFGR_ SWS_ 2 - RCC_
CFGR_ SWS_ HSE - RCC_
CFGR_ SWS_ HSI - RCC_
CFGR_ SWS_ LSE - RCC_
CFGR_ SWS_ LSI - RCC_
CFGR_ SWS_ Msk - RCC_
CFGR_ SWS_ PLL - RCC_
CFGR_ SWS_ Pos - RCC_
CFGR_ SW_ 0 - RCC_
CFGR_ SW_ 1 - RCC_
CFGR_ SW_ 2 - RCC_
CFGR_ SW_ Msk - RCC_
CFGR_ SW_ Pos - RCC_
CICR_ CSSC - RCC_
CICR_ CSSC_ Msk - RCC_
CICR_ CSSC_ Pos - RCC_
CICR_ HSERDYC - RCC_
CICR_ HSERDYC_ Msk - RCC_
CICR_ HSERDYC_ Pos - RCC_
CICR_ HSIRDYC - RCC_
CICR_ HSIRDYC_ Msk - RCC_
CICR_ HSIRDYC_ Pos - RCC_
CICR_ LSECSSC - RCC_
CICR_ LSECSSC_ Msk - RCC_
CICR_ LSECSSC_ Pos - RCC_
CICR_ LSERDYC - RCC_
CICR_ LSERDYC_ Msk - RCC_
CICR_ LSERDYC_ Pos - RCC_
CICR_ LSIRDYC - RCC_
CICR_ LSIRDYC_ Msk - RCC_
CICR_ LSIRDYC_ Pos - RCC_
CICR_ PLLRDYC - RCC_
CICR_ PLLRDYC_ Msk - RCC_
CICR_ PLLRDYC_ Pos - RCC_
CIER_ HSERDYIE - RCC_
CIER_ HSERDYIE_ Msk - RCC_
CIER_ HSERDYIE_ Pos - RCC_
CIER_ HSIRDYIE - RCC_
CIER_ HSIRDYIE_ Msk - RCC_
CIER_ HSIRDYIE_ Pos - RCC_
CIER_ LSERDYIE - RCC_
CIER_ LSERDYIE_ Msk - RCC_
CIER_ LSERDYIE_ Pos - RCC_
CIER_ LSIRDYIE - RCC_
CIER_ LSIRDYIE_ Msk - RCC_
CIER_ LSIRDYIE_ Pos - RCC_
CIER_ PLLRDYIE - RCC_
CIER_ PLLRDYIE_ Msk - RCC_
CIER_ PLLRDYIE_ Pos - RCC_
CIFR_ CSSF - RCC_
CIFR_ CSSF_ Msk - RCC_
CIFR_ CSSF_ Pos - RCC_
CIFR_ HSERDYF - RCC_
CIFR_ HSERDYF_ Msk - RCC_
CIFR_ HSERDYF_ Pos - RCC_
CIFR_ HSIRDYF - RCC_
CIFR_ HSIRDYF_ Msk - RCC_
CIFR_ HSIRDYF_ Pos - RCC_
CIFR_ LSECSSF - RCC_
CIFR_ LSECSSF_ Msk - RCC_
CIFR_ LSECSSF_ Pos - RCC_
CIFR_ LSERDYF - RCC_
CIFR_ LSERDYF_ Msk - RCC_
CIFR_ LSERDYF_ Pos - RCC_
CIFR_ LSIRDYF - RCC_
CIFR_ LSIRDYF_ Msk - RCC_
CIFR_ LSIRDYF_ Pos - RCC_
CIFR_ PLLRDYF - RCC_
CIFR_ PLLRDYF_ Msk - RCC_
CIFR_ PLLRDYF_ Pos - RCC_
CLOCKTYPE_ ALL - RCC_
CLOCKTYPE_ HCLK - RCC_
CLOCKTYPE_ PCLK1 - RCC_
CLOCKTYPE_ SYSCLK - RCC_
COMP1CLKSOURCE_ LSC - RCC_
COMP1CLKSOURCE_ PCLK - RCC_
COMP2CLKSOURCE_ LSC - RCC_
COMP2CLKSOURCE_ PCLK - RCC_
CR_ CSSON - RCC_
CR_ CSSON_ Msk - RCC_
CR_ CSSON_ Pos - RCC_
CR_ HSEBYP - RCC_
CR_ HSEBYP_ Msk - RCC_
CR_ HSEBYP_ Pos - RCC_
CR_ HSEON - RCC_
CR_ HSEON_ Msk - RCC_
CR_ HSEON_ Pos - RCC_
CR_ HSERDY - RCC_
CR_ HSERDY_ Msk - RCC_
CR_ HSERDY_ Pos - RCC_
CR_ HSIDIV - RCC_
CR_ HSIDIV_ 0 - RCC_
CR_ HSIDIV_ 1 - RCC_
CR_ HSIDIV_ 2 - RCC_
CR_ HSIDIV_ Msk - RCC_
CR_ HSIDIV_ Pos - RCC_
CR_ HSION - RCC_
CR_ HSION_ Msk - RCC_
CR_ HSION_ Pos - RCC_
CR_ HSIRDY - RCC_
CR_ HSIRDY_ Msk - RCC_
CR_ HSIRDY_ Pos - RCC_
CR_ PLLON - RCC_
CR_ PLLON_ Msk - RCC_
CR_ PLLON_ Pos - RCC_
CR_ PLLRDY - RCC_
CR_ PLLRDY_ Msk - RCC_
CR_ PLLRDY_ Pos - RCC_
CSR_ IWDGRSTF - RCC_
CSR_ IWDGRSTF_ Msk - RCC_
CSR_ IWDGRSTF_ Pos - RCC_
CSR_ LSION - RCC_
CSR_ LSION_ Msk - RCC_
CSR_ LSION_ Pos - RCC_
CSR_ LSIRDY - RCC_
CSR_ LSIRDY_ Msk - RCC_
CSR_ LSIRDY_ Pos - RCC_
CSR_ NRST_ FLTDIS - RCC_
CSR_ NRST_ FLTDIS_ Msk - RCC_
CSR_ NRST_ FLTDIS_ Pos - RCC_
CSR_ OBLRSTF - RCC_
CSR_ OBLRSTF_ Msk - RCC_
CSR_ OBLRSTF_ Pos - RCC_
CSR_ PINRSTF - RCC_
CSR_ PINRSTF_ Msk - RCC_
CSR_ PINRSTF_ Pos - RCC_
CSR_ PWRRSTF - RCC_
CSR_ PWRRSTF_ Msk - RCC_
CSR_ PWRRSTF_ Pos - RCC_
CSR_ RMVF - RCC_
CSR_ RMVF_ Msk - RCC_
CSR_ RMVF_ Pos - RCC_
CSR_ SFTRSTF - RCC_
CSR_ SFTRSTF_ Msk - RCC_
CSR_ SFTRSTF_ Pos - RCC_
CSR_ WWDGRSTF - RCC_
CSR_ WWDGRSTF_ Msk - RCC_
CSR_ WWDGRSTF_ Pos - RCC_
DBP_ TIMEOUT_ VALUE - RCC_
ECSCR_ HSE_ FREQ - RCC_
ECSCR_ HSE_ FREQ_ 0 - RCC_
ECSCR_ HSE_ FREQ_ 1 - RCC_
ECSCR_ HSE_ FREQ_ Msk - RCC_
ECSCR_ HSE_ FREQ_ Pos - RCC_
ECSCR_ LSE_ DRIVER - RCC_
ECSCR_ LSE_ DRIVER_ 0 - RCC_
ECSCR_ LSE_ DRIVER_ 1 - RCC_
ECSCR_ LSE_ DRIVER_ Msk - RCC_
ECSCR_ LSE_ DRIVER_ Pos - RCC_
FLAG_ HSERDY - RCC_
FLAG_ HSIRDY - RCC_
FLAG_ IWDGRST - RCC_
FLAG_ LSERDY - RCC_
FLAG_ LSIRDY - RCC_
FLAG_ MASK - RCC_
FLAG_ OBLRST - RCC_
FLAG_ PINRST - RCC_
FLAG_ PLLRDY - RCC_
FLAG_ PWRRST - RCC_
FLAG_ SFTRST - RCC_
FLAG_ WWDGRST - RCC_
HCLK_ DIV1 - RCC_
HCLK_ DIV2 - RCC_
HCLK_ DIV4 - RCC_
HCLK_ DIV8 - RCC_
HCLK_ DIV16 - RCC_
HSE_ 4_ 8MHz - RCC_
HSE_ 8_ 16MHz - RCC_
HSE_ 16_ 32MHz - RCC_
HSE_ BYPASS - RCC_
HSE_ OFF - RCC_
HSE_ ON - RCC_
HSI_ DIV1 - RCC_
HSI_ DIV2 - RCC_
HSI_ DIV4 - RCC_
HSI_ DIV8 - RCC_
HSI_ DIV16 - RCC_
HSI_ DIV32 - RCC_
HSI_ DIV64 - RCC_
HSI_ DIV128 - RCC_
HSI_ OFF - RCC_
HSI_ ON - RCC_
ICSCR_ HSI_ FS - RCC_
ICSCR_ HSI_ FS_ 0 - RCC_
ICSCR_ HSI_ FS_ 1 - RCC_
ICSCR_ HSI_ FS_ 2 - RCC_
ICSCR_ HSI_ FS_ Msk - RCC_
ICSCR_ HSI_ FS_ Pos - RCC_
ICSCR_ HSI_ TRIM - RCC_
ICSCR_ HSI_ TRIM_ 0 - RCC_
ICSCR_ HSI_ TRIM_ 1 - RCC_
ICSCR_ HSI_ TRIM_ 2 - RCC_
ICSCR_ HSI_ TRIM_ 3 - RCC_
ICSCR_ HSI_ TRIM_ 4 - RCC_
ICSCR_ HSI_ TRIM_ 5 - RCC_
ICSCR_ HSI_ TRIM_ 6 - RCC_
ICSCR_ HSI_ TRIM_ 7 - RCC_
ICSCR_ HSI_ TRIM_ 8 - RCC_
ICSCR_ HSI_ TRIM_ 9 - RCC_
ICSCR_ HSI_ TRIM_ 10 - RCC_
ICSCR_ HSI_ TRIM_ 11 - RCC_
ICSCR_ HSI_ TRIM_ 12 - RCC_
ICSCR_ HSI_ TRIM_ Msk - RCC_
ICSCR_ HSI_ TRIM_ Pos - RCC_
ICSCR_ LSI_ STARTUP - RCC_
ICSCR_ LSI_ STARTUP_ 0 - RCC_
ICSCR_ LSI_ STARTUP_ 1 - RCC_
ICSCR_ LSI_ STARTUP_ Msk - RCC_
ICSCR_ LSI_ STARTUP_ Pos - RCC_
ICSCR_ LSI_ TRIM - RCC_
ICSCR_ LSI_ TRIM_ 0 - RCC_
ICSCR_ LSI_ TRIM_ 1 - RCC_
ICSCR_ LSI_ TRIM_ 2 - RCC_
ICSCR_ LSI_ TRIM_ 3 - RCC_
ICSCR_ LSI_ TRIM_ 4 - RCC_
ICSCR_ LSI_ TRIM_ 5 - RCC_
ICSCR_ LSI_ TRIM_ 6 - RCC_
ICSCR_ LSI_ TRIM_ 7 - RCC_
ICSCR_ LSI_ TRIM_ 8 - RCC_
ICSCR_ LSI_ TRIM_ Msk - RCC_
ICSCR_ LSI_ TRIM_ Pos - RCC_
IOPENR_ GPIOAEN - RCC_
IOPENR_ GPIOAEN_ Msk - RCC_
IOPENR_ GPIOAEN_ Pos - RCC_
IOPENR_ GPIOBEN - RCC_
IOPENR_ GPIOBEN_ Msk - RCC_
IOPENR_ GPIOBEN_ Pos - RCC_
IOPENR_ GPIOFEN - RCC_
IOPENR_ GPIOFEN_ Msk - RCC_
IOPENR_ GPIOFEN_ Pos - RCC_
IOPRSTR_ GPIOARST - RCC_
IOPRSTR_ GPIOARST_ Msk - RCC_
IOPRSTR_ GPIOARST_ Pos - RCC_
IOPRSTR_ GPIOBRST - RCC_
IOPRSTR_ GPIOBRST_ Msk - RCC_
IOPRSTR_ GPIOBRST_ Pos - RCC_
IOPRSTR_ GPIOFRST - RCC_
IOPRSTR_ GPIOFRST_ Msk - RCC_
IOPRSTR_ GPIOFRST_ Pos - RCC_
IT_ CSS - RCC_
IT_ HSERDY - RCC_
IT_ HSIRDY - RCC_
IT_ LSECSS - RCC_
IT_ LSERDY - RCC_
IT_ LSIRDY - RCC_
IT_ PLLRDY - RCC_
LPTIMCLKSOURCE_ LSE - RCC_
LPTIMCLKSOURCE_ LSI - RCC_
LPTIMCLKSOURCE_ PCLK - RCC_
LSCOSOURCE_ LSE - RCC_
LSCOSOURCE_ LSI - RCC_
LSEDRIVE_ HIGH - RCC_
LSEDRIVE_ LOW - RCC_
LSEDRIVE_ MEDIUM - RCC_
LSE_ BYPASS - RCC_
LSE_ OFF - RCC_
LSE_ ON - RCC_
LSE_ TIMEOUT_ VALUE - RCC_
LSI_ OFF - RCC_
LSI_ ON - RCC_MCO
- RCC_
MCO1 - RCC_
MCO2 - RCC_
MCO3 - RCC_
MCO4 - RCC_
MCO5 - RCC_
MCO6 - RCC_
MCO7 - RCC_
MCO1SOURCE_ HSE - RCC_
MCO1SOURCE_ HSI - RCC_
MCO1SOURCE_ HSI10M - RCC_
MCO1SOURCE_ LSE - RCC_
MCO1SOURCE_ LSI - RCC_
MCO1SOURCE_ NOCLOCK - RCC_
MCO1SOURCE_ PLLCLK - RCC_
MCO1SOURCE_ SYSCLK - RCC_
MCODIV_ 1 - RCC_
MCODIV_ 2 - RCC_
MCODIV_ 4 - RCC_
MCODIV_ 8 - RCC_
MCODIV_ 16 - RCC_
MCODIV_ 32 - RCC_
MCODIV_ 64 - RCC_
MCODIV_ 128 - RCC_
OSCILLATORTYPE_ HSE - RCC_
OSCILLATORTYPE_ HSI - RCC_
OSCILLATORTYPE_ LSE - RCC_
OSCILLATORTYPE_ LSI - RCC_
OSCILLATORTYPE_ NONE - RCC_
PERIPHCLK_ COMP1 - RCC_
PERIPHCLK_ COMP2 - RCC_
PERIPHCLK_ LPTIM - RCC_
PERIPHCLK_ PVD - RCC_
PERIPHCLK_ RTC - RCC_
PLLCFGR_ PLLSRC - RCC_
PLLCFGR_ PLLSRC_ HSE - RCC_
PLLCFGR_ PLLSRC_ HSE_ Msk - RCC_
PLLCFGR_ PLLSRC_ HSE_ Pos - RCC_
PLLCFGR_ PLLSRC_ HSI - RCC_
PLLCFGR_ PLLSRC_ HSI_ Msk - RCC_
PLLCFGR_ PLLSRC_ HSI_ Pos - RCC_
PLLCFGR_ PLLSRC_ Msk - RCC_
PLLCFGR_ PLLSRC_ NONE - RCC_
PLLCFGR_ PLLSRC_ Pos - RCC_
PLLSOURCE_ HSE - RCC_
PLLSOURCE_ HSI - RCC_
PLLSOURCE_ NONE - RCC_
PLL_ NONE - RCC_
PLL_ OFF - RCC_
PLL_ ON - RCC_
PVDCLKSOURCE_ LSC - RCC_
PVDCLKSOURCE_ PCLK - RCC_
RTCCLKSOURCE_ HSE_ DIV128 - RCC_
RTCCLKSOURCE_ LSE - RCC_
RTCCLKSOURCE_ LSI - RCC_
RTCCLKSOURCE_ NONE - RCC_
SYSCLKSOURCE_ HSE - RCC_
SYSCLKSOURCE_ HSI - RCC_
SYSCLKSOURCE_ LSE - RCC_
SYSCLKSOURCE_ LSI - RCC_
SYSCLKSOURCE_ PLLCLK - RCC_
SYSCLKSOURCE_ STATUS_ HSE - RCC_
SYSCLKSOURCE_ STATUS_ HSI - RCC_
SYSCLKSOURCE_ STATUS_ LSE - RCC_
SYSCLKSOURCE_ STATUS_ LSI - RCC_
SYSCLKSOURCE_ STATUS_ PLLCLK - RCC_
SYSCLK_ DIV1 - RCC_
SYSCLK_ DIV2 - RCC_
SYSCLK_ DIV4 - RCC_
SYSCLK_ DIV8 - RCC_
SYSCLK_ DIV16 - RCC_
SYSCLK_ DIV64 - RCC_
SYSCLK_ DIV128 - RCC_
SYSCLK_ DIV256 - RCC_
SYSCLK_ DIV512 - RTC
- RTC_
ALARM_ A - RTC_
ALRH_ RTC_ ALR - RTC_
ALRH_ RTC_ ALR_ Msk - RTC_
ALRH_ RTC_ ALR_ Pos - RTC_
ALRL_ RTC_ ALR - RTC_
ALRL_ RTC_ ALR_ Msk - RTC_
ALRL_ RTC_ ALR_ Pos - RTC_
AUTO_ 1_ SECOND - RTC_
BASE - RTC_
CNTH_ RTC_ CNT - RTC_
CNTH_ RTC_ CNT_ Msk - RTC_
CNTH_ RTC_ CNT_ Pos - RTC_
CNTL_ RTC_ CNT - RTC_
CNTL_ RTC_ CNT_ Msk - RTC_
CNTL_ RTC_ CNT_ Pos - RTC_
CRH_ ALRIE - RTC_
CRH_ ALRIE_ Msk - RTC_
CRH_ ALRIE_ Pos - RTC_
CRH_ OWIE - RTC_
CRH_ OWIE_ Msk - RTC_
CRH_ OWIE_ Pos - RTC_
CRH_ SECIE - RTC_
CRH_ SECIE_ Msk - RTC_
CRH_ SECIE_ Pos - RTC_
CRL_ ALRF - RTC_
CRL_ ALRF_ Msk - RTC_
CRL_ ALRF_ Pos - RTC_
CRL_ CNF - RTC_
CRL_ CNF_ Msk - RTC_
CRL_ CNF_ Pos - RTC_
CRL_ OWF - RTC_
CRL_ OWF_ Msk - RTC_
CRL_ OWF_ Pos - RTC_
CRL_ RSF - RTC_
CRL_ RSF_ Msk - RTC_
CRL_ RSF_ Pos - RTC_
CRL_ RTOFF - RTC_
CRL_ RTOFF_ Msk - RTC_
CRL_ RTOFF_ Pos - RTC_
CRL_ SECF - RTC_
CRL_ SECF_ Msk - RTC_
CRL_ SECF_ Pos - RTC_
DIVH_ RTC_ DIV - RTC_
DIVH_ RTC_ DIV_ Msk - RTC_
DIVH_ RTC_ DIV_ Pos - RTC_
DIVL_ RTC_ DIV - RTC_
DIVL_ RTC_ DIV_ Msk - RTC_
DIVL_ RTC_ DIV_ Pos - RTC_
EXTI_ LINE_ ALARM_ EVENT - RTC_
FLAG_ ALRAF - RTC_
FLAG_ OW - RTC_
FLAG_ RSF - RTC_
FLAG_ RTOFF - RTC_
FLAG_ SEC - RTC_
FORMAT_ BCD - RTC_
FORMAT_ BIN - RTC_
IT_ ALRA - RTC_
IT_ OW - RTC_
IT_ SEC - RTC_
MONTH_ APRIL - RTC_
MONTH_ AUGUST - RTC_
MONTH_ DECEMBER - RTC_
MONTH_ FEBRUARY - RTC_
MONTH_ JANUARY - RTC_
MONTH_ JULY - RTC_
MONTH_ JUNE - RTC_
MONTH_ MARCH - RTC_
MONTH_ MAY - RTC_
MONTH_ NOVEMBER - RTC_
MONTH_ OCTOBER - RTC_
MONTH_ SEPTEMBER - RTC_
OUTPUTSOURCE_ ALARM - RTC_
OUTPUTSOURCE_ CALIBCLOCK - RTC_
OUTPUTSOURCE_ NONE - RTC_
OUTPUTSOURCE_ SECOND - RTC_
PRLH_ PRL - RTC_
PRLH_ PRL_ Msk - RTC_
PRLH_ PRL_ Pos - RTC_
PRLL_ PRL - RTC_
PRLL_ PRL_ Msk - RTC_
PRLL_ PRL_ Pos - RTC_
RTOFF_ RESET_ TIMEOUT_ VALUE - RTC_
TIMEOUT_ VALUE - RTC_
WEEKDAY_ FRIDAY - RTC_
WEEKDAY_ MONDAY - RTC_
WEEKDAY_ SATURDAY - RTC_
WEEKDAY_ SUNDAY - RTC_
WEEKDAY_ THURSDAY - RTC_
WEEKDAY_ TUESDAY - RTC_
WEEKDAY_ WEDNESDAY - SCB
- SCB_
AIRCR_ ENDIANESS_ Msk - SCB_
AIRCR_ ENDIANESS_ Pos - SCB_
AIRCR_ SYSRESETREQ_ Msk - SCB_
AIRCR_ SYSRESETREQ_ Pos - SCB_
AIRCR_ VECTCLRACTIVE_ Msk - SCB_
AIRCR_ VECTCLRACTIVE_ Pos - SCB_
AIRCR_ VECTKEYSTAT_ Msk - SCB_
AIRCR_ VECTKEYSTAT_ Pos - SCB_
AIRCR_ VECTKEY_ Msk - SCB_
AIRCR_ VECTKEY_ Pos - SCB_
BASE - SCB_
CCR_ STKALIGN_ Msk - SCB_
CCR_ STKALIGN_ Pos - SCB_
CCR_ UNALIGN_ TRP_ Msk - SCB_
CCR_ UNALIGN_ TRP_ Pos - SCB_
CPUID_ ARCHITECTURE_ Msk - SCB_
CPUID_ ARCHITECTURE_ Pos - SCB_
CPUID_ IMPLEMENTER_ Msk - SCB_
CPUID_ IMPLEMENTER_ Pos - SCB_
CPUID_ PARTNO_ Msk - SCB_
CPUID_ PARTNO_ Pos - SCB_
CPUID_ REVISION_ Msk - SCB_
CPUID_ REVISION_ Pos - SCB_
CPUID_ VARIANT_ Msk - SCB_
CPUID_ VARIANT_ Pos - SCB_
ICSR_ ISRPENDING_ Msk - SCB_
ICSR_ ISRPENDING_ Pos - SCB_
ICSR_ ISRPREEMPT_ Msk - SCB_
ICSR_ ISRPREEMPT_ Pos - SCB_
ICSR_ NMIPENDSET_ Msk - SCB_
ICSR_ NMIPENDSET_ Pos - SCB_
ICSR_ PENDSTCLR_ Msk - SCB_
ICSR_ PENDSTCLR_ Pos - SCB_
ICSR_ PENDSTSET_ Msk - SCB_
ICSR_ PENDSTSET_ Pos - SCB_
ICSR_ PENDSVCLR_ Msk - SCB_
ICSR_ PENDSVCLR_ Pos - SCB_
ICSR_ PENDSVSET_ Msk - SCB_
ICSR_ PENDSVSET_ Pos - SCB_
ICSR_ VECTACTIVE_ Msk - SCB_
ICSR_ VECTACTIVE_ Pos - SCB_
ICSR_ VECTPENDING_ Msk - SCB_
ICSR_ VECTPENDING_ Pos - SCB_
SCR_ SEVONPEND_ Msk - SCB_
SCR_ SEVONPEND_ Pos - SCB_
SCR_ SLEEPDEEP_ Msk - SCB_
SCR_ SLEEPDEEP_ Pos - SCB_
SCR_ SLEEPONEXIT_ Msk - SCB_
SCR_ SLEEPONEXIT_ Pos - SCB_
SHCSR_ SVCALLPENDED_ Msk - SCB_
SHCSR_ SVCALLPENDED_ Pos - SCB_
VTOR_ TBLOFF_ Msk - SCB_
VTOR_ TBLOFF_ Pos - SCS_
BASE - SPI1
- SPI2
- SPI1_
BASE - SPI2_
BASE - SPI_
BAUDRATEPRESCALER_ 2 - SPI_
BAUDRATEPRESCALER_ 4 - SPI_
BAUDRATEPRESCALER_ 8 - SPI_
BAUDRATEPRESCALER_ 16 - SPI_
BAUDRATEPRESCALER_ 32 - SPI_
BAUDRATEPRESCALER_ 64 - SPI_
BAUDRATEPRESCALER_ 128 - SPI_
BAUDRATEPRESCALER_ 256 - SPI_
CR1_ BIDIMODE - SPI_
CR1_ BIDIMODE_ Msk - SPI_
CR1_ BIDIMODE_ Pos - SPI_
CR1_ BIDIOE - SPI_
CR1_ BIDIOE_ Msk - SPI_
CR1_ BIDIOE_ Pos - SPI_
CR1_ BR - SPI_
CR1_ BR_ 0 - SPI_
CR1_ BR_ 1 - SPI_
CR1_ BR_ 2 - SPI_
CR1_ BR_ Msk - SPI_
CR1_ BR_ Pos - SPI_
CR1_ CPHA - SPI_
CR1_ CPHA_ Msk - SPI_
CR1_ CPHA_ Pos - SPI_
CR1_ CPOL - SPI_
CR1_ CPOL_ Msk - SPI_
CR1_ CPOL_ Pos - SPI_
CR1_ LSBFIRST - SPI_
CR1_ LSBFIRST_ Msk - SPI_
CR1_ LSBFIRST_ Pos - SPI_
CR1_ MSTR - SPI_
CR1_ MSTR_ Msk - SPI_
CR1_ MSTR_ Pos - SPI_
CR1_ RXONLY - SPI_
CR1_ RXONLY_ Msk - SPI_
CR1_ RXONLY_ Pos - SPI_
CR1_ SPE - SPI_
CR1_ SPE_ Msk - SPI_
CR1_ SPE_ Pos - SPI_
CR1_ SSI - SPI_
CR1_ SSI_ Msk - SPI_
CR1_ SSI_ Pos - SPI_
CR1_ SSM - SPI_
CR1_ SSM_ Msk - SPI_
CR1_ SSM_ Pos - SPI_
CR2_ DS - SPI_
CR2_ DS_ Msk - SPI_
CR2_ DS_ Pos - SPI_
CR2_ ERRIE - SPI_
CR2_ ERRIE_ Msk - SPI_
CR2_ ERRIE_ Pos - SPI_
CR2_ FRXTH - SPI_
CR2_ FRXTH_ Msk - SPI_
CR2_ FRXTH_ Pos - SPI_
CR2_ LDMA_ RX - SPI_
CR2_ LDMA_ RX_ Msk - SPI_
CR2_ LDMA_ RX_ Pos - SPI_
CR2_ LDMA_ TX - SPI_
CR2_ LDMA_ TX_ Msk - SPI_
CR2_ LDMA_ TX_ Pos - SPI_
CR2_ RXDMAEN - SPI_
CR2_ RXDMAEN_ Msk - SPI_
CR2_ RXDMAEN_ Pos - SPI_
CR2_ RXNEIE - SPI_
CR2_ RXNEIE_ Msk - SPI_
CR2_ RXNEIE_ Pos - SPI_
CR2_ SLVFM - SPI_
CR2_ SLVFM_ Msk - SPI_
CR2_ SLVFM_ Pos - SPI_
CR2_ SSOE - SPI_
CR2_ SSOE_ Msk - SPI_
CR2_ SSOE_ Pos - SPI_
CR2_ TXDMAEN - SPI_
CR2_ TXDMAEN_ Msk - SPI_
CR2_ TXDMAEN_ Pos - SPI_
CR2_ TXEIE - SPI_
CR2_ TXEIE_ Msk - SPI_
CR2_ TXEIE_ Pos - SPI_
DATASIZE_ 8BIT - SPI_
DATASIZE_ 16BIT - SPI_
DIRECTION_ 1LINE - SPI_
DIRECTION_ 2LINES - SPI_
DIRECTION_ 2LINES_ RXONLY - SPI_
DR_ DR - SPI_
DR_ DR_ Msk - SPI_
DR_ DR_ Pos - SPI_
FIRSTBIT_ LSB - SPI_
FIRSTBIT_ MSB - SPI_
FLAG_ BSY - SPI_
FLAG_ FRLVL - SPI_
FLAG_ FTLVL - SPI_
FLAG_ MASK - SPI_
FLAG_ MODF - SPI_
FLAG_ OVR - SPI_
FLAG_ RXNE - SPI_
FLAG_ TXE - SPI_
FRLVL_ EMPTY - SPI_
FRLVL_ FULL - SPI_
FRLVL_ HALF_ FULL - SPI_
FRLVL_ QUARTER_ FULL - SPI_
FTLVL_ EMPTY - SPI_
FTLVL_ FULL - SPI_
FTLVL_ HALF_ FULL - SPI_
FTLVL_ QUARTER_ FULL - SPI_
IT_ ERR - SPI_
IT_ RXNE - SPI_
IT_ TXE - SPI_
MODE_ MASTER - SPI_
MODE_ SLAVE - SPI_
NSS_ HARD_ INPUT - SPI_
NSS_ HARD_ OUTPUT - SPI_
NSS_ SOFT - SPI_
PHASE_ 1EDGE - SPI_
PHASE_ 2EDGE - SPI_
POLARITY_ HIGH - SPI_
POLARITY_ LOW - SPI_
RXFIFO_ THRESHOLD - SPI_
RXFIFO_ THRESHOLD_ HF - SPI_
RXFIFO_ THRESHOLD_ QF - SPI_
SLAVE_ FAST_ MODE_ DISABLE - SPI_
SLAVE_ FAST_ MODE_ ENABLE - SPI_
SR_ BSY - SPI_
SR_ BSY_ Msk - SPI_
SR_ BSY_ Pos - SPI_
SR_ FRLVL - SPI_
SR_ FRLVL_ 0 - SPI_
SR_ FRLVL_ 1 - SPI_
SR_ FRLVL_ Msk - SPI_
SR_ FRLVL_ Pos - SPI_
SR_ FTLVL - SPI_
SR_ FTLVL_ 0 - SPI_
SR_ FTLVL_ 1 - SPI_
SR_ FTLVL_ Msk - SPI_
SR_ FTLVL_ Pos - SPI_
SR_ MODF - SPI_
SR_ MODF_ Msk - SPI_
SR_ MODF_ Pos - SPI_
SR_ OVR - SPI_
SR_ OVR_ Msk - SPI_
SR_ OVR_ Pos - SPI_
SR_ RXNE - SPI_
SR_ RXNE_ Msk - SPI_
SR_ RXNE_ Pos - SPI_
SR_ TXE - SPI_
SR_ TXE_ Msk - SPI_
SR_ TXE_ Pos - SRAM_
BASE - SRAM_
END - SYSCFG
- SYSCFG_
BASE - SYSCFG_
BOOT_ MAINFLASH - SYSCFG_
BOOT_ SRAM - SYSCFG_
BOOT_ SYSTEMFLASH - SYSCFG_
CFGR1_ I2C_ PA2_ ANF - SYSCFG_
CFGR1_ I2C_ PA2_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PA2_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PA3_ ANF - SYSCFG_
CFGR1_ I2C_ PA3_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PA3_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PA7_ ANF - SYSCFG_
CFGR1_ I2C_ PA7_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PA7_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PA8_ ANF - SYSCFG_
CFGR1_ I2C_ PA8_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PA8_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PA9_ ANF - SYSCFG_
CFGR1_ I2C_ PA9_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PA9_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PA10_ ANF - SYSCFG_
CFGR1_ I2C_ PA10_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PA10_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PA11_ ANF - SYSCFG_
CFGR1_ I2C_ PA11_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PA11_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PA12_ ANF - SYSCFG_
CFGR1_ I2C_ PA12_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PA12_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PB6_ ANF - SYSCFG_
CFGR1_ I2C_ PB6_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PB6_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PB7_ ANF - SYSCFG_
CFGR1_ I2C_ PB7_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PB7_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PB8_ ANF - SYSCFG_
CFGR1_ I2C_ PB8_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PB8_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PF0_ ANF - SYSCFG_
CFGR1_ I2C_ PF0_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PF0_ ANF_ Pos - SYSCFG_
CFGR1_ I2C_ PF1_ ANF - SYSCFG_
CFGR1_ I2C_ PF1_ ANF_ Msk - SYSCFG_
CFGR1_ I2C_ PF1_ ANF_ Pos - SYSCFG_
CFGR1_ MEM_ MODE - SYSCFG_
CFGR1_ MEM_ MODE_ 0 - SYSCFG_
CFGR1_ MEM_ MODE_ 1 - SYSCFG_
CFGR1_ MEM_ MODE_ Msk - SYSCFG_
CFGR1_ MEM_ MODE_ Pos - SYSCFG_
CFGR2_ COMP1_ BRK_ TIM1 - SYSCFG_
CFGR2_ COMP1_ BRK_ TIM1_ Msk - SYSCFG_
CFGR2_ COMP1_ BRK_ TIM1_ Pos - SYSCFG_
CFGR2_ COMP1_ BRK_ TIM16 - SYSCFG_
CFGR2_ COMP1_ BRK_ TIM17 - SYSCFG_
CFGR2_ COMP1_ BRK_ TIM16_ Msk - SYSCFG_
CFGR2_ COMP1_ BRK_ TIM16_ Pos - SYSCFG_
CFGR2_ COMP1_ BRK_ TIM17_ Msk - SYSCFG_
CFGR2_ COMP1_ BRK_ TIM17_ Pos - SYSCFG_
CFGR2_ COMP2_ BRK_ TIM1 - SYSCFG_
CFGR2_ COMP2_ BRK_ TIM1_ Msk - SYSCFG_
CFGR2_ COMP2_ BRK_ TIM1_ Pos - SYSCFG_
CFGR2_ COMP2_ BRK_ TIM16 - SYSCFG_
CFGR2_ COMP2_ BRK_ TIM17 - SYSCFG_
CFGR2_ COMP2_ BRK_ TIM16_ Msk - SYSCFG_
CFGR2_ COMP2_ BRK_ TIM16_ Pos - SYSCFG_
CFGR2_ COMP2_ BRK_ TIM17_ Msk - SYSCFG_
CFGR2_ COMP2_ BRK_ TIM17_ Pos - SYSCFG_
CFGR2_ ETR_ SRC_ TIM1 - SYSCFG_
CFGR2_ ETR_ SRC_ TIM1_ 0 - SYSCFG_
CFGR2_ ETR_ SRC_ TIM1_ 1 - SYSCFG_
CFGR2_ ETR_ SRC_ TIM1_ Msk - SYSCFG_
CFGR2_ ETR_ SRC_ TIM1_ Pos - SYSCFG_
CFGR2_ LOCKUP_ LOCK - SYSCFG_
CFGR2_ LOCKUP_ LOCK_ Msk - SYSCFG_
CFGR2_ LOCKUP_ LOCK_ Pos - SYSCFG_
CFGR2_ PVD_ LOCK - SYSCFG_
CFGR2_ PVD_ LOCK_ Msk - SYSCFG_
CFGR2_ PVD_ LOCK_ Pos - SYSCFG_
CFGR3_ DMA1_ ACKLVL - SYSCFG_
CFGR3_ DMA1_ ACKLVL_ Msk - SYSCFG_
CFGR3_ DMA1_ ACKLVL_ Pos - SYSCFG_
CFGR3_ DMA1_ MAP - SYSCFG_
CFGR3_ DMA1_ MAP_ 0 - SYSCFG_
CFGR3_ DMA1_ MAP_ 1 - SYSCFG_
CFGR3_ DMA1_ MAP_ 2 - SYSCFG_
CFGR3_ DMA1_ MAP_ 3 - SYSCFG_
CFGR3_ DMA1_ MAP_ 4 - SYSCFG_
CFGR3_ DMA1_ MAP_ Msk - SYSCFG_
CFGR3_ DMA1_ MAP_ Pos - SYSCFG_
CFGR3_ DMA2_ ACKLVL - SYSCFG_
CFGR3_ DMA2_ ACKLVL_ Msk - SYSCFG_
CFGR3_ DMA2_ ACKLVL_ Pos - SYSCFG_
CFGR3_ DMA2_ MAP - SYSCFG_
CFGR3_ DMA2_ MAP_ 0 - SYSCFG_
CFGR3_ DMA2_ MAP_ 1 - SYSCFG_
CFGR3_ DMA2_ MAP_ 2 - SYSCFG_
CFGR3_ DMA2_ MAP_ 3 - SYSCFG_
CFGR3_ DMA2_ MAP_ 4 - SYSCFG_
CFGR3_ DMA2_ MAP_ Msk - SYSCFG_
CFGR3_ DMA2_ MAP_ Pos - SYSCFG_
CFGR3_ DMA3_ ACKLVL - SYSCFG_
CFGR3_ DMA3_ ACKLVL_ Msk - SYSCFG_
CFGR3_ DMA3_ ACKLVL_ Pos - SYSCFG_
CFGR3_ DMA3_ MAP - SYSCFG_
CFGR3_ DMA3_ MAP_ 0 - SYSCFG_
CFGR3_ DMA3_ MAP_ 1 - SYSCFG_
CFGR3_ DMA3_ MAP_ 2 - SYSCFG_
CFGR3_ DMA3_ MAP_ 3 - SYSCFG_
CFGR3_ DMA3_ MAP_ 4 - SYSCFG_
CFGR3_ DMA3_ MAP_ Msk - SYSCFG_
CFGR3_ DMA3_ MAP_ Pos - SYSTICK_
CLKSOURCE_ HCLK - SYSTICK_
CLKSOURCE_ HCLK_ DIV8 - SysTick
- SysTick_
BASE - SysTick_
CALIB_ NOREF_ Msk - SysTick_
CALIB_ NOREF_ Pos - SysTick_
CALIB_ SKEW_ Msk - SysTick_
CALIB_ SKEW_ Pos - SysTick_
CALIB_ TENMS_ Msk - SysTick_
CALIB_ TENMS_ Pos - SysTick_
CTRL_ CLKSOURCE_ Msk - SysTick_
CTRL_ CLKSOURCE_ Pos - SysTick_
CTRL_ COUNTFLAG_ Msk - SysTick_
CTRL_ COUNTFLAG_ Pos - SysTick_
CTRL_ ENABLE_ Msk - SysTick_
CTRL_ ENABLE_ Pos - SysTick_
CTRL_ TICKINT_ Msk - SysTick_
CTRL_ TICKINT_ Pos - SysTick_
LOAD_ RELOAD_ Msk - SysTick_
LOAD_ RELOAD_ Pos - SysTick_
VAL_ CURRENT_ Msk - SysTick_
VAL_ CURRENT_ Pos - TICK_
INT_ PRIORITY - TIM1
- TIM3
- TIM1_
BASE - TIM3_
BASE - TIM14
- TIM16
- TIM17
- TIM14_
BASE - TIM14_
OR_ TI1_ RMP - TIM14_
OR_ TI1_ RMP_ 0 - TIM14_
OR_ TI1_ RMP_ 1 - TIM14_
OR_ TI1_ RMP_ Msk - TIM14_
OR_ TI1_ RMP_ Pos - TIM16_
BASE - TIM17_
BASE - TIM_
ARR_ ARR - TIM_
ARR_ ARR_ Msk - TIM_
ARR_ ARR_ Pos - TIM_
AUTOMATICOUTPUT_ DISABLE - TIM_
AUTOMATICOUTPUT_ ENABLE - TIM_
AUTORELOAD_ PRELOAD_ DISABLE - TIM_
AUTORELOAD_ PRELOAD_ ENABLE - TIM_
BDTR_ AOE - TIM_
BDTR_ AOE_ Msk - TIM_
BDTR_ AOE_ Pos - TIM_
BDTR_ BKE - TIM_
BDTR_ BKE_ Msk - TIM_
BDTR_ BKE_ Pos - TIM_
BDTR_ BKP - TIM_
BDTR_ BKP_ Msk - TIM_
BDTR_ BKP_ Pos - TIM_
BDTR_ DTG - TIM_
BDTR_ DTG_ 0 - TIM_
BDTR_ DTG_ 1 - TIM_
BDTR_ DTG_ 2 - TIM_
BDTR_ DTG_ 3 - TIM_
BDTR_ DTG_ 4 - TIM_
BDTR_ DTG_ 5 - TIM_
BDTR_ DTG_ 6 - TIM_
BDTR_ DTG_ 7 - TIM_
BDTR_ DTG_ Msk - TIM_
BDTR_ DTG_ Pos - TIM_
BDTR_ LOCK - TIM_
BDTR_ LOCK_ 0 - TIM_
BDTR_ LOCK_ 1 - TIM_
BDTR_ LOCK_ Msk - TIM_
BDTR_ LOCK_ Pos - TIM_
BDTR_ MOE - TIM_
BDTR_ MOE_ Msk - TIM_
BDTR_ MOE_ Pos - TIM_
BDTR_ OSSI - TIM_
BDTR_ OSSI_ Msk - TIM_
BDTR_ OSSI_ Pos - TIM_
BDTR_ OSSR - TIM_
BDTR_ OSSR_ Msk - TIM_
BDTR_ OSSR_ Pos - TIM_
BREAKPOLARITY_ HIGH - TIM_
BREAKPOLARITY_ LOW - TIM_
BREAK_ DISABLE - TIM_
BREAK_ ENABLE - TIM_
CCER_ CC1E - TIM_
CCER_ CC1E_ Msk - TIM_
CCER_ CC1E_ Pos - TIM_
CCER_ CC1NE - TIM_
CCER_ CC1NE_ Msk - TIM_
CCER_ CC1NE_ Pos - TIM_
CCER_ CC1NP - TIM_
CCER_ CC1NP_ Msk - TIM_
CCER_ CC1NP_ Pos - TIM_
CCER_ CC1P - TIM_
CCER_ CC1P_ Msk - TIM_
CCER_ CC1P_ Pos - TIM_
CCER_ CC2E - TIM_
CCER_ CC2E_ Msk - TIM_
CCER_ CC2E_ Pos - TIM_
CCER_ CC2NE - TIM_
CCER_ CC2NE_ Msk - TIM_
CCER_ CC2NE_ Pos - TIM_
CCER_ CC2NP - TIM_
CCER_ CC2NP_ Msk - TIM_
CCER_ CC2NP_ Pos - TIM_
CCER_ CC2P - TIM_
CCER_ CC2P_ Msk - TIM_
CCER_ CC2P_ Pos - TIM_
CCER_ CC3E - TIM_
CCER_ CC3E_ Msk - TIM_
CCER_ CC3E_ Pos - TIM_
CCER_ CC3NE - TIM_
CCER_ CC3NE_ Msk - TIM_
CCER_ CC3NE_ Pos - TIM_
CCER_ CC3NP - TIM_
CCER_ CC3NP_ Msk - TIM_
CCER_ CC3NP_ Pos - TIM_
CCER_ CC3P - TIM_
CCER_ CC3P_ Msk - TIM_
CCER_ CC3P_ Pos - TIM_
CCER_ CC4E - TIM_
CCER_ CC4E_ Msk - TIM_
CCER_ CC4E_ Pos - TIM_
CCER_ CC4NP - TIM_
CCER_ CC4NP_ Msk - TIM_
CCER_ CC4NP_ Pos - TIM_
CCER_ CC4P - TIM_
CCER_ CC4P_ Msk - TIM_
CCER_ CC4P_ Pos - TIM_
CCER_ CCxE_ MASK - TIM_
CCER_ CCxNE_ MASK - TIM_
CCMR1_ CC1S - TIM_
CCMR1_ CC1S_ 0 - TIM_
CCMR1_ CC1S_ 1 - TIM_
CCMR1_ CC1S_ Msk - TIM_
CCMR1_ CC1S_ Pos - TIM_
CCMR1_ CC2S - TIM_
CCMR1_ CC2S_ 0 - TIM_
CCMR1_ CC2S_ 1 - TIM_
CCMR1_ CC2S_ Msk - TIM_
CCMR1_ CC2S_ Pos - TIM_
CCMR1_ IC1F - TIM_
CCMR1_ IC1F_ 0 - TIM_
CCMR1_ IC1F_ 1 - TIM_
CCMR1_ IC1F_ 2 - TIM_
CCMR1_ IC1F_ 3 - TIM_
CCMR1_ IC1F_ Msk - TIM_
CCMR1_ IC1F_ Pos - TIM_
CCMR1_ IC1PSC - TIM_
CCMR1_ IC1PSC_ 0 - TIM_
CCMR1_ IC1PSC_ 1 - TIM_
CCMR1_ IC1PSC_ Msk - TIM_
CCMR1_ IC1PSC_ Pos - TIM_
CCMR1_ IC2F - TIM_
CCMR1_ IC2F_ 0 - TIM_
CCMR1_ IC2F_ 1 - TIM_
CCMR1_ IC2F_ 2 - TIM_
CCMR1_ IC2F_ 3 - TIM_
CCMR1_ IC2F_ Msk - TIM_
CCMR1_ IC2F_ Pos - TIM_
CCMR1_ IC2PSC - TIM_
CCMR1_ IC2PSC_ 0 - TIM_
CCMR1_ IC2PSC_ 1 - TIM_
CCMR1_ IC2PSC_ Msk - TIM_
CCMR1_ IC2PSC_ Pos - TIM_
CCMR1_ OC1CE - TIM_
CCMR1_ OC1CE_ Msk - TIM_
CCMR1_ OC1CE_ Pos - TIM_
CCMR1_ OC1FE - TIM_
CCMR1_ OC1FE_ Msk - TIM_
CCMR1_ OC1FE_ Pos - TIM_
CCMR1_ OC1M - TIM_
CCMR1_ OC1M_ 0 - TIM_
CCMR1_ OC1M_ 1 - TIM_
CCMR1_ OC1M_ 2 - TIM_
CCMR1_ OC1M_ Msk - TIM_
CCMR1_ OC1M_ Pos - TIM_
CCMR1_ OC1PE - TIM_
CCMR1_ OC1PE_ Msk - TIM_
CCMR1_ OC1PE_ Pos - TIM_
CCMR1_ OC2CE - TIM_
CCMR1_ OC2CE_ Msk - TIM_
CCMR1_ OC2CE_ Pos - TIM_
CCMR1_ OC2FE - TIM_
CCMR1_ OC2FE_ Msk - TIM_
CCMR1_ OC2FE_ Pos - TIM_
CCMR1_ OC2M - TIM_
CCMR1_ OC2M_ 0 - TIM_
CCMR1_ OC2M_ 1 - TIM_
CCMR1_ OC2M_ 2 - TIM_
CCMR1_ OC2M_ Msk - TIM_
CCMR1_ OC2M_ Pos - TIM_
CCMR1_ OC2PE - TIM_
CCMR1_ OC2PE_ Msk - TIM_
CCMR1_ OC2PE_ Pos - TIM_
CCMR2_ CC3S - TIM_
CCMR2_ CC3S_ 0 - TIM_
CCMR2_ CC3S_ 1 - TIM_
CCMR2_ CC3S_ Msk - TIM_
CCMR2_ CC3S_ Pos - TIM_
CCMR2_ CC4S - TIM_
CCMR2_ CC4S_ 0 - TIM_
CCMR2_ CC4S_ 1 - TIM_
CCMR2_ CC4S_ Msk - TIM_
CCMR2_ CC4S_ Pos - TIM_
CCMR2_ IC3F - TIM_
CCMR2_ IC3F_ 0 - TIM_
CCMR2_ IC3F_ 1 - TIM_
CCMR2_ IC3F_ 2 - TIM_
CCMR2_ IC3F_ 3 - TIM_
CCMR2_ IC3F_ Msk - TIM_
CCMR2_ IC3F_ Pos - TIM_
CCMR2_ IC3PSC - TIM_
CCMR2_ IC3PSC_ 0 - TIM_
CCMR2_ IC3PSC_ 1 - TIM_
CCMR2_ IC3PSC_ Msk - TIM_
CCMR2_ IC3PSC_ Pos - TIM_
CCMR2_ IC4F - TIM_
CCMR2_ IC4F_ 0 - TIM_
CCMR2_ IC4F_ 1 - TIM_
CCMR2_ IC4F_ 2 - TIM_
CCMR2_ IC4F_ 3 - TIM_
CCMR2_ IC4F_ Msk - TIM_
CCMR2_ IC4F_ Pos - TIM_
CCMR2_ IC4PSC - TIM_
CCMR2_ IC4PSC_ 0 - TIM_
CCMR2_ IC4PSC_ 1 - TIM_
CCMR2_ IC4PSC_ Msk - TIM_
CCMR2_ IC4PSC_ Pos - TIM_
CCMR2_ OC3CE - TIM_
CCMR2_ OC3CE_ Msk - TIM_
CCMR2_ OC3CE_ Pos - TIM_
CCMR2_ OC3FE - TIM_
CCMR2_ OC3FE_ Msk - TIM_
CCMR2_ OC3FE_ Pos - TIM_
CCMR2_ OC3M - TIM_
CCMR2_ OC3M_ 0 - TIM_
CCMR2_ OC3M_ 1 - TIM_
CCMR2_ OC3M_ 2 - TIM_
CCMR2_ OC3M_ Msk - TIM_
CCMR2_ OC3M_ Pos - TIM_
CCMR2_ OC3PE - TIM_
CCMR2_ OC3PE_ Msk - TIM_
CCMR2_ OC3PE_ Pos - TIM_
CCMR2_ OC4CE - TIM_
CCMR2_ OC4CE_ Msk - TIM_
CCMR2_ OC4CE_ Pos - TIM_
CCMR2_ OC4FE - TIM_
CCMR2_ OC4FE_ Msk - TIM_
CCMR2_ OC4FE_ Pos - TIM_
CCMR2_ OC4M - TIM_
CCMR2_ OC4M_ 0 - TIM_
CCMR2_ OC4M_ 1 - TIM_
CCMR2_ OC4M_ 2 - TIM_
CCMR2_ OC4M_ Msk - TIM_
CCMR2_ OC4M_ Pos - TIM_
CCMR2_ OC4PE - TIM_
CCMR2_ OC4PE_ Msk - TIM_
CCMR2_ OC4PE_ Pos - TIM_
CCR1_ CCR1 - TIM_
CCR1_ CCR1_ Msk - TIM_
CCR1_ CCR1_ Pos - TIM_
CCR2_ CCR2 - TIM_
CCR2_ CCR2_ Msk - TIM_
CCR2_ CCR2_ Pos - TIM_
CCR3_ CCR3 - TIM_
CCR3_ CCR3_ Msk - TIM_
CCR3_ CCR3_ Pos - TIM_
CCR4_ CCR4 - TIM_
CCR4_ CCR4_ Msk - TIM_
CCR4_ CCR4_ Pos - TIM_
CCxN_ DISABLE - TIM_
CCxN_ ENABLE - TIM_
CCx_ DISABLE - TIM_
CCx_ ENABLE - TIM_
CHANNEL_ 1 - TIM_
CHANNEL_ 2 - TIM_
CHANNEL_ 3 - TIM_
CHANNEL_ 4 - TIM_
CHANNEL_ ALL - TIM_
CLEARINPUTPOLARITY_ INVERTED - TIM_
CLEARINPUTPOLARITY_ NONINVERTED - TIM_
CLEARINPUTPRESCALER_ DIV1 - TIM_
CLEARINPUTPRESCALER_ DIV2 - TIM_
CLEARINPUTPRESCALER_ DIV4 - TIM_
CLEARINPUTPRESCALER_ DIV8 - TIM_
CLEARINPUTSOURCE_ ETR - TIM_
CLEARINPUTSOURCE_ NONE - TIM_
CLEARINPUTSOURCE_ OCREFCLR - TIM_
CLOCKDIVISION_ DIV1 - TIM_
CLOCKDIVISION_ DIV2 - TIM_
CLOCKDIVISION_ DIV4 - TIM_
CLOCKPOLARITY_ BOTHEDGE - TIM_
CLOCKPOLARITY_ FALLING - TIM_
CLOCKPOLARITY_ INVERTED - TIM_
CLOCKPOLARITY_ NONINVERTED - TIM_
CLOCKPOLARITY_ RISING - TIM_
CLOCKPRESCALER_ DIV1 - TIM_
CLOCKPRESCALER_ DIV2 - TIM_
CLOCKPRESCALER_ DIV4 - TIM_
CLOCKPRESCALER_ DIV8 - TIM_
CLOCKSOURCE_ ETRMOD E1 - TIM_
CLOCKSOURCE_ ETRMOD E2 - TIM_
CLOCKSOURCE_ INTERNAL - TIM_
CLOCKSOURCE_ ITR0 - TIM_
CLOCKSOURCE_ ITR1 - TIM_
CLOCKSOURCE_ ITR2 - TIM_
CLOCKSOURCE_ ITR3 - TIM_
CLOCKSOURCE_ TI1 - TIM_
CLOCKSOURCE_ TI2 - TIM_
CLOCKSOURCE_ TI1ED - TIM_
CNT_ CNT - TIM_
CNT_ CNT_ Msk - TIM_
CNT_ CNT_ Pos - TIM_
COMMUTATION_ SOFTWARE - TIM_
COMMUTATION_ TRGI - TIM_
COUNTERMODE_ CENTERALIGNE D1 - TIM_
COUNTERMODE_ CENTERALIGNE D2 - TIM_
COUNTERMODE_ CENTERALIGNE D3 - TIM_
COUNTERMODE_ DOWN - TIM_
COUNTERMODE_ UP - TIM_
CR1_ ARPE - TIM_
CR1_ ARPE_ Msk - TIM_
CR1_ ARPE_ Pos - TIM_
CR1_ CEN - TIM_
CR1_ CEN_ Msk - TIM_
CR1_ CEN_ Pos - TIM_
CR1_ CKD - TIM_
CR1_ CKD_ 0 - TIM_
CR1_ CKD_ 1 - TIM_
CR1_ CKD_ Msk - TIM_
CR1_ CKD_ Pos - TIM_
CR1_ CMS - TIM_
CR1_ CMS_ 0 - TIM_
CR1_ CMS_ 1 - TIM_
CR1_ CMS_ Msk - TIM_
CR1_ CMS_ Pos - TIM_
CR1_ DIR - TIM_
CR1_ DIR_ Msk - TIM_
CR1_ DIR_ Pos - TIM_
CR1_ OPM - TIM_
CR1_ OPM_ Msk - TIM_
CR1_ OPM_ Pos - TIM_
CR1_ UDIS - TIM_
CR1_ UDIS_ Msk - TIM_
CR1_ UDIS_ Pos - TIM_
CR1_ URS - TIM_
CR1_ URS_ Msk - TIM_
CR1_ URS_ Pos - TIM_
CR2_ CCDS - TIM_
CR2_ CCDS_ Msk - TIM_
CR2_ CCDS_ Pos - TIM_
CR2_ CCPC - TIM_
CR2_ CCPC_ Msk - TIM_
CR2_ CCPC_ Pos - TIM_
CR2_ CCUS - TIM_
CR2_ CCUS_ Msk - TIM_
CR2_ CCUS_ Pos - TIM_
CR2_ MMS - TIM_
CR2_ MMS_ 0 - TIM_
CR2_ MMS_ 1 - TIM_
CR2_ MMS_ 2 - TIM_
CR2_ MMS_ Msk - TIM_
CR2_ MMS_ Pos - TIM_
CR2_ OIS1 - TIM_
CR2_ OIS2 - TIM_
CR2_ OIS3 - TIM_
CR2_ OIS4 - TIM_
CR2_ OIS1N - TIM_
CR2_ OIS1N_ Msk - TIM_
CR2_ OIS1N_ Pos - TIM_
CR2_ OIS1_ Msk - TIM_
CR2_ OIS1_ Pos - TIM_
CR2_ OIS2N - TIM_
CR2_ OIS2N_ Msk - TIM_
CR2_ OIS2N_ Pos - TIM_
CR2_ OIS2_ Msk - TIM_
CR2_ OIS2_ Pos - TIM_
CR2_ OIS3N - TIM_
CR2_ OIS3N_ Msk - TIM_
CR2_ OIS3N_ Pos - TIM_
CR2_ OIS3_ Msk - TIM_
CR2_ OIS3_ Pos - TIM_
CR2_ OIS4_ Msk - TIM_
CR2_ OIS4_ Pos - TIM_
CR2_ TI1S - TIM_
CR2_ TI1S_ Msk - TIM_
CR2_ TI1S_ Pos - TIM_
DCR_ DBA - TIM_
DCR_ DBA_ 0 - TIM_
DCR_ DBA_ 1 - TIM_
DCR_ DBA_ 2 - TIM_
DCR_ DBA_ 3 - TIM_
DCR_ DBA_ 4 - TIM_
DCR_ DBA_ Msk - TIM_
DCR_ DBA_ Pos - TIM_
DCR_ DBL - TIM_
DCR_ DBL_ 0 - TIM_
DCR_ DBL_ 1 - TIM_
DCR_ DBL_ 2 - TIM_
DCR_ DBL_ 3 - TIM_
DCR_ DBL_ 4 - TIM_
DCR_ DBL_ Msk - TIM_
DCR_ DBL_ Pos - TIM_
DIER_ BIE - TIM_
DIER_ BIE_ Msk - TIM_
DIER_ BIE_ Pos - TIM_
DIER_ CC1DE - TIM_
DIER_ CC1DE_ Msk - TIM_
DIER_ CC1DE_ Pos - TIM_
DIER_ CC1IE - TIM_
DIER_ CC1IE_ Msk - TIM_
DIER_ CC1IE_ Pos - TIM_
DIER_ CC2DE - TIM_
DIER_ CC2DE_ Msk - TIM_
DIER_ CC2DE_ Pos - TIM_
DIER_ CC2IE - TIM_
DIER_ CC2IE_ Msk - TIM_
DIER_ CC2IE_ Pos - TIM_
DIER_ CC3DE - TIM_
DIER_ CC3DE_ Msk - TIM_
DIER_ CC3DE_ Pos - TIM_
DIER_ CC3IE - TIM_
DIER_ CC3IE_ Msk - TIM_
DIER_ CC3IE_ Pos - TIM_
DIER_ CC4DE - TIM_
DIER_ CC4DE_ Msk - TIM_
DIER_ CC4DE_ Pos - TIM_
DIER_ CC4IE - TIM_
DIER_ CC4IE_ Msk - TIM_
DIER_ CC4IE_ Pos - TIM_
DIER_ COMDE - TIM_
DIER_ COMDE_ Msk - TIM_
DIER_ COMDE_ Pos - TIM_
DIER_ COMIE - TIM_
DIER_ COMIE_ Msk - TIM_
DIER_ COMIE_ Pos - TIM_
DIER_ TDE - TIM_
DIER_ TDE_ Msk - TIM_
DIER_ TDE_ Pos - TIM_
DIER_ TIE - TIM_
DIER_ TIE_ Msk - TIM_
DIER_ TIE_ Pos - TIM_
DIER_ UDE - TIM_
DIER_ UDE_ Msk - TIM_
DIER_ UDE_ Pos - TIM_
DIER_ UIE - TIM_
DIER_ UIE_ Msk - TIM_
DIER_ UIE_ Pos - TIM_
DMABASE_ ARR - TIM_
DMABASE_ BDTR - TIM_
DMABASE_ CCER - TIM_
DMABASE_ CCMR1 - TIM_
DMABASE_ CCMR2 - TIM_
DMABASE_ CCR1 - TIM_
DMABASE_ CCR2 - TIM_
DMABASE_ CCR3 - TIM_
DMABASE_ CCR4 - TIM_
DMABASE_ CNT - TIM_
DMABASE_ CR1 - TIM_
DMABASE_ CR2 - TIM_
DMABASE_ DCR - TIM_
DMABASE_ DIER - TIM_
DMABASE_ DMAR - TIM_
DMABASE_ EGR - TIM_
DMABASE_ PSC - TIM_
DMABASE_ RCR - TIM_
DMABASE_ SMCR - TIM_
DMABASE_ SR - TIM_
DMABURSTLENGTH_ 1TRANSFER - TIM_
DMABURSTLENGTH_ 2TRANSFERS - TIM_
DMABURSTLENGTH_ 3TRANSFERS - TIM_
DMABURSTLENGTH_ 4TRANSFERS - TIM_
DMABURSTLENGTH_ 5TRANSFERS - TIM_
DMABURSTLENGTH_ 6TRANSFERS - TIM_
DMABURSTLENGTH_ 7TRANSFERS - TIM_
DMABURSTLENGTH_ 8TRANSFERS - TIM_
DMABURSTLENGTH_ 9TRANSFERS - TIM_
DMABURSTLENGTH_ 10TRANSFERS - TIM_
DMABURSTLENGTH_ 11TRANSFERS - TIM_
DMABURSTLENGTH_ 12TRANSFERS - TIM_
DMABURSTLENGTH_ 13TRANSFERS - TIM_
DMABURSTLENGTH_ 14TRANSFERS - TIM_
DMABURSTLENGTH_ 15TRANSFERS - TIM_
DMABURSTLENGTH_ 16TRANSFERS - TIM_
DMABURSTLENGTH_ 17TRANSFERS - TIM_
DMABURSTLENGTH_ 18TRANSFERS - TIM_
DMAR_ DMAB - TIM_
DMAR_ DMAB_ Msk - TIM_
DMAR_ DMAB_ Pos - TIM_
DMA_ CC1 - TIM_
DMA_ CC2 - TIM_
DMA_ CC3 - TIM_
DMA_ CC4 - TIM_
DMA_ COM - TIM_
DMA_ ID_ CC1 - TIM_
DMA_ ID_ CC2 - TIM_
DMA_ ID_ CC3 - TIM_
DMA_ ID_ CC4 - TIM_
DMA_ ID_ COMMUTATION - TIM_
DMA_ ID_ TRIGGER - TIM_
DMA_ ID_ UPDATE - TIM_
DMA_ TRIGGER - TIM_
DMA_ UPDATE - TIM_
EGR_ BG - TIM_
EGR_ BG_ Msk - TIM_
EGR_ BG_ Pos - TIM_
EGR_ CC1G - TIM_
EGR_ CC1G_ Msk - TIM_
EGR_ CC1G_ Pos - TIM_
EGR_ CC2G - TIM_
EGR_ CC2G_ Msk - TIM_
EGR_ CC2G_ Pos - TIM_
EGR_ CC3G - TIM_
EGR_ CC3G_ Msk - TIM_
EGR_ CC3G_ Pos - TIM_
EGR_ CC4G - TIM_
EGR_ CC4G_ Msk - TIM_
EGR_ CC4G_ Pos - TIM_
EGR_ COMG - TIM_
EGR_ COMG_ Msk - TIM_
EGR_ COMG_ Pos - TIM_
EGR_ TG - TIM_
EGR_ TG_ Msk - TIM_
EGR_ TG_ Pos - TIM_
EGR_ UG - TIM_
EGR_ UG_ Msk - TIM_
EGR_ UG_ Pos - TIM_
ENCODERINPUTPOLARITY_ BOTHEDGE - TIM_
ENCODERINPUTPOLARITY_ FALLING - TIM_
ENCODERINPUTPOLARITY_ RISING - TIM_
ENCODERMODE_ TI1 - TIM_
ENCODERMODE_ TI2 - TIM_
ENCODERMODE_ TI12 - TIM_
ETRPOLARITY_ INVERTED - TIM_
ETRPOLARITY_ NONINVERTED - TIM_
ETRPRESCALER_ DIV1 - TIM_
ETRPRESCALER_ DIV2 - TIM_
ETRPRESCALER_ DIV4 - TIM_
ETRPRESCALER_ DIV8 - TIM_
EVENTSOURCE_ BREAK - TIM_
EVENTSOURCE_ CC1 - TIM_
EVENTSOURCE_ CC2 - TIM_
EVENTSOURCE_ CC3 - TIM_
EVENTSOURCE_ CC4 - TIM_
EVENTSOURCE_ COM - TIM_
EVENTSOURCE_ TRIGGER - TIM_
EVENTSOURCE_ UPDATE - TIM_
FLAG_ BREAK - TIM_
FLAG_ CC1 - TIM_
FLAG_ CC2 - TIM_
FLAG_ CC3 - TIM_
FLAG_ CC4 - TIM_
FLAG_ CC1OF - TIM_
FLAG_ CC2OF - TIM_
FLAG_ CC3OF - TIM_
FLAG_ CC4OF - TIM_
FLAG_ COM - TIM_
FLAG_ TRIGGER - TIM_
FLAG_ UPDATE - TIM_
ICPOLARITY_ BOTHEDGE - TIM_
ICPOLARITY_ FALLING - TIM_
ICPOLARITY_ RISING - TIM_
ICPSC_ DIV1 - TIM_
ICPSC_ DIV2 - TIM_
ICPSC_ DIV4 - TIM_
ICPSC_ DIV8 - TIM_
ICSELECTION_ DIRECTTI - TIM_
ICSELECTION_ INDIRECTTI - TIM_
ICSELECTION_ TRC - TIM_
INPUTCHANNELPOLARITY_ BOTHEDGE - TIM_
INPUTCHANNELPOLARITY_ FALLING - TIM_
INPUTCHANNELPOLARITY_ RISING - TIM_
IT_ BREAK - TIM_
IT_ CC1 - TIM_
IT_ CC2 - TIM_
IT_ CC3 - TIM_
IT_ CC4 - TIM_
IT_ COM - TIM_
IT_ TRIGGER - TIM_
IT_ UPDATE - TIM_
LOCKLEVEL_ 1 - TIM_
LOCKLEVEL_ 2 - TIM_
LOCKLEVEL_ 3 - TIM_
LOCKLEVEL_ OFF - TIM_
MASTERSLAVEMODE_ DISABLE - TIM_
MASTERSLAVEMODE_ ENABLE - TIM_
OCFAST_ DISABLE - TIM_
OCFAST_ ENABLE - TIM_
OCIDLESTATE_ RESET - TIM_
OCIDLESTATE_ SET - TIM_
OCMODE_ ACTIVE - TIM_
OCMODE_ FORCED_ ACTIVE - TIM_
OCMODE_ FORCED_ INACTIVE - TIM_
OCMODE_ INACTIVE - TIM_
OCMODE_ PWM1 - TIM_
OCMODE_ PWM2 - TIM_
OCMODE_ TIMING - TIM_
OCMODE_ TOGGLE - TIM_
OCNIDLESTATE_ RESET - TIM_
OCNIDLESTATE_ SET - TIM_
OCNPOLARITY_ HIGH - TIM_
OCNPOLARITY_ LOW - TIM_
OCPOLARITY_ HIGH - TIM_
OCPOLARITY_ LOW - TIM_
OPMODE_ REPETITIVE - TIM_
OPMODE_ SINGLE - TIM_
OSSI_ DISABLE - TIM_
OSSI_ ENABLE - TIM_
OSSR_ DISABLE - TIM_
OSSR_ ENABLE - TIM_
OUTPUTNSTATE_ DISABLE - TIM_
OUTPUTNSTATE_ ENABLE - TIM_
OUTPUTSTATE_ DISABLE - TIM_
OUTPUTSTATE_ ENABLE - TIM_
PSC_ PSC - TIM_
PSC_ PSC_ Msk - TIM_
PSC_ PSC_ Pos - TIM_
RCR_ REP - TIM_
RCR_ REP_ Msk - TIM_
RCR_ REP_ Pos - TIM_
SLAVEMODE_ DISABLE - TIM_
SLAVEMODE_ EXTERNA L1 - TIM_
SLAVEMODE_ GATED - TIM_
SLAVEMODE_ RESET - TIM_
SLAVEMODE_ TRIGGER - TIM_
SMCR_ ECE - TIM_
SMCR_ ECE_ Msk - TIM_
SMCR_ ECE_ Pos - TIM_
SMCR_ ETF - TIM_
SMCR_ ETF_ 0 - TIM_
SMCR_ ETF_ 1 - TIM_
SMCR_ ETF_ 2 - TIM_
SMCR_ ETF_ 3 - TIM_
SMCR_ ETF_ Msk - TIM_
SMCR_ ETF_ Pos - TIM_
SMCR_ ETP - TIM_
SMCR_ ETPS - TIM_
SMCR_ ETPS_ 0 - TIM_
SMCR_ ETPS_ 1 - TIM_
SMCR_ ETPS_ Msk - TIM_
SMCR_ ETPS_ Pos - TIM_
SMCR_ ETP_ Msk - TIM_
SMCR_ ETP_ Pos - TIM_
SMCR_ MSM - TIM_
SMCR_ MSM_ Msk - TIM_
SMCR_ MSM_ Pos - TIM_
SMCR_ OCCS - TIM_
SMCR_ OCCS_ Msk - TIM_
SMCR_ OCCS_ Pos - TIM_
SMCR_ SMS - TIM_
SMCR_ SMS_ 0 - TIM_
SMCR_ SMS_ 1 - TIM_
SMCR_ SMS_ 2 - TIM_
SMCR_ SMS_ Msk - TIM_
SMCR_ SMS_ Pos - TIM_
SMCR_ TS - TIM_
SMCR_ TS_ 0 - TIM_
SMCR_ TS_ 1 - TIM_
SMCR_ TS_ 2 - TIM_
SMCR_ TS_ Msk - TIM_
SMCR_ TS_ Pos - TIM_
SR_ BIF - TIM_
SR_ BIF_ Msk - TIM_
SR_ BIF_ Pos - TIM_
SR_ CC1IF - TIM_
SR_ CC1IF_ Msk - TIM_
SR_ CC1IF_ Pos - TIM_
SR_ CC1OF - TIM_
SR_ CC1OF_ Msk - TIM_
SR_ CC1OF_ Pos - TIM_
SR_ CC2IF - TIM_
SR_ CC2IF_ Msk - TIM_
SR_ CC2IF_ Pos - TIM_
SR_ CC2OF - TIM_
SR_ CC2OF_ Msk - TIM_
SR_ CC2OF_ Pos - TIM_
SR_ CC3IF - TIM_
SR_ CC3IF_ Msk - TIM_
SR_ CC3IF_ Pos - TIM_
SR_ CC3OF - TIM_
SR_ CC3OF_ Msk - TIM_
SR_ CC3OF_ Pos - TIM_
SR_ CC4IF - TIM_
SR_ CC4IF_ Msk - TIM_
SR_ CC4IF_ Pos - TIM_
SR_ CC4OF - TIM_
SR_ CC4OF_ Msk - TIM_
SR_ CC4OF_ Pos - TIM_
SR_ COMIF - TIM_
SR_ COMIF_ Msk - TIM_
SR_ COMIF_ Pos - TIM_
SR_ TIF - TIM_
SR_ TIF_ Msk - TIM_
SR_ TIF_ Pos - TIM_
SR_ UIF - TIM_
SR_ UIF_ Msk - TIM_
SR_ UIF_ Pos - TIM_
TI1SELECTION_ CH1 - TIM_
TI1SELECTION_ XORCOMBINATION - TIM_
TIM14_ GPIO - TIM_
TIM14_ HSE - TIM_
TIM14_ MCO - TIM_
TIM14_ RTC - TIM_
TRGO_ ENABLE - TIM_
TRGO_ OC1 - TIM_
TRGO_ OC1REF - TIM_
TRGO_ OC2REF - TIM_
TRGO_ OC3REF - TIM_
TRGO_ OC4REF - TIM_
TRGO_ RESET - TIM_
TRGO_ UPDATE - TIM_
TRIGGERPOLARITY_ BOTHEDGE - TIM_
TRIGGERPOLARITY_ FALLING - TIM_
TRIGGERPOLARITY_ INVERTED - TIM_
TRIGGERPOLARITY_ NONINVERTED - TIM_
TRIGGERPOLARITY_ RISING - TIM_
TRIGGERPRESCALER_ DIV1 - TIM_
TRIGGERPRESCALER_ DIV2 - TIM_
TRIGGERPRESCALER_ DIV4 - TIM_
TRIGGERPRESCALER_ DIV8 - TIM_
TS_ ETRF - TIM_
TS_ ITR0 - TIM_
TS_ ITR1 - TIM_
TS_ ITR2 - TIM_
TS_ ITR3 - TIM_
TS_ NONE - TIM_
TS_ TI1F P1 - TIM_
TS_ TI1F_ ED - TIM_
TS_ TI2F P2 - UART_
ADVFEATURE_ AUTOBAUDRATE_ DISABLE - UART_
ADVFEATURE_ AUTOBAUDRATE_ ENABLE - UART_
ADVFEATURE_ AUTOBAUDRATE_ INIT - UART_
ADVFEATURE_ AUTOBAUDRATE_ ONFALLINGEDGE - UART_
ADVFEATURE_ AUTOBAUDRATE_ ONSTARTBIT - UART_
ADVFEATURE_ NO_ INIT - UART_
CR1_ REG_ INDEX - UART_
CR2_ REG_ INDEX - UART_
CR3_ REG_ INDEX - UART_
FLAG_ ABRE - UART_
FLAG_ ABRF - UART_
FLAG_ CTS - UART_
FLAG_ FE - UART_
FLAG_ IDLE - UART_
FLAG_ NE - UART_
FLAG_ ORE - UART_
FLAG_ PE - UART_
FLAG_ RXNE - UART_
FLAG_ TC - UART_
FLAG_ TXE - UART_
HWCONTROL_ CTS - UART_
HWCONTROL_ NONE - UART_
HWCONTROL_ RTS - UART_
HWCONTROL_ RTS_ CTS - UART_
IT_ CTS - UART_
IT_ ERR - UART_
IT_ IDLE - UART_
IT_ MASK - UART_
IT_ PE - UART_
IT_ RXNE - UART_
IT_ TC - UART_
IT_ TXE - UART_
LINBREAKDETECTLENGTH_ 10B - UART_
MODE_ RX - UART_
MODE_ TX - UART_
MODE_ TX_ RX - UART_
OVERSAMPLING_ 8 - UART_
OVERSAMPLING_ 16 - UART_
PARITY_ EVEN - UART_
PARITY_ NONE - UART_
PARITY_ ODD - UART_
STATE_ DISABLE - UART_
STATE_ ENABLE - UART_
STOPBITS_ 1 - UART_
STOPBITS_ 2 - UART_
WAKEUPMETHOD_ ADDRESSMARK - UART_
WAKEUPMETHOD_ IDLELINE - UART_
WORDLENGTH_ 8B - UART_
WORDLENGTH_ 9B - UID_
BASE - USART1
- USART2
- USAR
T1_ BASE - USAR
T2_ BASE - USART_
BRR_ DIV_ Fraction - USART_
BRR_ DIV_ Fraction_ Msk - USART_
BRR_ DIV_ Fraction_ Pos - USART_
BRR_ DIV_ Mantissa - USART_
BRR_ DIV_ Mantissa_ Msk - USART_
BRR_ DIV_ Mantissa_ Pos - USART_
CR1_ IDLEIE - USART_
CR1_ IDLEIE_ Msk - USART_
CR1_ IDLEIE_ Pos - USART_
CR1_ M - USART_
CR1_ M_ Msk - USART_
CR1_ M_ Pos - USART_
CR1_ PCE - USART_
CR1_ PCE_ Msk - USART_
CR1_ PCE_ Pos - USART_
CR1_ PEIE - USART_
CR1_ PEIE_ Msk - USART_
CR1_ PEIE_ Pos - USART_
CR1_ PS - USART_
CR1_ PS_ Msk - USART_
CR1_ PS_ Pos - USART_
CR1_ RE - USART_
CR1_ RE_ Msk - USART_
CR1_ RE_ Pos - USART_
CR1_ RWU - USART_
CR1_ RWU_ Msk - USART_
CR1_ RWU_ Pos - USART_
CR1_ RXNEIE - USART_
CR1_ RXNEIE_ Msk - USART_
CR1_ RXNEIE_ Pos - USART_
CR1_ SBK - USART_
CR1_ SBK_ Msk - USART_
CR1_ SBK_ Pos - USART_
CR1_ TCIE - USART_
CR1_ TCIE_ Msk - USART_
CR1_ TCIE_ Pos - USART_
CR1_ TE - USART_
CR1_ TE_ Msk - USART_
CR1_ TE_ Pos - USART_
CR1_ TXEIE - USART_
CR1_ TXEIE_ Msk - USART_
CR1_ TXEIE_ Pos - USART_
CR1_ UE - USART_
CR1_ UE_ Msk - USART_
CR1_ UE_ Pos - USART_
CR1_ WAKE - USART_
CR1_ WAKE_ Msk - USART_
CR1_ WAKE_ Pos - USART_
CR2_ ADD - USART_
CR2_ ADD_ Msk - USART_
CR2_ ADD_ Pos - USART_
CR2_ CLKEN - USART_
CR2_ CLKEN_ Msk - USART_
CR2_ CLKEN_ Pos - USART_
CR2_ CPHA - USART_
CR2_ CPHA_ Msk - USART_
CR2_ CPHA_ Pos - USART_
CR2_ CPOL - USART_
CR2_ CPOL_ Msk - USART_
CR2_ CPOL_ Pos - USART_
CR2_ LBCL - USART_
CR2_ LBCL_ Msk - USART_
CR2_ LBCL_ Pos - USART_
CR2_ STOP - USART_
CR2_ STOP_ Msk - USART_
CR2_ STOP_ Pos - USART_
CR3_ ABREN - USART_
CR3_ ABREN_ Msk - USART_
CR3_ ABREN_ Pos - USART_
CR3_ ABRMODE - USART_
CR3_ ABRMODE_ 0 - USART_
CR3_ ABRMODE_ 1 - USART_
CR3_ ABRMODE_ Msk - USART_
CR3_ ABRMODE_ Pos - USART_
CR3_ CTSE - USART_
CR3_ CTSE_ Msk - USART_
CR3_ CTSE_ Pos - USART_
CR3_ CTSIE - USART_
CR3_ CTSIE_ Msk - USART_
CR3_ CTSIE_ Pos - USART_
CR3_ DMAR - USART_
CR3_ DMAR_ Msk - USART_
CR3_ DMAR_ Pos - USART_
CR3_ DMAT - USART_
CR3_ DMAT_ Msk - USART_
CR3_ DMAT_ Pos - USART_
CR3_ EIE - USART_
CR3_ EIE_ Msk - USART_
CR3_ EIE_ Pos - USART_
CR3_ HDSEL - USART_
CR3_ HDSEL_ Msk - USART_
CR3_ HDSEL_ Pos - USART_
CR3_ OVER8 - USART_
CR3_ OVER8_ Msk - USART_
CR3_ OVER8_ Pos - USART_
CR3_ RTSE - USART_
CR3_ RTSE_ Msk - USART_
CR3_ RTSE_ Pos - USART_
DR_ DR - USART_
DR_ DR_ Msk - USART_
DR_ DR_ Pos - USART_
SR_ ABRE - USART_
SR_ ABRE_ Msk - USART_
SR_ ABRE_ Pos - USART_
SR_ ABRF - USART_
SR_ ABRF_ Msk - USART_
SR_ ABRF_ Pos - USART_
SR_ ABRRQ - USART_
SR_ ABRRQ_ Msk - USART_
SR_ ABRRQ_ Pos - USART_
SR_ CTS - USART_
SR_ CTS_ Msk - USART_
SR_ CTS_ Pos - USART_
SR_ FE - USART_
SR_ FE_ Msk - USART_
SR_ FE_ Pos - USART_
SR_ IDLE - USART_
SR_ IDLE_ Msk - USART_
SR_ IDLE_ Pos - USART_
SR_ NE - USART_
SR_ NE_ Msk - USART_
SR_ NE_ Pos - USART_
SR_ ORE - USART_
SR_ ORE_ Msk - USART_
SR_ ORE_ Pos - USART_
SR_ PE - USART_
SR_ PE_ Msk - USART_
SR_ PE_ Pos - USART_
SR_ RXNE - USART_
SR_ RXNE_ Msk - USART_
SR_ RXNE_ Pos - USART_
SR_ TC - USART_
SR_ TC_ Msk - USART_
SR_ TC_ Pos - USART_
SR_ TXE - USART_
SR_ TXE_ Msk - USART_
SR_ TXE_ Pos - USE_
RTOS - VDD_
VALUE - WWDG
- WWDG_
BASE - WWDG_
CFR_ EWI - WWDG_
CFR_ EWI_ Msk - WWDG_
CFR_ EWI_ Pos - WWDG_
CFR_ W - WWDG_
CFR_ WDGTB - WWDG_
CFR_ WDGTB_ 0 - WWDG_
CFR_ WDGTB_ 1 - WWDG_
CFR_ WDGTB_ Msk - WWDG_
CFR_ WDGTB_ Pos - WWDG_
CFR_ W_ 0 - WWDG_
CFR_ W_ 1 - WWDG_
CFR_ W_ 2 - WWDG_
CFR_ W_ 3 - WWDG_
CFR_ W_ 4 - WWDG_
CFR_ W_ 5 - WWDG_
CFR_ W_ 6 - WWDG_
CFR_ W_ Msk - WWDG_
CFR_ W_ Pos - WWDG_
CR_ T - WWDG_
CR_ T_ 0 - WWDG_
CR_ T_ 1 - WWDG_
CR_ T_ 2 - WWDG_
CR_ T_ 3 - WWDG_
CR_ T_ 4 - WWDG_
CR_ T_ 5 - WWDG_
CR_ T_ 6 - WWDG_
CR_ T_ Msk - WWDG_
CR_ T_ Pos - WWDG_
CR_ WDGA - WWDG_
CR_ WDGA_ Msk - WWDG_
CR_ WDGA_ Pos - WWDG_
EWI_ DISABLE - WWDG_
EWI_ ENABLE - WWDG_
FLAG_ EWIF - WWDG_
IT_ EWI - WWDG_
PRESCALER_ 1 - WWDG_
PRESCALER_ 2 - WWDG_
PRESCALER_ 4 - WWDG_
PRESCALER_ 8 - WWDG_
SR_ EWIF - WWDG_
SR_ EWIF_ Msk - WWDG_
SR_ EWIF_ Pos - __
CM0PLUS_ CMSIS_ VERSION - __
CM0PLUS_ CMSIS_ VERSION_ MAIN - __
CM0PLUS_ CMSIS_ VERSION_ SUB - __
CM0PLUS_ REV - __
CORTEX_ M - __
FPU_ USED - __
MPU_ PRESENT - __
NVIC_ PRIO_ BITS - __
PY32 F0_ DEVICE_ VERSION - __
PY32 F0_ DEVICE_ VERSION_ MAIN - __
PY32 F0_ DEVICE_ VERSION_ RC - __
PY32 F0_ DEVICE_ VERSION_ SUB1 - __
PY32 F0_ DEVICE_ VERSION_ SUB2 - __
VTOR_ PRESENT - __
Vendor_ SysTick Config - xPSR_
C_ Msk - xPSR_
C_ Pos - xPSR_
ISR_ Msk - xPSR_
ISR_ Pos - xPSR_
N_ Msk - xPSR_
N_ Pos - xPSR_
T_ Msk - xPSR_
T_ Pos - xPSR_
V_ Msk - xPSR_
V_ Pos - xPSR_
Z_ Msk - xPSR_
Z_ Pos
Statics§
- AHBPresc
Table ⚠ - < AHB prescalers table values
- APBPresc
Table ⚠ - < APB prescalers table values
- HSIFreq
Table ⚠ - < HSI frequency table values
- System
Core ⚠Clock - < System Clock Frequency (Core Clock)
- pFlash⚠
- @defgroup FLASH_Exported_Variables FLASH Exported Variables @{
- uwTick
Freq ⚠ - uwTick
Prio ⚠ - @}
Functions§
- FLASH_
Wait ⚠ForLast Operation - @defgroup FLASH_Private_types FLASH Private Types @{
- HAL_
ADC_ ⚠AnalogWDG Config - HAL_
ADC_ ⚠Calibration_ Start - HAL_
ADC_ ⚠Config Channel - @addtogroup ADC_Exported_Functions_Group3 @{
- HAL_
ADC_ ⚠Conv Cplt Callback - HAL_
ADC_ ⚠Conv Half Cplt Callback - HAL_
ADC_ ⚠DeInit - HAL_
ADC_ ⚠Error Callback - HAL_
ADC_ ⚠GetCalib Status - HAL_
ADC_ ⚠GetError - HAL_
ADC_ ⚠GetState - @addtogroup ADC_Exported_Functions_Group4 @{
- HAL_
ADC_ ⚠GetValue - HAL_
ADC_ ⚠IRQHandler - HAL_
ADC_ ⚠Init - @addtogroup ADC_Exported_Functions_Group1 @{
- HAL_
ADC_ ⚠Level OutOf Window Callback - HAL_
ADC_ ⚠MspDe Init - HAL_
ADC_ ⚠MspInit - HAL_
ADC_ ⚠Poll ForConversion - HAL_
ADC_ ⚠Poll ForEvent - HAL_
ADC_ ⚠SetCalibration - HAL_
ADC_ ⚠Start - @addtogroup ADC_Exported_Functions_Group2 @{
- HAL_
ADC_ ⚠Start_ DMA - HAL_
ADC_ ⚠Start_ IT - HAL_
ADC_ ⚠Stop - HAL_
ADC_ ⚠Stop_ DMA - HAL_
ADC_ ⚠Stop_ IT - HAL_
CRC_ ⚠Accumulate - @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions @{
- HAL_
CRC_ ⚠Calculate - HAL_
CRC_ ⚠DeInit - HAL_
CRC_ ⚠GetState - @defgroup CRC_Exported_Functions_Group3 Peripheral State functions @{
- HAL_
CRC_ ⚠Init - @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions @{
- HAL_
CRC_ ⚠MspDe Init - HAL_
CRC_ ⚠MspInit - HAL_
DBGMCU_ ⚠DisableDBG Sleep Mode - HAL_
DBGMCU_ ⚠DisableDBG Stop Mode - HAL_
DBGMCU_ ⚠EnableDBG Sleep Mode - HAL_
DBGMCU_ ⚠EnableDBG Stop Mode - HAL_
DMA_ ⚠Abort - HAL_
DMA_ ⚠Abort_ IT - HAL_
DMA_ ⚠Channel Map - HAL_
DMA_ ⚠DeInit - HAL_
DMA_ ⚠GetError - HAL_
DMA_ ⚠GetState - @addtogroup DMA_Exported_Functions_Group3 @{
- HAL_
DMA_ ⚠IRQHandler - HAL_
DMA_ ⚠Init - @addtogroup DMA_Exported_Functions_Group1 @{
- HAL_
DMA_ ⚠Poll ForTransfer - HAL_
DMA_ ⚠Register Callback - HAL_
DMA_ ⚠Start - @addtogroup DMA_Exported_Functions_Group2 @{
- HAL_
DMA_ ⚠Start_ IT - HAL_
DMA_ ⚠UnRegister Callback - HAL_
DeInit ⚠ - HAL_
Delay ⚠ - HAL_
EXTI_ ⚠Clear Config Line - HAL_
EXTI_ ⚠Clear Pending - HAL_
EXTI_ ⚠GenerateSWI - HAL_
EXTI_ ⚠GetConfig Line - HAL_
EXTI_ ⚠GetHandle - HAL_
EXTI_ ⚠GetPending - HAL_
EXTI_ ⚠IRQHandler - @defgroup EXTI_Exported_Functions_Group2 IO operation functions @brief IO operation functions @{
- HAL_
EXTI_ ⚠Register Callback - HAL_
EXTI_ ⚠SetConfig Line - @defgroup EXTI_Exported_Functions_Group1 Configuration functions @brief Configuration functions @{
- HAL_
FLASH_ ⚠EndOf Operation Callback - HAL_
FLASH_ ⚠Erase - HAL_
FLASH_ ⚠Erase_ IT - HAL_
FLASH_ ⚠GetError - @addtogroup FLASH_Exported_Functions_Group3 @{
- HAL_
FLASH_ ⚠IRQHandler - HAL_
FLASH_ ⚠Lock - HAL_
FLASH_ ⚠OBGet Config - HAL_
FLASH_ ⚠OBProgram - HAL_
FLASH_ ⚠OB_ Launch - HAL_
FLASH_ ⚠OB_ Lock - HAL_
FLASH_ ⚠OB_ RDP_ Level Config - HAL_
FLASH_ ⚠OB_ Unlock - HAL_
FLASH_ ⚠Operation Error Callback - HAL_
FLASH_ ⚠Page Program - HAL_
FLASH_ ⚠Page Program_ IT - HAL_
FLASH_ ⚠Program - @addtogroup FLASH_Exported_Functions_Group1 @{
- HAL_
FLASH_ ⚠Program_ IT - HAL_
FLASH_ ⚠Unlock - @addtogroup FLASH_Exported_Functions_Group2 @{
- HAL_
GET_ ⚠ADC_ TSCA L1 - HAL_
GET_ ⚠ADC_ TSCA L2 - HAL_
GPIO_ ⚠DeInit - HAL_
GPIO_ ⚠EXTI_ Callback - HAL_
GPIO_ ⚠EXTI_ IRQHandler - HAL_
GPIO_ ⚠Init - @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions @brief Initialization and Configuration functions @{
- HAL_
GPIO_ ⚠Lock Pin - HAL_
GPIO_ ⚠Read Pin - @defgroup GPIO_Exported_Functions_Group2 IO operation functions @brief IO operation functions @{
- HAL_
GPIO_ ⚠Toggle Pin - HAL_
GPIO_ ⚠Write Pin - HAL_
GetDEVID ⚠ - HAL_
GetHal ⚠Version - HAL_
GetREVID ⚠ - HAL_
GetTick ⚠ - HAL_
GetTick ⚠Freq - HAL_
GetTick ⚠Prio - HAL_
GetUI ⚠Dw0 - HAL_
GetUI ⚠Dw1 - HAL_
GetUI ⚠Dw2 - HAL_
Half ⚠Duplex_ Enable Receiver - HAL_
Half ⚠Duplex_ Enable Transmitter - HAL_
Half ⚠Duplex_ Init - HAL_
I2C_ ⚠Abort Cplt Callback - HAL_
I2C_ ⚠Addr Callback - HAL_
I2C_ ⚠DeInit - HAL_
I2C_ ⚠Disable Listen_ IT - HAL_
I2C_ ⚠ER_ IRQHandler - HAL_
I2C_ ⚠EV_ IRQHandler - @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks @{ / /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA)
- HAL_
I2C_ ⚠Enable Listen_ IT - HAL_
I2C_ ⚠Error Callback - HAL_
I2C_ ⚠GetError - HAL_
I2C_ ⚠GetMode - HAL_
I2C_ ⚠GetState - @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions @{
- HAL_
I2C_ ⚠Init - @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions @{
- HAL_
I2C_ ⚠IsDevice Ready - HAL_
I2C_ ⚠Listen Cplt Callback - HAL_
I2C_ ⚠Master RxCplt Callback - HAL_
I2C_ ⚠Master TxCplt Callback - HAL_
I2C_ ⚠Master_ Abort_ IT - HAL_
I2C_ ⚠Master_ Receive - HAL_
I2C_ ⚠Master_ Receive_ DMA - HAL_
I2C_ ⚠Master_ Receive_ IT - HAL_
I2C_ ⚠Master_ Seq_ Receive_ DMA - HAL_
I2C_ ⚠Master_ Seq_ Receive_ IT - HAL_
I2C_ ⚠Master_ Seq_ Transmit_ DMA - HAL_
I2C_ ⚠Master_ Seq_ Transmit_ IT - HAL_
I2C_ ⚠Master_ Transmit - Blocking mode: Polling
- HAL_
I2C_ ⚠Master_ Transmit_ DMA - Non-Blocking mode: DMA
- HAL_
I2C_ ⚠Master_ Transmit_ IT - Non-Blocking mode: Interrupt
- HAL_
I2C_ ⚠MemRx Cplt Callback - HAL_
I2C_ ⚠MemTx Cplt Callback - HAL_
I2C_ ⚠Mem_ Read - HAL_
I2C_ ⚠Mem_ Read_ DMA - HAL_
I2C_ ⚠Mem_ Read_ IT - HAL_
I2C_ ⚠Mem_ Write - HAL_
I2C_ ⚠Mem_ Write_ DMA - HAL_
I2C_ ⚠Mem_ Write_ IT - HAL_
I2C_ ⚠MspDe Init - HAL_
I2C_ ⚠MspInit - HAL_
I2C_ ⚠Slave RxCplt Callback - HAL_
I2C_ ⚠Slave TxCplt Callback - HAL_
I2C_ ⚠Slave_ Receive - HAL_
I2C_ ⚠Slave_ Receive_ DMA - HAL_
I2C_ ⚠Slave_ Receive_ IT - HAL_
I2C_ ⚠Slave_ Seq_ Receive_ DMA - HAL_
I2C_ ⚠Slave_ Seq_ Receive_ IT - HAL_
I2C_ ⚠Slave_ Seq_ Transmit_ DMA - HAL_
I2C_ ⚠Slave_ Seq_ Transmit_ IT - HAL_
I2C_ ⚠Slave_ Transmit - HAL_
I2C_ ⚠Slave_ Transmit_ DMA - HAL_
I2C_ ⚠Slave_ Transmit_ IT - HAL_
IWDG_ ⚠Init - @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions @{
- HAL_
IWDG_ ⚠Refresh - @defgroup IWDG_Exported_Functions_Group2 IO operation functions @{
- HAL_
IncTick ⚠ - @addtogroup HAL_Exported_Functions_Group2 @{
- HAL_
Init ⚠ - HAL_
Init ⚠Tick - HAL_
LED_ ⚠IRQHandler - HAL_
LED_ ⚠Init - @defgroup LED_Exported_Functions_Group LED operation functions @brief LED operation functions @{
- HAL_
LED_ ⚠Light Cplt Callback - HAL_
LED_ ⚠MspInit - HAL_
LED_ ⚠SetCom Display - HAL_
LPTIM_ ⚠Auto Reload Match Callback - HAL_
LPTIM_ ⚠DeInit - HAL_
LPTIM_ ⚠GetState - HAL_
LPTIM_ ⚠IRQHandler - HAL_
LPTIM_ ⚠Init - @defgroup LPTIM_Exported_Functions LPTIM Exported Functions @{
- HAL_
LPTIM_ ⚠MspDe Init - HAL_
LPTIM_ ⚠MspInit - HAL_
LPTIM_ ⚠Read Auto Reload - HAL_
LPTIM_ ⚠Read Counter - HAL_
LPTIM_ ⚠SetOnce_ Start - HAL_
LPTIM_ ⚠SetOnce_ Start_ IT - HAL_
LPTIM_ ⚠SetOnce_ Stop - HAL_
LPTIM_ ⚠SetOnce_ Stop_ IT - HAL_
MspDe ⚠Init - HAL_
MspInit ⚠ - HAL_
Multi ⚠Processor_ Enter Mute Mode - HAL_
Multi ⚠Processor_ Exit Mute Mode - HAL_
Multi ⚠Processor_ Init - HAL_
NVIC_ ⚠Clear PendingIRQ - HAL_
NVIC_ ⚠DisableIRQ - HAL_
NVIC_ ⚠EnableIRQ - HAL_
NVIC_ ⚠GetPendingIRQ - HAL_
NVIC_ ⚠GetPriority - @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions @brief Cortex control functions @{
- HAL_
NVIC_ ⚠SetPendingIRQ - HAL_
NVIC_ ⚠SetPriority - @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions @brief Initialization and Configuration functions @{
- HAL_
NVIC_ ⚠System Reset - HAL_
PWR_ ⚠ConfigBIAS - HAL_
PWR_ ⚠ConfigPVD - HAL_
PWR_ ⚠Config Stop Mode - HAL_
PWR_ ⚠DeInit - @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions @{
- HAL_
PWR_ ⚠Disable BkUp Access - HAL_
PWR_ ⚠DisablePVD - HAL_
PWR_ ⚠DisableSEV OnPend - HAL_
PWR_ ⚠Disable Sleep OnExit - HAL_
PWR_ ⚠Enable BkUp Access - @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions @{
- HAL_
PWR_ ⚠EnablePVD - HAL_
PWR_ ⚠EnableSEV OnPend - HAL_
PWR_ ⚠Enable Sleep OnExit - HAL_
PWR_ ⚠EnterSLEEP Mode - HAL_
PWR_ ⚠EnterSTOP Mode - HAL_
PWR_ ⚠PVD_ Callback - HAL_
PWR_ ⚠PVD_ IRQHandler - HAL_
RCCEx_ ⚠DisableLSCO - HAL_
RCCEx_ ⚠EnableLSCO - HAL_
RCCEx_ ⚠GetPeriphCLK Config - HAL_
RCCEx_ ⚠GetPeriphCLK Freq - HAL_
RCCEx_ ⚠PeriphCLK Config - @addtogroup RCCEx_Exported_Functions_Group1 @{
- HAL_
RCC_ ⚠ADC_ CLK_ DISABLE - HAL_
RCC_ ⚠ADC_ CLK_ ENABLE - HAL_
RCC_ ⚠ADC_ FORCE_ RESET - HAL_
RCC_ ⚠ADC_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠ADC_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠ADC_ RELEASE_ RESET - HAL_
RCC_ ⚠AHB_ FORCE_ RESET - HAL_
RCC_ ⚠AHB_ RELEASE_ RESET - HAL_
RCC_ ⚠APB1_ FORCE_ RESET - HAL_
RCC_ ⚠APB1_ RELEASE_ RESET - HAL_
RCC_ ⚠APB2_ FORCE_ RESET - HAL_
RCC_ ⚠APB2_ RELEASE_ RESET - HAL_
RCC_ ⚠BACKUPRESET_ FORCE - HAL_
RCC_ ⚠BACKUPRESET_ RELEASE - HAL_
RCC_ ⚠CLEAR_ RESET_ FLAGS - HAL_
RCC_ ⚠COMP1_ CLK_ DISABLE - HAL_
RCC_ ⚠COMP1_ CLK_ ENABLE - HAL_
RCC_ ⚠COMP1_ FORCE_ RESET - HAL_
RCC_ ⚠COMP1_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠COMP1_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠COMP1_ RELEASE_ RESET - HAL_
RCC_ ⚠COMP2_ CLK_ DISABLE - HAL_
RCC_ ⚠COMP2_ CLK_ ENABLE - HAL_
RCC_ ⚠COMP2_ FORCE_ RESET - HAL_
RCC_ ⚠COMP2_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠COMP2_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠COMP2_ RELEASE_ RESET - HAL_
RCC_ ⚠CRC_ CLK_ DISABLE - HAL_
RCC_ ⚠CRC_ CLK_ ENABLE - HAL_
RCC_ ⚠CRC_ FORCE_ RESET - HAL_
RCC_ ⚠CRC_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠CRC_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠CRC_ RELEASE_ RESET - HAL_
RCC_ ⚠CSSCallback - HAL_
RCC_ ⚠Clock Config - HAL_
RCC_ ⚠DBGMCU_ CLK_ DISABLE - HAL_
RCC_ ⚠DBGMCU_ CLK_ ENABLE - HAL_
RCC_ ⚠DBGMCU_ FORCE_ RESET - HAL_
RCC_ ⚠DBGMCU_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠DBGMCU_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠DBGMCU_ RELEASE_ RESET - HAL_
RCC_ ⚠DMA_ CLK_ DISABLE - HAL_
RCC_ ⚠DMA_ CLK_ ENABLE - HAL_
RCC_ ⚠DMA_ FORCE_ RESET - HAL_
RCC_ ⚠DMA_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠DMA_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠DMA_ RELEASE_ RESET - HAL_
RCC_ ⚠DeInit - @addtogroup RCC_Exported_Functions_Group1 @{
- HAL_
RCC_ ⚠DisableLSECSS - HAL_
RCC_ ⚠EnableCSS - HAL_
RCC_ ⚠EnableLSECSS - HAL_
RCC_ ⚠FLASH_ CLK_ DISABLE - HAL_
RCC_ ⚠FLASH_ CLK_ ENABLE - HAL_
RCC_ ⚠FLASH_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠FLASH_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠GET_ PLL_ OSCSOURCE - HAL_
RCC_ ⚠GET_ RTC_ SOURCE - HAL_
RCC_ ⚠GET_ SYSCLK_ SOURCE - HAL_
RCC_ ⚠GPIOA_ CLK_ DISABLE - HAL_
RCC_ ⚠GPIOA_ CLK_ ENABLE - HAL_
RCC_ ⚠GPIOA_ FORCE_ RESET - HAL_
RCC_ ⚠GPIOA_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠GPIOA_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠GPIOA_ RELEASE_ RESET - HAL_
RCC_ ⚠GPIOB_ CLK_ DISABLE - HAL_
RCC_ ⚠GPIOB_ CLK_ ENABLE - HAL_
RCC_ ⚠GPIOB_ FORCE_ RESET - HAL_
RCC_ ⚠GPIOB_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠GPIOB_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠GPIOB_ RELEASE_ RESET - HAL_
RCC_ ⚠GPIOF_ CLK_ DISABLE - HAL_
RCC_ ⚠GPIOF_ CLK_ ENABLE - HAL_
RCC_ ⚠GPIOF_ FORCE_ RESET - HAL_
RCC_ ⚠GPIOF_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠GPIOF_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠GPIOF_ RELEASE_ RESET - HAL_
RCC_ ⚠GetClock Config - HAL_
RCC_ ⚠GetHCLK Freq - HAL_
RCC_ ⚠GetOsc Config - HAL_
RCC_ ⚠GetPCL K1Freq - HAL_
RCC_ ⚠GetSys Clock Freq - HAL_
RCC_ ⚠HSI_ DISABLE - HAL_
RCC_ ⚠HSI_ ENABLE - HAL_
RCC_ ⚠I2C1_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠I2C_ CLK_ DISABLE - HAL_
RCC_ ⚠I2C_ CLK_ ENABLE - HAL_
RCC_ ⚠I2C_ FORCE_ RESET - HAL_
RCC_ ⚠I2C_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠I2C_ RELEASE_ RESET - HAL_
RCC_ ⚠IOP_ FORCE_ RESET - HAL_
RCC_ ⚠IOP_ RELEASE_ RESET - HAL_
RCC_ ⚠LED_ CLK_ DISABLE - HAL_
RCC_ ⚠LED_ CLK_ ENABLE - HAL_
RCC_ ⚠LED_ FORCE_ RESET - HAL_
RCC_ ⚠LED_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠LED_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠LED_ RELEASE_ RESET - HAL_
RCC_ ⚠LPTIM_ CLK_ DISABLE - HAL_
RCC_ ⚠LPTIM_ CLK_ ENABLE - HAL_
RCC_ ⚠LPTIM_ FORCE_ RESET - HAL_
RCC_ ⚠LPTIM_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠LPTIM_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠LPTIM_ RELEASE_ RESET - HAL_
RCC_ ⚠LSECSS Callback - HAL_
RCC_ ⚠LSI_ DISABLE - HAL_
RCC_ ⚠LSI_ ENABLE - HAL_
RCC_ ⚠MCOConfig - @addtogroup RCC_Exported_Functions_Group2 @{
- HAL_
RCC_ ⚠NMI_ IRQHandler - HAL_
RCC_ ⚠OscConfig - HAL_
RCC_ ⚠PLL_ DISABLE - HAL_
RCC_ ⚠PLL_ ENABLE - HAL_
RCC_ ⚠PWR_ CLK_ DISABLE - HAL_
RCC_ ⚠PWR_ CLK_ ENABLE - HAL_
RCC_ ⚠PWR_ FORCE_ RESET - HAL_
RCC_ ⚠PWR_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠PWR_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠PWR_ RELEASE_ RESET - HAL_
RCC_ ⚠RTCAPB_ CLK_ DISABLE - HAL_
RCC_ ⚠RTCAPB_ CLK_ ENABLE - HAL_
RCC_ ⚠RTCAPB_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠RTCAPB_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠RTC_ DISABLE - HAL_
RCC_ ⚠RTC_ ENABLE - HAL_
RCC_ ⚠SPI1_ CLK_ DISABLE - HAL_
RCC_ ⚠SPI1_ CLK_ ENABLE - HAL_
RCC_ ⚠SPI1_ FORCE_ RESET - HAL_
RCC_ ⚠SPI1_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠SPI1_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠SPI1_ RELEASE_ RESET - HAL_
RCC_ ⚠SPI2_ CLK_ DISABLE - HAL_
RCC_ ⚠SPI2_ CLK_ ENABLE - HAL_
RCC_ ⚠SPI2_ FORCE_ RESET - HAL_
RCC_ ⚠SPI2_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠SPI2_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠SPI2_ RELEASE_ RESET - HAL_
RCC_ ⚠SRAM_ CLK_ DISABLE - HAL_
RCC_ ⚠SRAM_ CLK_ ENABLE - HAL_
RCC_ ⚠SYSCFG_ CLK_ DISABLE - HAL_
RCC_ ⚠SYSCFG_ CLK_ ENABLE - HAL_
RCC_ ⚠SYSCFG_ FORCE_ RESET - HAL_
RCC_ ⚠SYSCFG_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠SYSCFG_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠SYSCFG_ RELEASE_ RESET - HAL_
RCC_ ⚠TIM1_ CLK_ DISABLE - HAL_
RCC_ ⚠TIM1_ CLK_ ENABLE - HAL_
RCC_ ⚠TIM1_ FORCE_ RESET - HAL_
RCC_ ⚠TIM1_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠TIM1_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠TIM1_ RELEASE_ RESET - HAL_
RCC_ ⚠TIM3_ CLK_ DISABLE - HAL_
RCC_ ⚠TIM3_ CLK_ ENABLE - HAL_
RCC_ ⚠TIM3_ FORCE_ RESET - HAL_
RCC_ ⚠TIM3_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠TIM3_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠TIM3_ RELEASE_ RESET - HAL_
RCC_ ⚠TIM14_ CLK_ DISABLE - HAL_
RCC_ ⚠TIM14_ CLK_ ENABLE - HAL_
RCC_ ⚠TIM14_ FORCE_ RESET - HAL_
RCC_ ⚠TIM14_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠TIM14_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠TIM14_ RELEASE_ RESET - HAL_
RCC_ ⚠TIM16_ CLK_ DISABLE - HAL_
RCC_ ⚠TIM16_ CLK_ ENABLE - HAL_
RCC_ ⚠TIM16_ FORCE_ RESET - HAL_
RCC_ ⚠TIM16_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠TIM16_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠TIM16_ RELEASE_ RESET - HAL_
RCC_ ⚠TIM17_ CLK_ DISABLE - HAL_
RCC_ ⚠TIM17_ CLK_ ENABLE - HAL_
RCC_ ⚠TIM17_ FORCE_ RESET - HAL_
RCC_ ⚠TIM17_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠TIM17_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠TIM17_ RELEASE_ RESET - HAL_
RCC_ ⚠USAR T1_ CLK_ DISABLE - HAL_
RCC_ ⚠USAR T1_ CLK_ ENABLE - HAL_
RCC_ ⚠USAR T1_ FORCE_ RESET - HAL_
RCC_ ⚠USAR T1_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠USAR T1_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠USAR T1_ RELEASE_ RESET - HAL_
RCC_ ⚠USAR T2_ CLK_ DISABLE - HAL_
RCC_ ⚠USAR T2_ CLK_ ENABLE - HAL_
RCC_ ⚠USAR T2_ FORCE_ RESET - HAL_
RCC_ ⚠USAR T2_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠USAR T2_ IS_ CLK_ ENABLED - HAL_
RCC_ ⚠USAR T2_ RELEASE_ RESET - HAL_
RCC_ ⚠WWDG_ CLK_ ENABLE - HAL_
RCC_ ⚠WWDG_ IS_ CLK_ DISABLED - HAL_
RCC_ ⚠WWDG_ IS_ CLK_ ENABLED - HAL_
RTCEx_ ⚠Deactivate Second - HAL_
RTCEx_ ⚠RTCEvent Callback - HAL_
RTCEx_ ⚠RTCEvent Error Callback - HAL_
RTCEx_ ⚠RTCIRQ Handler - HAL_
RTCEx_ ⚠SetSecond_ IT - @addtogroup RTCEx_Exported_Functions_Group2 @{
- HAL_
RTCEx_ ⚠SetSmooth Calib - @addtogroup RTCEx_Exported_Functions_Group3 @{
- HAL_
RTC_ ⚠AlarmA Event Callback - HAL_
RTC_ ⚠AlarmIRQ Handler - HAL_
RTC_ ⚠DeInit - HAL_
RTC_ ⚠Deactivate Alarm - HAL_
RTC_ ⚠GetAlarm - HAL_
RTC_ ⚠GetDate - HAL_
RTC_ ⚠GetState - @addtogroup RTC_Exported_Functions_Group4 @{
- HAL_
RTC_ ⚠GetTime - HAL_
RTC_ ⚠Init - @addtogroup RTC_Exported_Functions_Group1 @{
- HAL_
RTC_ ⚠MspDe Init - HAL_
RTC_ ⚠MspInit - HAL_
RTC_ ⚠Poll ForAlarmA Event - HAL_
RTC_ ⚠SetAlarm - @addtogroup RTC_Exported_Functions_Group3 @{
- HAL_
RTC_ ⚠SetAlarm_ IT - HAL_
RTC_ ⚠SetDate - HAL_
RTC_ ⚠SetTime - @addtogroup RTC_Exported_Functions_Group2 @{
- HAL_
RTC_ ⚠Wait ForSynchro - @addtogroup RTC_Exported_Functions_Group5 @{
- HAL_
Resume ⚠Tick - HAL_
SPI_ ⚠Abort - HAL_
SPI_ ⚠Abort Cplt Callback - HAL_
SPI_ ⚠Abort_ IT - HAL_
SPI_ ⚠DMAPause - HAL_
SPI_ ⚠DMAResume - HAL_
SPI_ ⚠DMAStop - HAL_
SPI_ ⚠DeInit - HAL_
SPI_ ⚠Error Callback - HAL_
SPI_ ⚠GetError - HAL_
SPI_ ⚠GetState - @addtogroup SPI_Exported_Functions_Group3 @{
- HAL_
SPI_ ⚠IRQHandler - HAL_
SPI_ ⚠Init - @addtogroup SPI_Exported_Functions_Group1 @{
- HAL_
SPI_ ⚠MspDe Init - HAL_
SPI_ ⚠MspInit - HAL_
SPI_ ⚠Receive - HAL_
SPI_ ⚠Receive_ DMA - HAL_
SPI_ ⚠Receive_ IT - HAL_
SPI_ ⚠RxCplt Callback - HAL_
SPI_ ⚠RxHalf Cplt Callback - HAL_
SPI_ ⚠Transmit - @addtogroup SPI_Exported_Functions_Group2 @{
- HAL_
SPI_ ⚠Transmit Receive - HAL_
SPI_ ⚠Transmit Receive_ DMA - HAL_
SPI_ ⚠Transmit Receive_ IT - HAL_
SPI_ ⚠Transmit_ DMA - HAL_
SPI_ ⚠Transmit_ IT - HAL_
SPI_ ⚠TxCplt Callback - HAL_
SPI_ ⚠TxHalf Cplt Callback - HAL_
SPI_ ⚠TxRx Cplt Callback - HAL_
SPI_ ⚠TxRx Half Cplt Callback - HAL_
SYSCFG_ ⚠DMA_ Req - HAL_
SYSTICK_ ⚠CLKSource Config - HAL_
SYSTICK_ ⚠Callback - HAL_
SYSTICK_ ⚠Config - HAL_
SYSTICK_ ⚠IRQHandler - HAL_
SetTick ⚠Freq - HAL_
Suspend ⚠Tick - HAL_
TIMEx_ ⚠Break Callback - HAL_
TIMEx_ ⚠Commut Callback - @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions @brief Extended Callbacks functions @{
- HAL_
TIMEx_ ⚠Commut Half Cplt Callback - HAL_
TIMEx_ ⚠Config Break Dead Time - HAL_
TIMEx_ ⚠Config Commut Event - @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions @brief Peripheral Control functions @{
- HAL_
TIMEx_ ⚠Config Commut Event_ DMA - HAL_
TIMEx_ ⚠Config Commut Event_ IT - HAL_
TIMEx_ ⚠Hall Sensor_ DeInit - HAL_
TIMEx_ ⚠Hall Sensor_ GetState - @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions @brief Extended Peripheral State functions @{
- HAL_
TIMEx_ ⚠Hall Sensor_ Init - @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions @brief Timer Hall Sensor functions @{
- HAL_
TIMEx_ ⚠Hall Sensor_ MspDe Init - HAL_
TIMEx_ ⚠Hall Sensor_ MspInit - HAL_
TIMEx_ ⚠Hall Sensor_ Start - HAL_
TIMEx_ ⚠Hall Sensor_ Start_ DMA - HAL_
TIMEx_ ⚠Hall Sensor_ Start_ IT - HAL_
TIMEx_ ⚠Hall Sensor_ Stop - HAL_
TIMEx_ ⚠Hall Sensor_ Stop_ DMA - HAL_
TIMEx_ ⚠Hall Sensor_ Stop_ IT - HAL_
TIMEx_ ⚠Master Config Synchronization - HAL_
TIMEx_ ⚠OCN_ Start - @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions @brief Timer Complementary Output Compare functions @{
- HAL_
TIMEx_ ⚠OCN_ Start_ DMA - HAL_
TIMEx_ ⚠OCN_ Start_ IT - HAL_
TIMEx_ ⚠OCN_ Stop - HAL_
TIMEx_ ⚠OCN_ Stop_ DMA - HAL_
TIMEx_ ⚠OCN_ Stop_ IT - HAL_
TIMEx_ ⚠OnePulseN_ Start - @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions @brief Timer Complementary One Pulse functions @{
- HAL_
TIMEx_ ⚠OnePulseN_ Start_ IT - HAL_
TIMEx_ ⚠OnePulseN_ Stop - HAL_
TIMEx_ ⚠OnePulseN_ Stop_ IT - HAL_
TIMEx_ ⚠PWMN_ Start - @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions @brief Timer Complementary PWM functions @{
- HAL_
TIMEx_ ⚠PWMN_ Start_ DMA - HAL_
TIMEx_ ⚠PWMN_ Start_ IT - HAL_
TIMEx_ ⚠PWMN_ Stop - HAL_
TIMEx_ ⚠PWMN_ Stop_ DMA - HAL_
TIMEx_ ⚠PWMN_ Stop_ IT - HAL_
TIMEx_ ⚠Remap Config - HAL_
TIM_ ⚠Base_ DeInit - HAL_
TIM_ ⚠Base_ GetState - @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions @brief Peripheral State functions @{
- HAL_
TIM_ ⚠Base_ Init - @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions @brief Time Base functions @{
- HAL_
TIM_ ⚠Base_ MspDe Init - HAL_
TIM_ ⚠Base_ MspInit - HAL_
TIM_ ⚠Base_ Start - HAL_
TIM_ ⚠Base_ Start_ DMA - HAL_
TIM_ ⚠Base_ Start_ IT - HAL_
TIM_ ⚠Base_ Stop - HAL_
TIM_ ⚠Base_ Stop_ DMA - HAL_
TIM_ ⚠Base_ Stop_ IT - HAL_
TIM_ ⚠Config Clock Source - HAL_
TIM_ ⚠ConfigO Cref Clear - HAL_
TIM_ ⚠ConfigT I1Input - HAL_
TIM_ ⚠DMABurst_ Multi Read Start - HAL_
TIM_ ⚠DMABurst_ Multi Write Start - HAL_
TIM_ ⚠DMABurst_ Read Start - HAL_
TIM_ ⚠DMABurst_ Read Stop - HAL_
TIM_ ⚠DMABurst_ Write Start - HAL_
TIM_ ⚠DMABurst_ Write Stop - HAL_
TIM_ ⚠Encoder_ DeInit - HAL_
TIM_ ⚠Encoder_ GetState - HAL_
TIM_ ⚠Encoder_ Init - @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions @brief TIM Encoder functions @{
- HAL_
TIM_ ⚠Encoder_ MspDe Init - HAL_
TIM_ ⚠Encoder_ MspInit - HAL_
TIM_ ⚠Encoder_ Start - HAL_
TIM_ ⚠Encoder_ Start_ DMA - HAL_
TIM_ ⚠Encoder_ Start_ IT - HAL_
TIM_ ⚠Encoder_ Stop - HAL_
TIM_ ⚠Encoder_ Stop_ DMA - HAL_
TIM_ ⚠Encoder_ Stop_ IT - HAL_
TIM_ ⚠Error Callback - HAL_
TIM_ ⚠Generate Event - HAL_
TIM_ ⚠IC_ Capture Callback - HAL_
TIM_ ⚠IC_ Capture Half Cplt Callback - HAL_
TIM_ ⚠IC_ Config Channel - HAL_
TIM_ ⚠IC_ DeInit - HAL_
TIM_ ⚠IC_ GetState - HAL_
TIM_ ⚠IC_ Init - @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions @brief TIM Input Capture functions @{
- HAL_
TIM_ ⚠IC_ MspDe Init - HAL_
TIM_ ⚠IC_ MspInit - HAL_
TIM_ ⚠IC_ Start - HAL_
TIM_ ⚠IC_ Start_ DMA - HAL_
TIM_ ⚠IC_ Start_ IT - HAL_
TIM_ ⚠IC_ Stop - HAL_
TIM_ ⚠IC_ Stop_ DMA - HAL_
TIM_ ⚠IC_ Stop_ IT - HAL_
TIM_ ⚠IRQHandler - @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management @brief IRQ handler management @{
- HAL_
TIM_ ⚠OC_ Config Channel - @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions @brief Peripheral Control functions @{
- HAL_
TIM_ ⚠OC_ DeInit - HAL_
TIM_ ⚠OC_ Delay Elapsed Callback - HAL_
TIM_ ⚠OC_ GetState - HAL_
TIM_ ⚠OC_ Init - @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions @brief TIM Output Compare functions @{
- HAL_
TIM_ ⚠OC_ MspDe Init - HAL_
TIM_ ⚠OC_ MspInit - HAL_
TIM_ ⚠OC_ Start - HAL_
TIM_ ⚠OC_ Start_ DMA - HAL_
TIM_ ⚠OC_ Start_ IT - HAL_
TIM_ ⚠OC_ Stop - HAL_
TIM_ ⚠OC_ Stop_ DMA - HAL_
TIM_ ⚠OC_ Stop_ IT - HAL_
TIM_ ⚠OnePulse_ Config Channel - HAL_
TIM_ ⚠OnePulse_ DeInit - HAL_
TIM_ ⚠OnePulse_ GetState - HAL_
TIM_ ⚠OnePulse_ Init - @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions @brief TIM One Pulse functions @{
- HAL_
TIM_ ⚠OnePulse_ MspDe Init - HAL_
TIM_ ⚠OnePulse_ MspInit - HAL_
TIM_ ⚠OnePulse_ Start - HAL_
TIM_ ⚠OnePulse_ Start_ IT - HAL_
TIM_ ⚠OnePulse_ Stop - HAL_
TIM_ ⚠OnePulse_ Stop_ IT - HAL_
TIM_ ⚠PWM_ Config Channel - HAL_
TIM_ ⚠PWM_ DeInit - HAL_
TIM_ ⚠PWM_ GetState - HAL_
TIM_ ⚠PWM_ Init - @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions @brief TIM PWM functions @{
- HAL_
TIM_ ⚠PWM_ MspDe Init - HAL_
TIM_ ⚠PWM_ MspInit - HAL_
TIM_ ⚠PWM_ Pulse Finished Callback - HAL_
TIM_ ⚠PWM_ Pulse Finished Half Cplt Callback - HAL_
TIM_ ⚠PWM_ Start - HAL_
TIM_ ⚠PWM_ Start_ DMA - HAL_
TIM_ ⚠PWM_ Start_ IT - HAL_
TIM_ ⚠PWM_ Stop - HAL_
TIM_ ⚠PWM_ Stop_ DMA - HAL_
TIM_ ⚠PWM_ Stop_ IT - HAL_
TIM_ ⚠Period Elapsed Callback - @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions @brief TIM Callbacks functions @{
- HAL_
TIM_ ⚠Period Elapsed Half Cplt Callback - HAL_
TIM_ ⚠Read Captured Value - HAL_
TIM_ ⚠Slave Config Synchro - HAL_
TIM_ ⚠Slave Config Synchro_ IT - HAL_
TIM_ ⚠Trigger Callback - HAL_
TIM_ ⚠Trigger Half Cplt Callback - HAL_
UART_ ⚠Abort - HAL_
UART_ ⚠Abort Cplt Callback - HAL_
UART_ ⚠Abort Receive - HAL_
UART_ ⚠Abort Receive Cplt Callback - HAL_
UART_ ⚠Abort Receive_ IT - HAL_
UART_ ⚠Abort Transmit - HAL_
UART_ ⚠Abort Transmit Cplt Callback - HAL_
UART_ ⚠Abort Transmit_ IT - HAL_
UART_ ⚠Abort_ IT - HAL_
UART_ ⚠DMAPause - HAL_
UART_ ⚠DMAResume - HAL_
UART_ ⚠DMAStop - HAL_
UART_ ⚠DeInit - HAL_
UART_ ⚠Error Callback - HAL_
UART_ ⚠GetError - HAL_
UART_ ⚠GetState - @addtogroup UART_Exported_Functions_Group4 @{
- HAL_
UART_ ⚠IRQHandler - HAL_
UART_ ⚠Idle Frame Detect Cplt Callback - HAL_
UART_ ⚠Init - @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions @{
- HAL_
UART_ ⚠MspDe Init - HAL_
UART_ ⚠MspInit - HAL_
UART_ ⚠Receive - HAL_
UART_ ⚠Receive_ DMA - HAL_
UART_ ⚠Receive_ IT - HAL_
UART_ ⚠RxCplt Callback - HAL_
UART_ ⚠RxHalf Cplt Callback - HAL_
UART_ ⚠Send Break - @addtogroup UART_Exported_Functions_Group3 @{
- HAL_
UART_ ⚠Transmit - @addtogroup UART_Exported_Functions_Group IO operation functions @{
- HAL_
UART_ ⚠Transmit_ DMA - HAL_
UART_ ⚠Transmit_ IT - HAL_
UART_ ⚠TxCplt Callback - HAL_
UART_ ⚠TxHalf Cplt Callback - HAL_
WWDG_ ⚠Early Wakeup Callback - HAL_
WWDG_ ⚠IRQHandler - HAL_
WWDG_ ⚠Init - @addtogroup WWDG_Exported_Functions_Group1 @{
- HAL_
WWDG_ ⚠MspInit - HAL_
WWDG_ ⚠Refresh - @addtogroup WWDG_Exported_Functions_Group2 @{
- RCC_
GET_ ⚠HSICALIBRATION_ 4MHz - RCC_
GET_ ⚠HSICALIBRATION_ 8MHz - RCC_
GET_ ⚠HSICALIBRATION_ 16MHz - RCC_
GET_ ⚠HSICALIBRATION_ 22p12M Hz - RCC_
GET_ ⚠HSICALIBRATION_ 24MHz - System
Core ⚠Clock Update - System
Init ⚠ - @addtogroup PY32F0xx_System_Exported_Functions @{
- TIMEx_
DMACommutation ⚠Cplt - TIMEx_
DMACommutation ⚠Half Cplt - TIM_
Base_ ⚠SetConfig - @defgroup TIM_Private_Functions TIM Private Functions @{
- TIM_
CCxChannel ⚠Cmd - TIM_
DMACapture ⚠Cplt - TIM_
DMACapture ⚠Half Cplt - TIM_
DMADelay ⚠Pulse Cplt - TIM_
DMADelay ⚠Pulse Half Cplt - TIM_
DMAError ⚠ - TIM_
ETR_ ⚠SetConfig - TIM_
OC2_ ⚠SetConfig - TIM_
TI1_ ⚠SetConfig
Type Aliases§
- ADC_
Handle Type Def - @brief ADC handle Structure definition
- DMA_
Handle Type Def - @brief DMA handle Structure definition
- EXTI_
CallbackID Type Def - @defgroup EXTI_Exported_Types EXTI Exported Types @{
- Error
Status - Flag
Status - @brief Exported_types
- Functional
State - GPIO_
PinState - @brief GPIO Bit SET and Bit RESET enumeration
- HAL_
CRC_ State Type Def - @brief CRC HAL State Structure definition
- HAL_
DMA_ CallbackID Type Def - @brief HAL DMA Callback ID structure definition
- HAL_
DMA_ Level Complete Type Def - @brief HAL DMA Error Code structure definition
- HAL_
DMA_ State Type Def - @brief HAL DMA State structures definition
- HAL_
I2C_ Mode Type Def - @defgroup HAL_mode_structure_definition HAL mode structure definition @brief HAL Mode structure definition @note HAL I2C Mode value coding follow below described bitmap :\n b7 (not used)\n x : Should be set to 0\n b6\n 0 : None\n 1 : Memory (HAL I2C communication is in Memory Mode)\n b5\n 0 : None\n 1 : Slave (HAL I2C communication is in Slave Mode)\n b4\n 0 : None\n 1 : Master (HAL I2C communication is in Master Mode)\n b3-b2-b1-b0 (not used)\n xxxx : Should be set to 0000 @{
- HAL_
I2C_ State Type Def - @defgroup HAL_state_structure_definition HAL state structure definition @brief HAL State structure definition @note HAL I2C State value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : Abort (Abort user request on going) 10 : Timeout 11 : Error b5 Peripheral initilisation status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called) b4 (not used) x : Should be set to 0 b3 0 : Ready or Busy (No Listen mode ongoing) 1 : Listen (Peripheral in Address Listen Mode) b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing) @{
- HAL_
LED_ State Type Def - @brief HAL LED State structures definition
- HAL_
LPTIM_ State Type Def - @brief HAL LPTIM State structure definition
- HAL_
Lock Type Def - @brief HAL Lock structures definition
- HAL_
RTCState Type Def - @brief HAL State structures definition
- HAL_
SPI_ State Type Def - @brief HAL SPI State structure definition
- HAL_
Status Type Def - @brief HAL Status structures definition
- HAL_
TIM_ Active Channel - @brief HAL Active channel structures definition
- HAL_
TIM_ State Type Def - @brief HAL State structures definition
- HAL_
Tick Freq Type Def - @defgroup HAL_TICK_FREQ Tick Frequency @{
- HAL_
UART_ State Type Def - @brief HAL UART State structures definition @note HAL UART State value is a combination of 2 different substates: gState and RxState. - gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing) - RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
- I2C_
Handle Type Def - @defgroup I2C_handle_Structure_definition I2C handle Structure definition @brief I2C handle Structure definition @{
- IRQn_
Type - SPI_
Handle Type Def - @brief SPI handle Structure definition
- UART_
Handle Type Def - @brief UART handle Structure definition
- int_
fast8_ t - int_
fast16_ t - int_
fast32_ t - int_
fast64_ t - int_
least8_ t - int_
least16_ t - int_
least32_ t - int_
least64_ t - intmax_
t - uint_
fast8_ t - uint_
fast16_ t - uint_
fast32_ t - uint_
fast64_ t - uint_
least8_ t - uint_
least16_ t - uint_
least32_ t - uint_
least64_ t - uintmax_
t
Unions§
- APSR_
Type - \brief Union type to access the Application Program Status Register (APSR).
- CONTROL_
Type - \brief Union type to access the Control Registers (CONTROL).
- IPSR_
Type - \brief Union type to access the Interrupt Program Status Register (IPSR).
- xPSR_
Type - \brief Union type to access the Special-Purpose Program Status Registers (xPSR).