Crate py32csdk_hal_sys

Source

Re-exports§

pub use self::FlagStatus as ITStatus;

Modules§

interrupts

Structs§

ADC_AnalogWDGConfTypeDef
@brief Structure definition of ADC analog watchdog @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group.
ADC_ChannelConfTypeDef
@brief Structure definition of ADC channel for regular group @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC state can be either: - For all parameters: ADC disabled or enabled without conversion on going on regular group. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
ADC_Common_TypeDef
ADC_InitTypeDef
@brief Structure definition of ADC initialization and regular group @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. ADC state can be either: - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter ‘ClockPrescaler’) - For all parameters except ‘ClockPrescaler’ and ‘resolution’: ADC enabled without conversion on going on regular group. If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
ADC_TypeDef
@brief Analog to Digital Converter
APSR_Type__bindgen_ty_1
COMP_Common_TypeDef
COMP_TypeDef
@brief Comparator
CONTROL_Type__bindgen_ty_1
CRC_HandleTypeDef
@brief CRC Handle Structure definition
CRC_TypeDef
@brief CRC calculation unit
DBGMCU_TypeDef
@brief Debug MCU
DMA_Channel_TypeDef
DMA_InitTypeDef
@brief DMA Configuration Structure definition
DMA_TypeDef
@brief DMA Controller
EXTI_ConfigTypeDef
@brief EXTI Configuration structure definition
EXTI_HandleTypeDef
@brief EXTI Handle structure definition
EXTI_TypeDef
@brief Asynch Interrupt/Event Controller (EXTI)
FLASH_EraseInitTypeDef
@brief FLASH Erase structure definition
FLASH_OBProgramInitTypeDef
@brief FLASH Option Bytes PROGRAM structure definition
FLASH_ProcessTypeDef
@brief FLASH handle Structure definition
FLASH_TypeDef
@brief FLASH Registers
GPIO_InitTypeDef
@defgroup GPIO_Exported_Types GPIO Exported Types @{ / /** @brief GPIO Init structure definition
GPIO_TypeDef
@brief General Purpose I/O
I2C_InitTypeDef
@defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition @brief I2C Configuration Structure definition @{
I2C_TypeDef
@brief Inter-integrated Circuit Interface
IPSR_Type__bindgen_ty_1
IWDG_HandleTypeDef
@brief IWDG Handle Structure definition
IWDG_InitTypeDef
@brief IWDG Init structure definition
IWDG_TypeDef
@brief Independent WATCHDOG
LED_HandleTypeDef
LED_InitTypeDef
@brief LED Init Structure definition
LED_TypeDef
LPTIM_HandleTypeDef
LPTIM_InitTypeDef
@brief LPTIM Initialization Structure definition
LPTIM_TypeDef
@brief LPTIMER
NVIC_Type
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
OB_TypeDef
@brief Option Bytes
PWR_BIASConfigTypeDef
@brief PWR BIAS configuration structure definition
PWR_PVDTypeDef
@brief PWR PVD configuration structure definition
PWR_StopModeConfigTypeDef
@brief PWR Stop configuration structure definition
PWR_TypeDef
@brief Power Control
RCC_ClkInitTypeDef
@brief RCC System, AHB and APB busses clock configuration structure definition
RCC_OscInitTypeDef
@brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
RCC_PLLInitTypeDef
@brief RCC PLL configuration structure definition
RCC_PeriphCLKInitTypeDef
@brief RCC extended clocks structure definition
RCC_TypeDef
@brief Reset and Clock Control
RTC_AlarmTypeDef
@brief RTC Alarm structure definition
RTC_DateTypeDef
@brief RTC Date structure definition
RTC_HandleTypeDef
RTC_InitTypeDef
@brief RTC Configuration Structure definition
RTC_TimeTypeDef
@defgroup RTC_Exported_Types RTC Exported Types @{ / /** @brief RTC Time structure definition
RTC_TypeDef
@brief Real-Time Clock
SCB_Type
\brief Structure type to access the System Control Block (SCB).
SPI_InitTypeDef
@brief SPI Configuration Structure definition
SPI_TypeDef
@brief Serial Peripheral Interface
SYSCFG_TypeDef
@brief System configuration controller
SysTick_Type
\brief Structure type to access the System Timer (SysTick).
TIM_Base_InitTypeDef
@brief TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef
@brief TIM Break input(s) and Dead time configuration Structure definition @note 2 break inputs can be configured (BKIN and BKIN2) with configurable filter and polarity.
TIM_ClearInputConfigTypeDef
@brief TIM Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef
@brief Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef
@brief TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef
@brief TIM Hall sensor Configuration Structure definition
TIM_HandleTypeDef
TIM_IC_InitTypeDef
@brief TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef
@brief TIM Master configuration Structure definition
TIM_OC_InitTypeDef
@brief TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef
@brief TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef
@brief TIM Slave configuration Structure definition
TIM_TypeDef
@brief TIM
UART_AdvFeatureInitTypeDef
UART_InitTypeDef
@brief UART Init Structure definition
USART_TypeDef
@brief Universal Synchronous Asynchronous Receiver Transmitter
WWDG_HandleTypeDef
WWDG_InitTypeDef
@brief WWDG Init structure definition
WWDG_TypeDef
@brief Window WATCHDOG
__ADC_HandleTypeDef
@brief ADC handle Structure definition
__BindgenBitfieldUnit
__DMA_HandleTypeDef
@brief DMA handle Structure definition
__I2C_HandleTypeDef
@defgroup I2C_handle_Structure_definition I2C handle Structure definition @brief I2C handle Structure definition @{
__SPI_HandleTypeDef
@brief SPI handle Structure definition
__UART_HandleTypeDef
@brief UART handle Structure definition
xPSR_Type__bindgen_ty_1

Constants§

ADC
ADC1
ADC1_2_EXTERNALTRIG_T1_CC4
ADC1_2_EXTERNALTRIG_T1_TRGO
ADC1_2_EXTERNALTRIG_T3_TRGO
ADC1_BASE
ADC1_COMMON
ADC_ANALOGWATCHDOG_ALL_REG
ADC_ANALOGWATCHDOG_NONE
ADC_ANALOGWATCHDOG_SINGLE_REG
ADC_AWD_EVENT
ADC_BASE
ADC_CALIBSAMPLETIME_1CYCLE
ADC_CALIBSAMPLETIME_2CYCLES
ADC_CALIBSAMPLETIME_4CYCLES
ADC_CALIBSAMPLETIME_8CYCLES
ADC_CALIBSELECTION_OFFSET_LINEARITY
ADC_CALIBSELECTION_ONLYOFFSET
ADC_CALIBSTATUS_FAIL
ADC_CALIBSTATUS_INVALID
ADC_CALIBSTATUS_ONGOING
ADC_CALIBSTATUS_SUCCESS
ADC_CCR_ALL
ADC_CCR_TSEN
ADC_CCR_TSEN_Msk
ADC_CCR_TSEN_Pos
ADC_CCR_VREFEN
ADC_CCR_VREFEN_Msk
ADC_CCR_VREFEN_Pos
ADC_CCSR_CALFAIL
ADC_CCSR_CALFAIL_Msk
ADC_CCSR_CALFAIL_Pos
ADC_CCSR_CALON
ADC_CCSR_CALON_Msk
ADC_CCSR_CALON_Pos
ADC_CCSR_CALSEL
ADC_CCSR_CALSEL_Msk
ADC_CCSR_CALSEL_Pos
ADC_CCSR_CALSMP
ADC_CCSR_CALSMP_0
ADC_CCSR_CALSMP_1
ADC_CCSR_CALSMP_Msk
ADC_CCSR_CALSMP_Pos
ADC_CFGR1_ALIGN
ADC_CFGR1_ALIGN_Msk
ADC_CFGR1_ALIGN_Pos
ADC_CFGR1_AWDCH
ADC_CFGR1_AWDCH_0
ADC_CFGR1_AWDCH_1
ADC_CFGR1_AWDCH_2
ADC_CFGR1_AWDCH_3
ADC_CFGR1_AWDCH_Msk
ADC_CFGR1_AWDCH_Pos
ADC_CFGR1_AWDEN
ADC_CFGR1_AWDEN_Msk
ADC_CFGR1_AWDEN_Pos
ADC_CFGR1_AWDSGL
ADC_CFGR1_AWDSGL_Msk
ADC_CFGR1_AWDSGL_Pos
ADC_CFGR1_CONT
ADC_CFGR1_CONT_Msk
ADC_CFGR1_CONT_Pos
ADC_CFGR1_DISCEN
ADC_CFGR1_DISCEN_Msk
ADC_CFGR1_DISCEN_Pos
ADC_CFGR1_DMACFG
ADC_CFGR1_DMACFG_Msk
ADC_CFGR1_DMACFG_Pos
ADC_CFGR1_DMAEN
ADC_CFGR1_DMAEN_Msk
ADC_CFGR1_DMAEN_Pos
ADC_CFGR1_EXTEN
ADC_CFGR1_EXTEN_0
ADC_CFGR1_EXTEN_1
ADC_CFGR1_EXTEN_Msk
ADC_CFGR1_EXTEN_Pos
ADC_CFGR1_EXTSEL
ADC_CFGR1_EXTSEL_0
ADC_CFGR1_EXTSEL_1
ADC_CFGR1_EXTSEL_2
ADC_CFGR1_EXTSEL_Msk
ADC_CFGR1_EXTSEL_Pos
ADC_CFGR1_OVRMOD
ADC_CFGR1_OVRMOD_Msk
ADC_CFGR1_OVRMOD_Pos
ADC_CFGR1_RESSEL
ADC_CFGR1_RESSEL_0
ADC_CFGR1_RESSEL_1
ADC_CFGR1_RESSEL_Msk
ADC_CFGR1_RESSEL_Pos
ADC_CFGR1_SCANDIR
ADC_CFGR1_SCANDIR_Msk
ADC_CFGR1_SCANDIR_Pos
ADC_CFGR1_WAIT
ADC_CFGR1_WAIT_Msk
ADC_CFGR1_WAIT_Pos
ADC_CFGR2_CKMODE
ADC_CFGR2_CKMODE_0
ADC_CFGR2_CKMODE_1
ADC_CFGR2_CKMODE_2
ADC_CFGR2_CKMODE_3
ADC_CFGR2_CKMODE_Msk
ADC_CFGR2_CKMODE_Pos
ADC_CHANNEL_0
ADC_CHANNEL_1
ADC_CHANNEL_2
ADC_CHANNEL_3
ADC_CHANNEL_4
ADC_CHANNEL_5
ADC_CHANNEL_6
ADC_CHANNEL_7
ADC_CHANNEL_8
ADC_CHANNEL_9
ADC_CHANNEL_11
ADC_CHANNEL_12
ADC_CHANNEL_TEMPSENSOR
ADC_CHANNEL_VREFINT
ADC_CHSELR_CHSEL
ADC_CHSELR_CHSEL0
ADC_CHSELR_CHSEL0_Msk
ADC_CHSELR_CHSEL0_Pos
ADC_CHSELR_CHSEL1
ADC_CHSELR_CHSEL2
ADC_CHSELR_CHSEL3
ADC_CHSELR_CHSEL4
ADC_CHSELR_CHSEL5
ADC_CHSELR_CHSEL6
ADC_CHSELR_CHSEL7
ADC_CHSELR_CHSEL8
ADC_CHSELR_CHSEL9
ADC_CHSELR_CHSEL1_Msk
ADC_CHSELR_CHSEL1_Pos
ADC_CHSELR_CHSEL2_Msk
ADC_CHSELR_CHSEL2_Pos
ADC_CHSELR_CHSEL3_Msk
ADC_CHSELR_CHSEL3_Pos
ADC_CHSELR_CHSEL4_Msk
ADC_CHSELR_CHSEL4_Pos
ADC_CHSELR_CHSEL5_Msk
ADC_CHSELR_CHSEL5_Pos
ADC_CHSELR_CHSEL6_Msk
ADC_CHSELR_CHSEL6_Pos
ADC_CHSELR_CHSEL7_Msk
ADC_CHSELR_CHSEL7_Pos
ADC_CHSELR_CHSEL8_Msk
ADC_CHSELR_CHSEL8_Pos
ADC_CHSELR_CHSEL9_Msk
ADC_CHSELR_CHSEL9_Pos
ADC_CHSELR_CHSEL11
ADC_CHSELR_CHSEL12
ADC_CHSELR_CHSEL11_Msk
ADC_CHSELR_CHSEL11_Pos
ADC_CHSELR_CHSEL12_Msk
ADC_CHSELR_CHSEL12_Pos
ADC_CHSELR_CHSEL_Msk
ADC_CHSELR_CHSEL_Pos
ADC_CLOCK_ASYNC_HSI_DIV1
ADC_CLOCK_ASYNC_HSI_DIV2
ADC_CLOCK_ASYNC_HSI_DIV4
ADC_CLOCK_ASYNC_HSI_DIV8
ADC_CLOCK_ASYNC_HSI_DIV16
ADC_CLOCK_ASYNC_HSI_DIV32
ADC_CLOCK_ASYNC_HSI_DIV64
ADC_CLOCK_SYNC_PCLK_DIV1
ADC_CLOCK_SYNC_PCLK_DIV2
ADC_CLOCK_SYNC_PCLK_DIV4
ADC_CLOCK_SYNC_PCLK_DIV8
ADC_CLOCK_SYNC_PCLK_DIV16
ADC_CLOCK_SYNC_PCLK_DIV32
ADC_CLOCK_SYNC_PCLK_DIV64
ADC_CR_ADCAL
ADC_CR_ADCAL_Msk
ADC_CR_ADCAL_Pos
ADC_CR_ADEN
ADC_CR_ADEN_Msk
ADC_CR_ADEN_Pos
ADC_CR_ADSTART
ADC_CR_ADSTART_Msk
ADC_CR_ADSTART_Pos
ADC_CR_ADSTP
ADC_CR_ADSTP_Msk
ADC_CR_ADSTP_Pos
ADC_DATAALIGN_LEFT
ADC_DATAALIGN_RIGHT
ADC_DR_DATA
ADC_DR_DATA_0
ADC_DR_DATA_1
ADC_DR_DATA_2
ADC_DR_DATA_3
ADC_DR_DATA_4
ADC_DR_DATA_5
ADC_DR_DATA_6
ADC_DR_DATA_7
ADC_DR_DATA_8
ADC_DR_DATA_9
ADC_DR_DATA_10
ADC_DR_DATA_11
ADC_DR_DATA_12
ADC_DR_DATA_13
ADC_DR_DATA_14
ADC_DR_DATA_15
ADC_DR_DATA_Msk
ADC_DR_DATA_Pos
ADC_EOC_SEQ_CONV
ADC_EOC_SINGLE_CONV
ADC_EXTERNALTRIGCONVEDGE_FALLING
ADC_EXTERNALTRIGCONVEDGE_NONE
ADC_EXTERNALTRIGCONVEDGE_RISING
ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
ADC_EXTERNALTRIGCONV_T1_CC4
ADC_EXTERNALTRIGCONV_T1_TRGO
ADC_EXTERNALTRIGCONV_T3_TRGO
ADC_FLAG_AWD
ADC_FLAG_EOC
ADC_FLAG_EOS
ADC_FLAG_EOSMP
ADC_FLAG_OVR
ADC_FLAG_POSTCONV_ALL
ADC_IER_AWDIE
ADC_IER_AWDIE_Msk
ADC_IER_AWDIE_Pos
ADC_IER_EOCIE
ADC_IER_EOCIE_Msk
ADC_IER_EOCIE_Pos
ADC_IER_EOSEQIE
ADC_IER_EOSEQIE_Msk
ADC_IER_EOSEQIE_Pos
ADC_IER_EOSMPIE
ADC_IER_EOSMPIE_Msk
ADC_IER_EOSMPIE_Pos
ADC_IER_OVRIE
ADC_IER_OVRIE_Msk
ADC_IER_OVRIE_Pos
ADC_ISR_AWD
ADC_ISR_AWD_Msk
ADC_ISR_AWD_Pos
ADC_ISR_EOC
ADC_ISR_EOC_Msk
ADC_ISR_EOC_Pos
ADC_ISR_EOSEQ
ADC_ISR_EOSEQ_Msk
ADC_ISR_EOSEQ_Pos
ADC_ISR_EOSMP
ADC_ISR_EOSMP_Msk
ADC_ISR_EOSMP_Pos
ADC_ISR_OVR
ADC_ISR_OVR_Msk
ADC_ISR_OVR_Pos
ADC_IT_AWD
ADC_IT_EOC
ADC_IT_EOS
ADC_IT_EOSMP
ADC_IT_OVR
ADC_OVR_DATA_OVERWRITTEN
ADC_OVR_DATA_PRESERVED
ADC_OVR_EVENT
ADC_RANK_CHANNEL_NUMBER
ADC_RANK_NONE
ADC_RESOLUTION_6B
ADC_RESOLUTION_8B
ADC_RESOLUTION_10B
ADC_RESOLUTION_12B
ADC_SAMPLETIME_3CYCLES_5
ADC_SAMPLETIME_5CYCLES_5
ADC_SAMPLETIME_7CYCLES_5
ADC_SAMPLETIME_13CYCLES_5
ADC_SAMPLETIME_28CYCLES_5
ADC_SAMPLETIME_41CYCLES_5
ADC_SAMPLETIME_71CYCLES_5
ADC_SAMPLETIME_239CYCLES_5
ADC_SCAN_DIRECTION_BACKWARD
ADC_SCAN_DIRECTION_FORWARD
ADC_SCAN_ENABLE
ADC_SMPR_SMP
ADC_SMPR_SMP_0
ADC_SMPR_SMP_1
ADC_SMPR_SMP_2
ADC_SMPR_SMP_Msk
ADC_SMPR_SMP_Pos
ADC_SOFTWARE_START
ADC_TR_HT
ADC_TR_HT_0
ADC_TR_HT_1
ADC_TR_HT_2
ADC_TR_HT_3
ADC_TR_HT_4
ADC_TR_HT_5
ADC_TR_HT_6
ADC_TR_HT_7
ADC_TR_HT_8
ADC_TR_HT_9
ADC_TR_HT_10
ADC_TR_HT_11
ADC_TR_HT_Msk
ADC_TR_HT_Pos
ADC_TR_LT
ADC_TR_LT_0
ADC_TR_LT_1
ADC_TR_LT_2
ADC_TR_LT_3
ADC_TR_LT_4
ADC_TR_LT_5
ADC_TR_LT_6
ADC_TR_LT_7
ADC_TR_LT_8
ADC_TR_LT_9
ADC_TR_LT_10
ADC_TR_LT_11
ADC_TR_LT_Msk
ADC_TR_LT_Pos
AHBPERIPH_BASE
APBPERIPH_BASE
APSR_C_Msk
APSR_C_Pos
APSR_N_Msk
APSR_N_Pos
APSR_V_Msk
APSR_V_Pos
APSR_Z_Msk
APSR_Z_Pos
BDCR_REG_INDEX
BKP_RTCCR_ASOE
BKP_RTCCR_ASOE_Msk
BKP_RTCCR_ASOE_Pos
BKP_RTCCR_ASOS
BKP_RTCCR_ASOS_Msk
BKP_RTCCR_ASOS_Pos
BKP_RTCCR_CAL
BKP_RTCCR_CAL_0
BKP_RTCCR_CAL_1
BKP_RTCCR_CAL_2
BKP_RTCCR_CAL_3
BKP_RTCCR_CAL_4
BKP_RTCCR_CAL_5
BKP_RTCCR_CAL_6
BKP_RTCCR_CAL_Msk
BKP_RTCCR_CAL_Pos
BKP_RTCCR_CCO
BKP_RTCCR_CCO_Msk
BKP_RTCCR_CCO_Pos
COMP1
COMP2
COMP1_BASE
COMP2_BASE
COMP12_COMMON
COMP_CSR_COMP1_EN
COMP_CSR_COMP2_EN
COMP_CSR_COMP_OUT
COMP_CSR_COMP_OUT_Msk
COMP_CSR_COMP_OUT_Pos
COMP_CSR_EN
COMP_CSR_EN_Msk
COMP_CSR_EN_Pos
COMP_CSR_HYST
COMP_CSR_HYST_Msk
COMP_CSR_HYST_Pos
COMP_CSR_INMSEL
COMP_CSR_INMSEL_0
COMP_CSR_INMSEL_1
COMP_CSR_INMSEL_2
COMP_CSR_INMSEL_3
COMP_CSR_INMSEL_Msk
COMP_CSR_INMSEL_Pos
COMP_CSR_INPSEL
COMP_CSR_INPSEL_0
COMP_CSR_INPSEL_1
COMP_CSR_INPSEL_Msk
COMP_CSR_INPSEL_Pos
COMP_CSR_LOCK
COMP_CSR_LOCK_Msk
COMP_CSR_LOCK_Pos
COMP_CSR_POLARITY
COMP_CSR_POLARITY_Msk
COMP_CSR_POLARITY_Pos
COMP_CSR_PWRMODE
COMP_CSR_PWRMODE_0
COMP_CSR_PWRMODE_1
COMP_CSR_PWRMODE_Msk
COMP_CSR_PWRMODE_Pos
COMP_CSR_SCALER_EN
COMP_CSR_SCALER_EN_Msk
COMP_CSR_SCALER_EN_Pos
COMP_CSR_WINMODE
COMP_CSR_WINMODE_Msk
COMP_CSR_WINMODE_Pos
COMP_FR_FLTCNT
COMP_FR_FLTCNT_Msk
COMP_FR_FLTCNT_Pos
COMP_FR_FLTEN
COMP_FR_FLTEN_Msk
COMP_FR_FLTEN_Pos
CONTROL_SPSEL_Msk
CONTROL_SPSEL_Pos
CONTROL_nPRIV_Msk
CONTROL_nPRIV_Pos
CRC
CRC_BASE
CRC_CR_RESET
CRC_CR_RESET_Msk
CRC_CR_RESET_Pos
CRC_DR_DR
CRC_DR_DR_Msk
CRC_DR_DR_Pos
CRC_IDR_IDR
CRC_IDR_IDR_Msk
CRC_IDR_IDR_Pos
CR_REG_INDEX
CSR_REG_INDEX
DBGMCU
DBGMCU_APB_FZ1_DBG_IWDG_STOP
DBGMCU_APB_FZ1_DBG_IWDG_STOP_Msk
DBGMCU_APB_FZ1_DBG_IWDG_STOP_Pos
DBGMCU_APB_FZ1_DBG_LPTIM_STOP
DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Msk
DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Pos
DBGMCU_APB_FZ1_DBG_RTC_STOP
DBGMCU_APB_FZ1_DBG_RTC_STOP_Msk
DBGMCU_APB_FZ1_DBG_RTC_STOP_Pos
DBGMCU_APB_FZ1_DBG_TIM3_STOP
DBGMCU_APB_FZ1_DBG_TIM3_STOP_Msk
DBGMCU_APB_FZ1_DBG_TIM3_STOP_Pos
DBGMCU_APB_FZ1_DBG_WWDG_STOP
DBGMCU_APB_FZ1_DBG_WWDG_STOP_Msk
DBGMCU_APB_FZ1_DBG_WWDG_STOP_Pos
DBGMCU_APB_FZ2_DBG_TIM1_STOP
DBGMCU_APB_FZ2_DBG_TIM1_STOP_Msk
DBGMCU_APB_FZ2_DBG_TIM1_STOP_Pos
DBGMCU_APB_FZ2_DBG_TIM14_STOP
DBGMCU_APB_FZ2_DBG_TIM14_STOP_Msk
DBGMCU_APB_FZ2_DBG_TIM14_STOP_Pos
DBGMCU_APB_FZ2_DBG_TIM16_STOP
DBGMCU_APB_FZ2_DBG_TIM16_STOP_Msk
DBGMCU_APB_FZ2_DBG_TIM16_STOP_Pos
DBGMCU_APB_FZ2_DBG_TIM17_STOP
DBGMCU_APB_FZ2_DBG_TIM17_STOP_Msk
DBGMCU_APB_FZ2_DBG_TIM17_STOP_Pos
DBGMCU_BASE
DBGMCU_CR_DBG_STOP
DBGMCU_CR_DBG_STOP_Msk
DBGMCU_CR_DBG_STOP_Pos
DBGMCU_IDCODE_DEV_ID
DBGMCU_IDCODE_DEV_ID_Msk
DBGMCU_IDCODE_DEV_ID_Pos
DBGMCU_IDCODE_REV_ID
DBGMCU_IDCODE_REV_ID_Msk
DBGMCU_IDCODE_REV_ID_Pos
DMA1
DMA1_BASE
DMA1_Channel1
DMA1_Channel2
DMA1_Channel3
DMA1_Channel1_BASE
DMA1_Channel2_BASE
DMA1_Channel3_BASE
DMA_CCR_CIRC
DMA_CCR_CIRC_Msk
DMA_CCR_CIRC_Pos
DMA_CCR_DIR
DMA_CCR_DIR_Msk
DMA_CCR_DIR_Pos
DMA_CCR_EN
DMA_CCR_EN_Msk
DMA_CCR_EN_Pos
DMA_CCR_HTIE
DMA_CCR_HTIE_Msk
DMA_CCR_HTIE_Pos
DMA_CCR_MEM2MEM
DMA_CCR_MEM2MEM_Msk
DMA_CCR_MEM2MEM_Pos
DMA_CCR_MINC
DMA_CCR_MINC_Msk
DMA_CCR_MINC_Pos
DMA_CCR_MSIZE
DMA_CCR_MSIZE_0
DMA_CCR_MSIZE_1
DMA_CCR_MSIZE_Msk
DMA_CCR_MSIZE_Pos
DMA_CCR_PINC
DMA_CCR_PINC_Msk
DMA_CCR_PINC_Pos
DMA_CCR_PL
DMA_CCR_PL_0
DMA_CCR_PL_1
DMA_CCR_PL_Msk
DMA_CCR_PL_Pos
DMA_CCR_PSIZE
DMA_CCR_PSIZE_0
DMA_CCR_PSIZE_1
DMA_CCR_PSIZE_Msk
DMA_CCR_PSIZE_Pos
DMA_CCR_TCIE
DMA_CCR_TCIE_Msk
DMA_CCR_TCIE_Pos
DMA_CCR_TEIE
DMA_CCR_TEIE_Msk
DMA_CCR_TEIE_Pos
DMA_CHANNEL_MAP_ADC
DMA_CHANNEL_MAP_END
DMA_CHANNEL_MAP_I2C_RX
DMA_CHANNEL_MAP_I2C_TX
DMA_CHANNEL_MAP_SPI1_RX
DMA_CHANNEL_MAP_SPI1_TX
DMA_CHANNEL_MAP_SPI2_RX
DMA_CHANNEL_MAP_SPI2_TX
DMA_CHANNEL_MAP_TIM1_CH1
DMA_CHANNEL_MAP_TIM1_CH2
DMA_CHANNEL_MAP_TIM1_CH3
DMA_CHANNEL_MAP_TIM1_CH4
DMA_CHANNEL_MAP_TIM1_COM
DMA_CHANNEL_MAP_TIM1_TRIG
DMA_CHANNEL_MAP_TIM1_UP
DMA_CHANNEL_MAP_TIM3_CH1
DMA_CHANNEL_MAP_TIM3_CH3
DMA_CHANNEL_MAP_TIM3_CH4
DMA_CHANNEL_MAP_TIM3_TRIG
DMA_CHANNEL_MAP_TIM3_UP
DMA_CHANNEL_MAP_TIM16_CH1
DMA_CHANNEL_MAP_TIM16_UP
DMA_CHANNEL_MAP_TIM17_CH1
DMA_CHANNEL_MAP_TIM17_UP
DMA_CHANNEL_MAP_USART1_RX
DMA_CHANNEL_MAP_USART1_TX
DMA_CHANNEL_MAP_USART2_RX
DMA_CHANNEL_MAP_USART2_TX
DMA_CIRCULAR
DMA_CMAR_MA
DMA_CMAR_MA_Msk
DMA_CMAR_MA_Pos
DMA_CNDTR_NDT
DMA_CNDTR_NDT_Msk
DMA_CNDTR_NDT_Pos
DMA_CPAR_PA
DMA_CPAR_PA_Msk
DMA_CPAR_PA_Pos
DMA_FLAG_GL1
DMA_FLAG_GL2
DMA_FLAG_GL3
DMA_FLAG_HT1
DMA_FLAG_HT2
DMA_FLAG_HT3
DMA_FLAG_TC1
DMA_FLAG_TC2
DMA_FLAG_TC3
DMA_FLAG_TE1
DMA_FLAG_TE2
DMA_FLAG_TE3
DMA_IFCR_CGIF1
DMA_IFCR_CGIF2
DMA_IFCR_CGIF3
DMA_IFCR_CGIF1_Msk
DMA_IFCR_CGIF1_Pos
DMA_IFCR_CGIF2_Msk
DMA_IFCR_CGIF2_Pos
DMA_IFCR_CGIF3_Msk
DMA_IFCR_CGIF3_Pos
DMA_IFCR_CHTIF1
DMA_IFCR_CHTIF2
DMA_IFCR_CHTIF3
DMA_IFCR_CHTIF1_Msk
DMA_IFCR_CHTIF1_Pos
DMA_IFCR_CHTIF2_Msk
DMA_IFCR_CHTIF2_Pos
DMA_IFCR_CHTIF3_Msk
DMA_IFCR_CHTIF3_Pos
DMA_IFCR_CTCIF1
DMA_IFCR_CTCIF2
DMA_IFCR_CTCIF3
DMA_IFCR_CTCIF1_Msk
DMA_IFCR_CTCIF1_Pos
DMA_IFCR_CTCIF2_Msk
DMA_IFCR_CTCIF2_Pos
DMA_IFCR_CTCIF3_Msk
DMA_IFCR_CTCIF3_Pos
DMA_IFCR_CTEIF1
DMA_IFCR_CTEIF2
DMA_IFCR_CTEIF3
DMA_IFCR_CTEIF1_Msk
DMA_IFCR_CTEIF1_Pos
DMA_IFCR_CTEIF2_Msk
DMA_IFCR_CTEIF2_Pos
DMA_IFCR_CTEIF3_Msk
DMA_IFCR_CTEIF3_Pos
DMA_ISR_GIF1
DMA_ISR_GIF2
DMA_ISR_GIF3
DMA_ISR_GIF1_Msk
DMA_ISR_GIF1_Pos
DMA_ISR_GIF2_Msk
DMA_ISR_GIF2_Pos
DMA_ISR_GIF3_Msk
DMA_ISR_GIF3_Pos
DMA_ISR_HTIF1
DMA_ISR_HTIF2
DMA_ISR_HTIF3
DMA_ISR_HTIF1_Msk
DMA_ISR_HTIF1_Pos
DMA_ISR_HTIF2_Msk
DMA_ISR_HTIF2_Pos
DMA_ISR_HTIF3_Msk
DMA_ISR_HTIF3_Pos
DMA_ISR_TCIF1
DMA_ISR_TCIF2
DMA_ISR_TCIF3
DMA_ISR_TCIF1_Msk
DMA_ISR_TCIF1_Pos
DMA_ISR_TCIF2_Msk
DMA_ISR_TCIF2_Pos
DMA_ISR_TCIF3_Msk
DMA_ISR_TCIF3_Pos
DMA_ISR_TEIF1
DMA_ISR_TEIF2
DMA_ISR_TEIF3
DMA_ISR_TEIF1_Msk
DMA_ISR_TEIF1_Pos
DMA_ISR_TEIF2_Msk
DMA_ISR_TEIF2_Pos
DMA_ISR_TEIF3_Msk
DMA_ISR_TEIF3_Pos
DMA_IT_HT
DMA_IT_TC
DMA_IT_TE
DMA_MDATAALIGN_BYTE
DMA_MDATAALIGN_HALFWORD
DMA_MDATAALIGN_WORD
DMA_MEMORY_TO_MEMORY
DMA_MEMORY_TO_PERIPH
DMA_MINC_DISABLE
DMA_MINC_ENABLE
DMA_NORMAL
DMA_PDATAALIGN_BYTE
DMA_PDATAALIGN_HALFWORD
DMA_PDATAALIGN_WORD
DMA_PERIPH_TO_MEMORY
DMA_PINC_DISABLE
DMA_PINC_ENABLE
DMA_PRIORITY_HIGH
DMA_PRIORITY_LOW
DMA_PRIORITY_MEDIUM
DMA_PRIORITY_VERY_HIGH
EXTI
EXTI_BASE
EXTI_CONFIG
EXTI_CallbackIDTypeDef_HAL_EXTI_COMMON_CB_ID
EXTI_DIRECT
EXTI_EMR_EM
EXTI_EMR_EM0
EXTI_EMR_EM0_Msk
EXTI_EMR_EM0_Pos
EXTI_EMR_EM1
EXTI_EMR_EM2
EXTI_EMR_EM3
EXTI_EMR_EM4
EXTI_EMR_EM5
EXTI_EMR_EM6
EXTI_EMR_EM7
EXTI_EMR_EM8
EXTI_EMR_EM9
EXTI_EMR_EM1_Msk
EXTI_EMR_EM1_Pos
EXTI_EMR_EM2_Msk
EXTI_EMR_EM2_Pos
EXTI_EMR_EM3_Msk
EXTI_EMR_EM3_Pos
EXTI_EMR_EM4_Msk
EXTI_EMR_EM4_Pos
EXTI_EMR_EM5_Msk
EXTI_EMR_EM5_Pos
EXTI_EMR_EM6_Msk
EXTI_EMR_EM6_Pos
EXTI_EMR_EM7_Msk
EXTI_EMR_EM7_Pos
EXTI_EMR_EM8_Msk
EXTI_EMR_EM8_Pos
EXTI_EMR_EM9_Msk
EXTI_EMR_EM9_Pos
EXTI_EMR_EM10
EXTI_EMR_EM11
EXTI_EMR_EM12
EXTI_EMR_EM13
EXTI_EMR_EM14
EXTI_EMR_EM15
EXTI_EMR_EM16
EXTI_EMR_EM17
EXTI_EMR_EM18
EXTI_EMR_EM19
EXTI_EMR_EM29
EXTI_EMR_EM10_Msk
EXTI_EMR_EM10_Pos
EXTI_EMR_EM11_Msk
EXTI_EMR_EM11_Pos
EXTI_EMR_EM12_Msk
EXTI_EMR_EM12_Pos
EXTI_EMR_EM13_Msk
EXTI_EMR_EM13_Pos
EXTI_EMR_EM14_Msk
EXTI_EMR_EM14_Pos
EXTI_EMR_EM15_Msk
EXTI_EMR_EM15_Pos
EXTI_EMR_EM16_Msk
EXTI_EMR_EM16_Pos
EXTI_EMR_EM17_Msk
EXTI_EMR_EM17_Pos
EXTI_EMR_EM18_Msk
EXTI_EMR_EM18_Pos
EXTI_EMR_EM19_Msk
EXTI_EMR_EM19_Pos
EXTI_EMR_EM29_Msk
EXTI_EMR_EM29_Pos
EXTI_EMR_EM_Msk
EXTI_EMR_EM_Pos
EXTI_EXTICR1_EXTI0
EXTI_EXTICR1_EXTI0_0
EXTI_EXTICR1_EXTI0_1
EXTI_EXTICR1_EXTI0_Msk
EXTI_EXTICR1_EXTI0_Pos
EXTI_EXTICR1_EXTI1
EXTI_EXTICR1_EXTI2
EXTI_EXTICR1_EXTI3
EXTI_EXTICR1_EXTI1_0
EXTI_EXTICR1_EXTI1_1
EXTI_EXTICR1_EXTI1_Msk
EXTI_EXTICR1_EXTI1_Pos
EXTI_EXTICR1_EXTI2_0
EXTI_EXTICR1_EXTI2_1
EXTI_EXTICR1_EXTI2_Msk
EXTI_EXTICR1_EXTI2_Pos
EXTI_EXTICR1_EXTI3_0
EXTI_EXTICR1_EXTI3_1
EXTI_EXTICR1_EXTI3_Msk
EXTI_EXTICR1_EXTI3_Pos
EXTI_EXTICR2_EXTI4
EXTI_EXTICR2_EXTI5
EXTI_EXTICR2_EXTI6
EXTI_EXTICR2_EXTI7
EXTI_EXTICR2_EXTI4_0
EXTI_EXTICR2_EXTI4_1
EXTI_EXTICR2_EXTI4_Msk
EXTI_EXTICR2_EXTI4_Pos
EXTI_EXTICR2_EXTI5_Msk
EXTI_EXTICR2_EXTI5_Pos
EXTI_EXTICR2_EXTI6_Msk
EXTI_EXTICR2_EXTI6_Pos
EXTI_EXTICR2_EXTI7_Msk
EXTI_EXTICR2_EXTI7_Pos
EXTI_EXTICR3_EXTI8
EXTI_EXTICR3_EXTI8_Msk
EXTI_EXTICR3_EXTI8_Pos
EXTI_FTSR_FT0
EXTI_FTSR_FT0_Msk
EXTI_FTSR_FT0_Pos
EXTI_FTSR_FT1
EXTI_FTSR_FT2
EXTI_FTSR_FT3
EXTI_FTSR_FT4
EXTI_FTSR_FT5
EXTI_FTSR_FT6
EXTI_FTSR_FT7
EXTI_FTSR_FT8
EXTI_FTSR_FT9
EXTI_FTSR_FT1_Msk
EXTI_FTSR_FT1_Pos
EXTI_FTSR_FT2_Msk
EXTI_FTSR_FT2_Pos
EXTI_FTSR_FT3_Msk
EXTI_FTSR_FT3_Pos
EXTI_FTSR_FT4_Msk
EXTI_FTSR_FT4_Pos
EXTI_FTSR_FT5_Msk
EXTI_FTSR_FT5_Pos
EXTI_FTSR_FT6_Msk
EXTI_FTSR_FT6_Pos
EXTI_FTSR_FT7_Msk
EXTI_FTSR_FT7_Pos
EXTI_FTSR_FT8_Msk
EXTI_FTSR_FT8_Pos
EXTI_FTSR_FT9_Msk
EXTI_FTSR_FT9_Pos
EXTI_FTSR_FT10
EXTI_FTSR_FT11
EXTI_FTSR_FT12
EXTI_FTSR_FT13
EXTI_FTSR_FT14
EXTI_FTSR_FT15
EXTI_FTSR_FT16
EXTI_FTSR_FT17
EXTI_FTSR_FT18
EXTI_FTSR_FT10_Msk
EXTI_FTSR_FT10_Pos
EXTI_FTSR_FT11_Msk
EXTI_FTSR_FT11_Pos
EXTI_FTSR_FT12_Msk
EXTI_FTSR_FT12_Pos
EXTI_FTSR_FT13_Msk
EXTI_FTSR_FT13_Pos
EXTI_FTSR_FT14_Msk
EXTI_FTSR_FT14_Pos
EXTI_FTSR_FT15_Msk
EXTI_FTSR_FT15_Pos
EXTI_FTSR_FT16_Msk
EXTI_FTSR_FT16_Pos
EXTI_FTSR_FT17_Msk
EXTI_FTSR_FT17_Pos
EXTI_FTSR_FT18_Msk
EXTI_FTSR_FT18_Pos
EXTI_GPIO
EXTI_GPIOA
EXTI_GPIOB
EXTI_GPIOF
EXTI_IMR_IM
EXTI_IMR_IM0
EXTI_IMR_IM0_Msk
EXTI_IMR_IM0_Pos
EXTI_IMR_IM1
EXTI_IMR_IM2
EXTI_IMR_IM3
EXTI_IMR_IM4
EXTI_IMR_IM5
EXTI_IMR_IM6
EXTI_IMR_IM7
EXTI_IMR_IM8
EXTI_IMR_IM9
EXTI_IMR_IM1_Msk
EXTI_IMR_IM1_Pos
EXTI_IMR_IM2_Msk
EXTI_IMR_IM2_Pos
EXTI_IMR_IM3_Msk
EXTI_IMR_IM3_Pos
EXTI_IMR_IM4_Msk
EXTI_IMR_IM4_Pos
EXTI_IMR_IM5_Msk
EXTI_IMR_IM5_Pos
EXTI_IMR_IM6_Msk
EXTI_IMR_IM6_Pos
EXTI_IMR_IM7_Msk
EXTI_IMR_IM7_Pos
EXTI_IMR_IM8_Msk
EXTI_IMR_IM8_Pos
EXTI_IMR_IM9_Msk
EXTI_IMR_IM9_Pos
EXTI_IMR_IM10
EXTI_IMR_IM11
EXTI_IMR_IM12
EXTI_IMR_IM13
EXTI_IMR_IM14
EXTI_IMR_IM15
EXTI_IMR_IM16
EXTI_IMR_IM17
EXTI_IMR_IM18
EXTI_IMR_IM19
EXTI_IMR_IM29
EXTI_IMR_IM10_Msk
EXTI_IMR_IM10_Pos
EXTI_IMR_IM11_Msk
EXTI_IMR_IM11_Pos
EXTI_IMR_IM12_Msk
EXTI_IMR_IM12_Pos
EXTI_IMR_IM13_Msk
EXTI_IMR_IM13_Pos
EXTI_IMR_IM14_Msk
EXTI_IMR_IM14_Pos
EXTI_IMR_IM15_Msk
EXTI_IMR_IM15_Pos
EXTI_IMR_IM16_Msk
EXTI_IMR_IM16_Pos
EXTI_IMR_IM17_Msk
EXTI_IMR_IM17_Pos
EXTI_IMR_IM18_Msk
EXTI_IMR_IM18_Pos
EXTI_IMR_IM19_Msk
EXTI_IMR_IM19_Pos
EXTI_IMR_IM29_Msk
EXTI_IMR_IM29_Pos
EXTI_IMR_IM_Msk
EXTI_IMR_IM_Pos
EXTI_LINE_0
EXTI_LINE_1
EXTI_LINE_2
EXTI_LINE_3
EXTI_LINE_4
EXTI_LINE_5
EXTI_LINE_6
EXTI_LINE_7
EXTI_LINE_8
EXTI_LINE_9
EXTI_LINE_10
EXTI_LINE_11
EXTI_LINE_12
EXTI_LINE_13
EXTI_LINE_14
EXTI_LINE_15
EXTI_LINE_16
EXTI_LINE_17
EXTI_LINE_18
EXTI_LINE_19
EXTI_LINE_20
EXTI_LINE_21
EXTI_LINE_22
EXTI_LINE_23
EXTI_LINE_24
EXTI_LINE_25
EXTI_LINE_26
EXTI_LINE_27
EXTI_LINE_28
EXTI_LINE_29
EXTI_LINE_30
EXTI_LINE_31
EXTI_LINE_NB
EXTI_MODE_EVENT
EXTI_MODE_INTERRUPT
EXTI_MODE_MASK
EXTI_MODE_NONE
EXTI_PIN_MASK
EXTI_PROPERTY_MASK
EXTI_PROPERTY_SHIFT
EXTI_PR_PIF0
EXTI_PR_PIF1
EXTI_PR_PIF2
EXTI_PR_PIF3
EXTI_PR_PIF4
EXTI_PR_PIF5
EXTI_PR_PIF6
EXTI_PR_PIF7
EXTI_PR_PIF8
EXTI_PR_PIF9
EXTI_PR_PIF10
EXTI_PR_PIF11
EXTI_PR_PIF12
EXTI_PR_PIF13
EXTI_PR_PIF14
EXTI_PR_PIF15
EXTI_PR_PIF16
EXTI_PR_PIF17
EXTI_PR_PIF18
EXTI_PR_PR0
EXTI_PR_PR0_Msk
EXTI_PR_PR0_Pos
EXTI_PR_PR1
EXTI_PR_PR2
EXTI_PR_PR3
EXTI_PR_PR4
EXTI_PR_PR5
EXTI_PR_PR6
EXTI_PR_PR7
EXTI_PR_PR8
EXTI_PR_PR9
EXTI_PR_PR1_Msk
EXTI_PR_PR1_Pos
EXTI_PR_PR2_Msk
EXTI_PR_PR2_Pos
EXTI_PR_PR3_Msk
EXTI_PR_PR3_Pos
EXTI_PR_PR5_Msk
EXTI_PR_PR5_Pos
EXTI_PR_PR6_Msk
EXTI_PR_PR6_Pos
EXTI_PR_PR7_Msk
EXTI_PR_PR7_Pos
EXTI_PR_PR8_Msk
EXTI_PR_PR8_Pos
EXTI_PR_PR9_Msk
EXTI_PR_PR9_Pos
EXTI_PR_PR10
EXTI_PR_PR11
EXTI_PR_PR12
EXTI_PR_PR13
EXTI_PR_PR14
EXTI_PR_PR15
EXTI_PR_PR16
EXTI_PR_PR17
EXTI_PR_PR18
EXTI_PR_PR10_Msk
EXTI_PR_PR10_Pos
EXTI_PR_PR11_Msk
EXTI_PR_PR11_Pos
EXTI_PR_PR12_Msk
EXTI_PR_PR12_Pos
EXTI_PR_PR13_Msk
EXTI_PR_PR13_Pos
EXTI_PR_PR14_Msk
EXTI_PR_PR14_Pos
EXTI_PR_PR15_Msk
EXTI_PR_PR15_Pos
EXTI_PR_PR16_Msk
EXTI_PR_PR16_Pos
EXTI_PR_PR17_Msk
EXTI_PR_PR17_Pos
EXTI_PR_PR18_Msk
EXTI_PR_PR18_Pos
EXTI_PR_PR_Msk
EXTI_PR_PR_Pos
EXTI_REG1
EXTI_REG2
EXTI_REG_MASK
EXTI_REG_SHIFT
EXTI_RESERVED
EXTI_RTSR_RT0
EXTI_RTSR_RT0_Msk
EXTI_RTSR_RT0_Pos
EXTI_RTSR_RT1
EXTI_RTSR_RT2
EXTI_RTSR_RT3
EXTI_RTSR_RT4
EXTI_RTSR_RT5
EXTI_RTSR_RT6
EXTI_RTSR_RT7
EXTI_RTSR_RT8
EXTI_RTSR_RT9
EXTI_RTSR_RT1_Msk
EXTI_RTSR_RT1_Pos
EXTI_RTSR_RT2_Msk
EXTI_RTSR_RT2_Pos
EXTI_RTSR_RT3_Msk
EXTI_RTSR_RT3_Pos
EXTI_RTSR_RT4_Msk
EXTI_RTSR_RT4_Pos
EXTI_RTSR_RT5_Msk
EXTI_RTSR_RT5_Pos
EXTI_RTSR_RT6_Msk
EXTI_RTSR_RT6_Pos
EXTI_RTSR_RT7_Msk
EXTI_RTSR_RT7_Pos
EXTI_RTSR_RT8_Msk
EXTI_RTSR_RT8_Pos
EXTI_RTSR_RT9_Msk
EXTI_RTSR_RT9_Pos
EXTI_RTSR_RT10
EXTI_RTSR_RT11
EXTI_RTSR_RT12
EXTI_RTSR_RT13
EXTI_RTSR_RT14
EXTI_RTSR_RT15
EXTI_RTSR_RT16
EXTI_RTSR_RT17
EXTI_RTSR_RT18
EXTI_RTSR_RT10_Msk
EXTI_RTSR_RT10_Pos
EXTI_RTSR_RT11_Msk
EXTI_RTSR_RT11_Pos
EXTI_RTSR_RT12_Msk
EXTI_RTSR_RT12_Pos
EXTI_RTSR_RT13_Msk
EXTI_RTSR_RT13_Pos
EXTI_RTSR_RT14_Msk
EXTI_RTSR_RT14_Pos
EXTI_RTSR_RT15_Msk
EXTI_RTSR_RT15_Pos
EXTI_RTSR_RT16_Msk
EXTI_RTSR_RT16_Pos
EXTI_RTSR_RT17_Msk
EXTI_RTSR_RT17_Pos
EXTI_RTSR_RT18_Msk
EXTI_RTSR_RT18_Pos
EXTI_SWIER_SWI0
EXTI_SWIER_SWI0_Msk
EXTI_SWIER_SWI0_Pos
EXTI_SWIER_SWI1
EXTI_SWIER_SWI2
EXTI_SWIER_SWI3
EXTI_SWIER_SWI4
EXTI_SWIER_SWI5
EXTI_SWIER_SWI6
EXTI_SWIER_SWI7
EXTI_SWIER_SWI8
EXTI_SWIER_SWI9
EXTI_SWIER_SWI1_Msk
EXTI_SWIER_SWI1_Pos
EXTI_SWIER_SWI2_Msk
EXTI_SWIER_SWI2_Pos
EXTI_SWIER_SWI3_Msk
EXTI_SWIER_SWI3_Pos
EXTI_SWIER_SWI4_Msk
EXTI_SWIER_SWI4_Pos
EXTI_SWIER_SWI5_Msk
EXTI_SWIER_SWI5_Pos
EXTI_SWIER_SWI6_Msk
EXTI_SWIER_SWI6_Pos
EXTI_SWIER_SWI7_Msk
EXTI_SWIER_SWI7_Pos
EXTI_SWIER_SWI8_Msk
EXTI_SWIER_SWI8_Pos
EXTI_SWIER_SWI9_Msk
EXTI_SWIER_SWI9_Pos
EXTI_SWIER_SWI10
EXTI_SWIER_SWI11
EXTI_SWIER_SWI12
EXTI_SWIER_SWI13
EXTI_SWIER_SWI14
EXTI_SWIER_SWI15
EXTI_SWIER_SWI16
EXTI_SWIER_SWI17
EXTI_SWIER_SWI18
EXTI_SWIER_SWI10_Msk
EXTI_SWIER_SWI10_Pos
EXTI_SWIER_SWI11_Msk
EXTI_SWIER_SWI11_Pos
EXTI_SWIER_SWI12_Msk
EXTI_SWIER_SWI12_Pos
EXTI_SWIER_SWI13_Msk
EXTI_SWIER_SWI13_Pos
EXTI_SWIER_SWI14_Msk
EXTI_SWIER_SWI14_Pos
EXTI_SWIER_SWI15_Msk
EXTI_SWIER_SWI15_Pos
EXTI_SWIER_SWI16_Msk
EXTI_SWIER_SWI16_Pos
EXTI_SWIER_SWI17_Msk
EXTI_SWIER_SWI17_Pos
EXTI_SWIER_SWI18_Msk
EXTI_SWIER_SWI18_Pos
EXTI_TRIGGER_FALLING
EXTI_TRIGGER_MASK
EXTI_TRIGGER_NONE
EXTI_TRIGGER_RISING
EXTI_TRIGGER_RISING_FALLING
ErrorStatus_ERROR
ErrorStatus_SUCCESS
FLASH
FLASHSIZE_BASE
FLASH_ACR_LATENCY
FLASH_ACR_LATENCY_Msk
FLASH_ACR_LATENCY_Pos
FLASH_BASE
FLASH_CR_EOPIE
FLASH_CR_EOPIE_Msk
FLASH_CR_EOPIE_Pos
FLASH_CR_ERRIE
FLASH_CR_ERRIE_Msk
FLASH_CR_ERRIE_Pos
FLASH_CR_LOCK
FLASH_CR_LOCK_Msk
FLASH_CR_LOCK_Pos
FLASH_CR_MER
FLASH_CR_MER_Msk
FLASH_CR_MER_Pos
FLASH_CR_OBL_LAUNCH
FLASH_CR_OBL_LAUNCH_Msk
FLASH_CR_OBL_LAUNCH_Pos
FLASH_CR_OPTLOCK
FLASH_CR_OPTLOCK_Msk
FLASH_CR_OPTLOCK_Pos
FLASH_CR_OPTSTRT
FLASH_CR_OPTSTRT_Msk
FLASH_CR_OPTSTRT_Pos
FLASH_CR_PER
FLASH_CR_PER_Msk
FLASH_CR_PER_Pos
FLASH_CR_PG
FLASH_CR_PGSTRT
FLASH_CR_PGSTRT_Msk
FLASH_CR_PGSTRT_Pos
FLASH_CR_PG_Msk
FLASH_CR_PG_Pos
FLASH_CR_SER
FLASH_CR_SER_Msk
FLASH_CR_SER_Pos
FLASH_END
FLASH_FLAG_ALL_ERRORS
FLASH_FLAG_BSY
FLASH_FLAG_EOP
FLASH_FLAG_OPTVERR
FLASH_FLAG_SR_CLEAR
FLASH_FLAG_SR_ERROR
FLASH_FLAG_WRPERR
FLASH_IT_EOP
FLASH_IT_OPERR
FLASH_KEY1
FLASH_KEY2
FLASH_KEY1_Msk
FLASH_KEY1_Pos
FLASH_KEY2_Msk
FLASH_KEY2_Pos
FLASH_KEYR_KEY
FLASH_KEYR_KEY_Msk
FLASH_KEYR_KEY_Pos
FLASH_LATENCY_0
FLASH_LATENCY_1
FLASH_OPTKEY1
FLASH_OPTKEY2
FLASH_OPTKEY1_Msk
FLASH_OPTKEY1_Pos
FLASH_OPTKEY2_Msk
FLASH_OPTKEY2_Pos
FLASH_OPTKEYR_OPTKEY
FLASH_OPTKEYR_OPTKEY_Msk
FLASH_OPTKEYR_OPTKEY_Pos
FLASH_OPTR_BOR_EN
FLASH_OPTR_BOR_EN_Msk
FLASH_OPTR_BOR_EN_Pos
FLASH_OPTR_BOR_LEV
FLASH_OPTR_BOR_LEV_0
FLASH_OPTR_BOR_LEV_1
FLASH_OPTR_BOR_LEV_2
FLASH_OPTR_BOR_LEV_Msk
FLASH_OPTR_BOR_LEV_Pos
FLASH_OPTR_IWDG_SW
FLASH_OPTR_IWDG_SW_Msk
FLASH_OPTR_IWDG_SW_Pos
FLASH_OPTR_NRST_MODE
FLASH_OPTR_NRST_MODE_Msk
FLASH_OPTR_NRST_MODE_Pos
FLASH_OPTR_RDP
FLASH_OPTR_RDP_LEVEL_0
FLASH_OPTR_RDP_LEVEL_1
FLASH_OPTR_RDP_Msk
FLASH_OPTR_RDP_Pos
FLASH_OPTR_WWDG_SW
FLASH_OPTR_WWDG_SW_Msk
FLASH_OPTR_WWDG_SW_Pos
FLASH_OPTR_nBOOT1
FLASH_OPTR_nBOOT1_Msk
FLASH_OPTR_nBOOT1_Pos
FLASH_PAGE_NB
FLASH_PAGE_SIZE
FLASH_PERTPE_PERTPE
FLASH_PERTPE_PERTPE_0
FLASH_PERTPE_PERTPE_1
FLASH_PERTPE_PERTPE_2
FLASH_PERTPE_PERTPE_3
FLASH_PERTPE_PERTPE_4
FLASH_PERTPE_PERTPE_5
FLASH_PERTPE_PERTPE_6
FLASH_PERTPE_PERTPE_7
FLASH_PERTPE_PERTPE_8
FLASH_PERTPE_PERTPE_9
FLASH_PERTPE_PERTPE_10
FLASH_PERTPE_PERTPE_11
FLASH_PERTPE_PERTPE_12
FLASH_PERTPE_PERTPE_13
FLASH_PERTPE_PERTPE_14
FLASH_PERTPE_PERTPE_15
FLASH_PERTPE_PERTPE_16
FLASH_PERTPE_PERTPE_Msk
FLASH_PERTPE_PERTPE_Pos
FLASH_PRETPE_PRETPE
FLASH_PRETPE_PRETPE_0
FLASH_PRETPE_PRETPE_1
FLASH_PRETPE_PRETPE_2
FLASH_PRETPE_PRETPE_3
FLASH_PRETPE_PRETPE_4
FLASH_PRETPE_PRETPE_5
FLASH_PRETPE_PRETPE_6
FLASH_PRETPE_PRETPE_7
FLASH_PRETPE_PRETPE_8
FLASH_PRETPE_PRETPE_9
FLASH_PRETPE_PRETPE_10
FLASH_PRETPE_PRETPE_11
FLASH_PRETPE_PRETPE_12
FLASH_PRETPE_PRETPE_13
FLASH_PRETPE_PRETPE_Msk
FLASH_PRETPE_PRETPE_Pos
FLASH_PRGTPE_PRGTPE
FLASH_PRGTPE_PRGTPE_0
FLASH_PRGTPE_PRGTPE_1
FLASH_PRGTPE_PRGTPE_2
FLASH_PRGTPE_PRGTPE_3
FLASH_PRGTPE_PRGTPE_4
FLASH_PRGTPE_PRGTPE_5
FLASH_PRGTPE_PRGTPE_6
FLASH_PRGTPE_PRGTPE_7
FLASH_PRGTPE_PRGTPE_8
FLASH_PRGTPE_PRGTPE_9
FLASH_PRGTPE_PRGTPE_10
FLASH_PRGTPE_PRGTPE_11
FLASH_PRGTPE_PRGTPE_12
FLASH_PRGTPE_PRGTPE_13
FLASH_PRGTPE_PRGTPE_14
FLASH_PRGTPE_PRGTPE_15
FLASH_PRGTPE_PRGTPE_Msk
FLASH_PRGTPE_PRGTPE_Pos
FLASH_PROGRAM_ERASE_CLOCK_4MHZ
FLASH_PROGRAM_ERASE_CLOCK_8MHZ
FLASH_PROGRAM_ERASE_CLOCK_16MHZ
FLASH_PROGRAM_ERASE_CLOCK_22p12MHZ
FLASH_PROGRAM_ERASE_CLOCK_24MHZ
FLASH_R_BASE
FLASH_SDKR_SDK_END
FLASH_SDKR_SDK_END_0
FLASH_SDKR_SDK_END_1
FLASH_SDKR_SDK_END_2
FLASH_SDKR_SDK_END_3
FLASH_SDKR_SDK_END_4
FLASH_SDKR_SDK_END_Msk
FLASH_SDKR_SDK_END_Pos
FLASH_SDKR_SDK_STRT
FLASH_SDKR_SDK_STRT_0
FLASH_SDKR_SDK_STRT_1
FLASH_SDKR_SDK_STRT_2
FLASH_SDKR_SDK_STRT_3
FLASH_SDKR_SDK_STRT_4
FLASH_SDKR_SDK_STRT_Msk
FLASH_SDKR_SDK_STRT_Pos
FLASH_SECTOR_NB
FLASH_SECTOR_SIZE
FLASH_SIZE
FLASH_SMERTPE_SMERTPE
FLASH_SMERTPE_SMERTPE_0
FLASH_SMERTPE_SMERTPE_1
FLASH_SMERTPE_SMERTPE_2
FLASH_SMERTPE_SMERTPE_3
FLASH_SMERTPE_SMERTPE_4
FLASH_SMERTPE_SMERTPE_5
FLASH_SMERTPE_SMERTPE_6
FLASH_SMERTPE_SMERTPE_7
FLASH_SMERTPE_SMERTPE_8
FLASH_SMERTPE_SMERTPE_9
FLASH_SMERTPE_SMERTPE_10
FLASH_SMERTPE_SMERTPE_11
FLASH_SMERTPE_SMERTPE_12
FLASH_SMERTPE_SMERTPE_13
FLASH_SMERTPE_SMERTPE_14
FLASH_SMERTPE_SMERTPE_15
FLASH_SMERTPE_SMERTPE_16
FLASH_SMERTPE_SMERTPE_Msk
FLASH_SMERTPE_SMERTPE_Pos
FLASH_SR_BSY
FLASH_SR_BSY_Msk
FLASH_SR_BSY_Pos
FLASH_SR_EOP
FLASH_SR_EOP_Msk
FLASH_SR_EOP_Pos
FLASH_SR_OPTVERR
FLASH_SR_OPTVERR_Msk
FLASH_SR_OPTVERR_Pos
FLASH_SR_WRPERR
FLASH_SR_WRPERR_Msk
FLASH_SR_WRPERR_Pos
FLASH_STCR_SLEEP_EN
FLASH_STCR_SLEEP_EN_Msk
FLASH_STCR_SLEEP_EN_Pos
FLASH_STCR_SLEEP_TIME
FLASH_STCR_SLEEP_TIME_Msk
FLASH_STCR_SLEEP_TIME_Pos
FLASH_TIMEOUT_VALUE
FLASH_TPS3_TPS3
FLASH_TPS3_TPS3_0
FLASH_TPS3_TPS3_1
FLASH_TPS3_TPS3_2
FLASH_TPS3_TPS3_3
FLASH_TPS3_TPS3_4
FLASH_TPS3_TPS3_5
FLASH_TPS3_TPS3_6
FLASH_TPS3_TPS3_7
FLASH_TPS3_TPS3_8
FLASH_TPS3_TPS3_9
FLASH_TPS3_TPS3_10
FLASH_TPS3_TPS3_Msk
FLASH_TPS3_TPS3_Pos
FLASH_TS0_TS0
FLASH_TS0_TS0_0
FLASH_TS0_TS0_1
FLASH_TS0_TS0_2
FLASH_TS0_TS0_3
FLASH_TS0_TS0_4
FLASH_TS0_TS0_5
FLASH_TS0_TS0_6
FLASH_TS0_TS0_7
FLASH_TS0_TS0_Msk
FLASH_TS0_TS0_Pos
FLASH_TS1_TS1
FLASH_TS1_TS1_0
FLASH_TS1_TS1_1
FLASH_TS1_TS1_2
FLASH_TS1_TS1_3
FLASH_TS1_TS1_4
FLASH_TS1_TS1_5
FLASH_TS1_TS1_6
FLASH_TS1_TS1_7
FLASH_TS1_TS1_Msk
FLASH_TS1_TS1_Pos
FLASH_TS2P_TS2P
FLASH_TS2P_TS2P_0
FLASH_TS2P_TS2P_1
FLASH_TS2P_TS2P_2
FLASH_TS2P_TS2P_3
FLASH_TS2P_TS2P_4
FLASH_TS2P_TS2P_5
FLASH_TS2P_TS2P_6
FLASH_TS2P_TS2P_7
FLASH_TS2P_TS2P_Msk
FLASH_TS2P_TS2P_Pos
FLASH_TS3_TS3
FLASH_TS3_TS3_0
FLASH_TS3_TS3_1
FLASH_TS3_TS3_2
FLASH_TS3_TS3_3
FLASH_TS3_TS3_4
FLASH_TS3_TS3_5
FLASH_TS3_TS3_6
FLASH_TS3_TS3_7
FLASH_TS3_TS3_Msk
FLASH_TS3_TS3_Pos
FLASH_TYPEERASE_MASSERASE
FLASH_TYPEERASE_PAGEERASE
FLASH_TYPEERASE_SECTORERASE
FLASH_TYPENONE
FLASH_TYPEPROGRAM_PAGE
FLASH_WRPR_WRP
FLASH_WRPR_WRP_0
FLASH_WRPR_WRP_1
FLASH_WRPR_WRP_2
FLASH_WRPR_WRP_3
FLASH_WRPR_WRP_4
FLASH_WRPR_WRP_5
FLASH_WRPR_WRP_6
FLASH_WRPR_WRP_7
FLASH_WRPR_WRP_8
FLASH_WRPR_WRP_9
FLASH_WRPR_WRP_10
FLASH_WRPR_WRP_11
FLASH_WRPR_WRP_12
FLASH_WRPR_WRP_13
FLASH_WRPR_WRP_14
FLASH_WRPR_WRP_15
FLASH_WRPR_WRP_Msk
FLASH_WRPR_WRP_Pos
FlagStatus_RESET
FlagStatus_SET
FunctionalState_DISABLE
FunctionalState_ENABLE
GPIOA
GPIOA_BASE
GPIOB
GPIOB_BASE
GPIOF
GPIOF_BASE
GPIO_AF0_SPI1
GPIO_AF0_SPI2
GPIO_AF0_SWJ
GPIO_AF0_TIM14
GPIO_AF0_USART1
GPIO_AF1_IR
GPIO_AF1_SPI2
GPIO_AF1_TIM1
GPIO_AF1_TIM3
GPIO_AF1_USART1
GPIO_AF2_SPI2
GPIO_AF2_TIM1
GPIO_AF2_TIM14
GPIO_AF2_TIM16
GPIO_AF2_TIM17
GPIO_AF3_LED
GPIO_AF3_SPI2
GPIO_AF3_USART1
GPIO_AF3_USART2
GPIO_AF4_TIM14
GPIO_AF4_USART2
GPIO_AF5_EVENTOUT
GPIO_AF5_LPTIM
GPIO_AF5_MCO
GPIO_AF5_TIM16
GPIO_AF5_TIM17
GPIO_AF5_USART2
GPIO_AF6_EVENTOUT
GPIO_AF6_I2C
GPIO_AF6_LED
GPIO_AF6_MCO
GPIO_AF7_COMP1
GPIO_AF7_COMP2
GPIO_AF7_EVENTOUT
GPIO_AF8_USART1
GPIO_AF9_USART2
GPIO_AF10_SPI1
GPIO_AF11_SPI2
GPIO_AF12_I2C
GPIO_AF13_TIM1
GPIO_AF13_TIM3
GPIO_AF13_TIM14
GPIO_AF13_TIM17
GPIO_AF14_TIM1
GPIO_AF15_IR
GPIO_AF15_MCO
GPIO_AF15_RTCOUT
GPIO_AFRH_AFSEL8
GPIO_AFRH_AFSEL9
GPIO_AFRH_AFSEL8_0
GPIO_AFRH_AFSEL8_1
GPIO_AFRH_AFSEL8_2
GPIO_AFRH_AFSEL8_3
GPIO_AFRH_AFSEL8_Msk
GPIO_AFRH_AFSEL8_Pos
GPIO_AFRH_AFSEL9_0
GPIO_AFRH_AFSEL9_1
GPIO_AFRH_AFSEL9_2
GPIO_AFRH_AFSEL9_3
GPIO_AFRH_AFSEL9_Msk
GPIO_AFRH_AFSEL9_Pos
GPIO_AFRH_AFSEL10
GPIO_AFRH_AFSEL11
GPIO_AFRH_AFSEL12
GPIO_AFRH_AFSEL13
GPIO_AFRH_AFSEL14
GPIO_AFRH_AFSEL15
GPIO_AFRH_AFSEL10_0
GPIO_AFRH_AFSEL10_1
GPIO_AFRH_AFSEL10_2
GPIO_AFRH_AFSEL10_3
GPIO_AFRH_AFSEL10_Msk
GPIO_AFRH_AFSEL10_Pos
GPIO_AFRH_AFSEL11_0
GPIO_AFRH_AFSEL11_1
GPIO_AFRH_AFSEL11_2
GPIO_AFRH_AFSEL11_3
GPIO_AFRH_AFSEL11_Msk
GPIO_AFRH_AFSEL11_Pos
GPIO_AFRH_AFSEL12_0
GPIO_AFRH_AFSEL12_1
GPIO_AFRH_AFSEL12_2
GPIO_AFRH_AFSEL12_3
GPIO_AFRH_AFSEL12_Msk
GPIO_AFRH_AFSEL12_Pos
GPIO_AFRH_AFSEL13_0
GPIO_AFRH_AFSEL13_1
GPIO_AFRH_AFSEL13_2
GPIO_AFRH_AFSEL13_3
GPIO_AFRH_AFSEL13_Msk
GPIO_AFRH_AFSEL13_Pos
GPIO_AFRH_AFSEL14_0
GPIO_AFRH_AFSEL14_1
GPIO_AFRH_AFSEL14_2
GPIO_AFRH_AFSEL14_3
GPIO_AFRH_AFSEL14_Msk
GPIO_AFRH_AFSEL14_Pos
GPIO_AFRH_AFSEL15_0
GPIO_AFRH_AFSEL15_1
GPIO_AFRH_AFSEL15_2
GPIO_AFRH_AFSEL15_3
GPIO_AFRH_AFSEL15_Msk
GPIO_AFRH_AFSEL15_Pos
GPIO_AFRL_AFSEL0
GPIO_AFRL_AFSEL0_0
GPIO_AFRL_AFSEL0_1
GPIO_AFRL_AFSEL0_2
GPIO_AFRL_AFSEL0_3
GPIO_AFRL_AFSEL0_Msk
GPIO_AFRL_AFSEL0_Pos
GPIO_AFRL_AFSEL1
GPIO_AFRL_AFSEL2
GPIO_AFRL_AFSEL3
GPIO_AFRL_AFSEL4
GPIO_AFRL_AFSEL5
GPIO_AFRL_AFSEL6
GPIO_AFRL_AFSEL7
GPIO_AFRL_AFSEL1_0
GPIO_AFRL_AFSEL1_1
GPIO_AFRL_AFSEL1_2
GPIO_AFRL_AFSEL1_3
GPIO_AFRL_AFSEL1_Msk
GPIO_AFRL_AFSEL1_Pos
GPIO_AFRL_AFSEL2_0
GPIO_AFRL_AFSEL2_1
GPIO_AFRL_AFSEL2_2
GPIO_AFRL_AFSEL2_3
GPIO_AFRL_AFSEL2_Msk
GPIO_AFRL_AFSEL2_Pos
GPIO_AFRL_AFSEL3_0
GPIO_AFRL_AFSEL3_1
GPIO_AFRL_AFSEL3_2
GPIO_AFRL_AFSEL3_3
GPIO_AFRL_AFSEL3_Msk
GPIO_AFRL_AFSEL3_Pos
GPIO_AFRL_AFSEL4_0
GPIO_AFRL_AFSEL4_1
GPIO_AFRL_AFSEL4_2
GPIO_AFRL_AFSEL4_3
GPIO_AFRL_AFSEL4_Msk
GPIO_AFRL_AFSEL4_Pos
GPIO_AFRL_AFSEL5_0
GPIO_AFRL_AFSEL5_1
GPIO_AFRL_AFSEL5_2
GPIO_AFRL_AFSEL5_3
GPIO_AFRL_AFSEL5_Msk
GPIO_AFRL_AFSEL5_Pos
GPIO_AFRL_AFSEL6_0
GPIO_AFRL_AFSEL6_1
GPIO_AFRL_AFSEL6_2
GPIO_AFRL_AFSEL6_3
GPIO_AFRL_AFSEL6_Msk
GPIO_AFRL_AFSEL6_Pos
GPIO_AFRL_AFSEL7_0
GPIO_AFRL_AFSEL7_1
GPIO_AFRL_AFSEL7_2
GPIO_AFRL_AFSEL7_3
GPIO_AFRL_AFSEL7_Msk
GPIO_AFRL_AFSEL7_Pos
GPIO_BRR_BR0
GPIO_BRR_BR0_Msk
GPIO_BRR_BR0_Pos
GPIO_BRR_BR1
GPIO_BRR_BR2
GPIO_BRR_BR3
GPIO_BRR_BR4
GPIO_BRR_BR5
GPIO_BRR_BR6
GPIO_BRR_BR7
GPIO_BRR_BR8
GPIO_BRR_BR9
GPIO_BRR_BR1_Msk
GPIO_BRR_BR1_Pos
GPIO_BRR_BR2_Msk
GPIO_BRR_BR2_Pos
GPIO_BRR_BR3_Msk
GPIO_BRR_BR3_Pos
GPIO_BRR_BR4_Msk
GPIO_BRR_BR4_Pos
GPIO_BRR_BR5_Msk
GPIO_BRR_BR5_Pos
GPIO_BRR_BR6_Msk
GPIO_BRR_BR6_Pos
GPIO_BRR_BR7_Msk
GPIO_BRR_BR7_Pos
GPIO_BRR_BR8_Msk
GPIO_BRR_BR8_Pos
GPIO_BRR_BR9_Msk
GPIO_BRR_BR9_Pos
GPIO_BRR_BR10
GPIO_BRR_BR11
GPIO_BRR_BR12
GPIO_BRR_BR13
GPIO_BRR_BR14
GPIO_BRR_BR15
GPIO_BRR_BR10_Msk
GPIO_BRR_BR10_Pos
GPIO_BRR_BR11_Msk
GPIO_BRR_BR11_Pos
GPIO_BRR_BR12_Msk
GPIO_BRR_BR12_Pos
GPIO_BRR_BR13_Msk
GPIO_BRR_BR13_Pos
GPIO_BRR_BR14_Msk
GPIO_BRR_BR14_Pos
GPIO_BRR_BR15_Msk
GPIO_BRR_BR15_Pos
GPIO_BSRR_BR0
GPIO_BSRR_BR0_Msk
GPIO_BSRR_BR0_Pos
GPIO_BSRR_BR1
GPIO_BSRR_BR2
GPIO_BSRR_BR3
GPIO_BSRR_BR4
GPIO_BSRR_BR5
GPIO_BSRR_BR6
GPIO_BSRR_BR7
GPIO_BSRR_BR8
GPIO_BSRR_BR9
GPIO_BSRR_BR1_Msk
GPIO_BSRR_BR1_Pos
GPIO_BSRR_BR2_Msk
GPIO_BSRR_BR2_Pos
GPIO_BSRR_BR3_Msk
GPIO_BSRR_BR3_Pos
GPIO_BSRR_BR4_Msk
GPIO_BSRR_BR4_Pos
GPIO_BSRR_BR5_Msk
GPIO_BSRR_BR5_Pos
GPIO_BSRR_BR6_Msk
GPIO_BSRR_BR6_Pos
GPIO_BSRR_BR7_Msk
GPIO_BSRR_BR7_Pos
GPIO_BSRR_BR8_Msk
GPIO_BSRR_BR8_Pos
GPIO_BSRR_BR9_Msk
GPIO_BSRR_BR9_Pos
GPIO_BSRR_BR10
GPIO_BSRR_BR11
GPIO_BSRR_BR12
GPIO_BSRR_BR13
GPIO_BSRR_BR14
GPIO_BSRR_BR15
GPIO_BSRR_BR10_Msk
GPIO_BSRR_BR10_Pos
GPIO_BSRR_BR11_Msk
GPIO_BSRR_BR11_Pos
GPIO_BSRR_BR12_Msk
GPIO_BSRR_BR12_Pos
GPIO_BSRR_BR13_Msk
GPIO_BSRR_BR13_Pos
GPIO_BSRR_BR14_Msk
GPIO_BSRR_BR14_Pos
GPIO_BSRR_BR15_Msk
GPIO_BSRR_BR15_Pos
GPIO_BSRR_BS0
GPIO_BSRR_BS0_Msk
GPIO_BSRR_BS0_Pos
GPIO_BSRR_BS1
GPIO_BSRR_BS2
GPIO_BSRR_BS3
GPIO_BSRR_BS4
GPIO_BSRR_BS5
GPIO_BSRR_BS6
GPIO_BSRR_BS7
GPIO_BSRR_BS8
GPIO_BSRR_BS9
GPIO_BSRR_BS1_Msk
GPIO_BSRR_BS1_Pos
GPIO_BSRR_BS2_Msk
GPIO_BSRR_BS2_Pos
GPIO_BSRR_BS3_Msk
GPIO_BSRR_BS3_Pos
GPIO_BSRR_BS4_Msk
GPIO_BSRR_BS4_Pos
GPIO_BSRR_BS5_Msk
GPIO_BSRR_BS5_Pos
GPIO_BSRR_BS6_Msk
GPIO_BSRR_BS6_Pos
GPIO_BSRR_BS7_Msk
GPIO_BSRR_BS7_Pos
GPIO_BSRR_BS8_Msk
GPIO_BSRR_BS8_Pos
GPIO_BSRR_BS9_Msk
GPIO_BSRR_BS9_Pos
GPIO_BSRR_BS10
GPIO_BSRR_BS11
GPIO_BSRR_BS12
GPIO_BSRR_BS13
GPIO_BSRR_BS14
GPIO_BSRR_BS15
GPIO_BSRR_BS10_Msk
GPIO_BSRR_BS10_Pos
GPIO_BSRR_BS11_Msk
GPIO_BSRR_BS11_Pos
GPIO_BSRR_BS12_Msk
GPIO_BSRR_BS12_Pos
GPIO_BSRR_BS13_Msk
GPIO_BSRR_BS13_Pos
GPIO_BSRR_BS14_Msk
GPIO_BSRR_BS14_Pos
GPIO_BSRR_BS15_Msk
GPIO_BSRR_BS15_Pos
GPIO_IDR_ID0
GPIO_IDR_ID0_Msk
GPIO_IDR_ID0_Pos
GPIO_IDR_ID1
GPIO_IDR_ID2
GPIO_IDR_ID3
GPIO_IDR_ID4
GPIO_IDR_ID5
GPIO_IDR_ID6
GPIO_IDR_ID7
GPIO_IDR_ID8
GPIO_IDR_ID9
GPIO_IDR_ID1_Msk
GPIO_IDR_ID1_Pos
GPIO_IDR_ID2_Msk
GPIO_IDR_ID2_Pos
GPIO_IDR_ID3_Msk
GPIO_IDR_ID3_Pos
GPIO_IDR_ID4_Msk
GPIO_IDR_ID4_Pos
GPIO_IDR_ID5_Msk
GPIO_IDR_ID5_Pos
GPIO_IDR_ID6_Msk
GPIO_IDR_ID6_Pos
GPIO_IDR_ID7_Msk
GPIO_IDR_ID7_Pos
GPIO_IDR_ID8_Msk
GPIO_IDR_ID8_Pos
GPIO_IDR_ID9_Msk
GPIO_IDR_ID9_Pos
GPIO_IDR_ID10
GPIO_IDR_ID11
GPIO_IDR_ID12
GPIO_IDR_ID13
GPIO_IDR_ID14
GPIO_IDR_ID15
GPIO_IDR_ID10_Msk
GPIO_IDR_ID10_Pos
GPIO_IDR_ID11_Msk
GPIO_IDR_ID11_Pos
GPIO_IDR_ID12_Msk
GPIO_IDR_ID12_Pos
GPIO_IDR_ID13_Msk
GPIO_IDR_ID13_Pos
GPIO_IDR_ID14_Msk
GPIO_IDR_ID14_Pos
GPIO_IDR_ID15_Msk
GPIO_IDR_ID15_Pos
GPIO_LCKR_LCK0
GPIO_LCKR_LCK0_Msk
GPIO_LCKR_LCK0_Pos
GPIO_LCKR_LCK1
GPIO_LCKR_LCK2
GPIO_LCKR_LCK3
GPIO_LCKR_LCK4
GPIO_LCKR_LCK5
GPIO_LCKR_LCK6
GPIO_LCKR_LCK7
GPIO_LCKR_LCK8
GPIO_LCKR_LCK9
GPIO_LCKR_LCK1_Msk
GPIO_LCKR_LCK1_Pos
GPIO_LCKR_LCK2_Msk
GPIO_LCKR_LCK2_Pos
GPIO_LCKR_LCK3_Msk
GPIO_LCKR_LCK3_Pos
GPIO_LCKR_LCK4_Msk
GPIO_LCKR_LCK4_Pos
GPIO_LCKR_LCK5_Msk
GPIO_LCKR_LCK5_Pos
GPIO_LCKR_LCK6_Msk
GPIO_LCKR_LCK6_Pos
GPIO_LCKR_LCK7_Msk
GPIO_LCKR_LCK7_Pos
GPIO_LCKR_LCK8_Msk
GPIO_LCKR_LCK8_Pos
GPIO_LCKR_LCK9_Msk
GPIO_LCKR_LCK9_Pos
GPIO_LCKR_LCK10
GPIO_LCKR_LCK11
GPIO_LCKR_LCK12
GPIO_LCKR_LCK13
GPIO_LCKR_LCK14
GPIO_LCKR_LCK15
GPIO_LCKR_LCK10_Msk
GPIO_LCKR_LCK10_Pos
GPIO_LCKR_LCK11_Msk
GPIO_LCKR_LCK11_Pos
GPIO_LCKR_LCK12_Msk
GPIO_LCKR_LCK12_Pos
GPIO_LCKR_LCK13_Msk
GPIO_LCKR_LCK13_Pos
GPIO_LCKR_LCK14_Msk
GPIO_LCKR_LCK14_Pos
GPIO_LCKR_LCK15_Msk
GPIO_LCKR_LCK15_Pos
GPIO_LCKR_LCKK
GPIO_LCKR_LCKK_Msk
GPIO_LCKR_LCKK_Pos
GPIO_MODER_MODE0
GPIO_MODER_MODE0_0
GPIO_MODER_MODE0_1
GPIO_MODER_MODE0_Msk
GPIO_MODER_MODE0_Pos
GPIO_MODER_MODE1
GPIO_MODER_MODE2
GPIO_MODER_MODE3
GPIO_MODER_MODE4
GPIO_MODER_MODE5
GPIO_MODER_MODE6
GPIO_MODER_MODE7
GPIO_MODER_MODE8
GPIO_MODER_MODE9
GPIO_MODER_MODE1_0
GPIO_MODER_MODE1_1
GPIO_MODER_MODE1_Msk
GPIO_MODER_MODE1_Pos
GPIO_MODER_MODE2_0
GPIO_MODER_MODE2_1
GPIO_MODER_MODE2_Msk
GPIO_MODER_MODE2_Pos
GPIO_MODER_MODE3_0
GPIO_MODER_MODE3_1
GPIO_MODER_MODE3_Msk
GPIO_MODER_MODE3_Pos
GPIO_MODER_MODE4_0
GPIO_MODER_MODE4_1
GPIO_MODER_MODE4_Msk
GPIO_MODER_MODE4_Pos
GPIO_MODER_MODE5_0
GPIO_MODER_MODE5_1
GPIO_MODER_MODE5_Msk
GPIO_MODER_MODE5_Pos
GPIO_MODER_MODE6_0
GPIO_MODER_MODE6_1
GPIO_MODER_MODE6_Msk
GPIO_MODER_MODE6_Pos
GPIO_MODER_MODE7_0
GPIO_MODER_MODE7_1
GPIO_MODER_MODE7_Msk
GPIO_MODER_MODE7_Pos
GPIO_MODER_MODE8_0
GPIO_MODER_MODE8_1
GPIO_MODER_MODE8_Msk
GPIO_MODER_MODE8_Pos
GPIO_MODER_MODE9_0
GPIO_MODER_MODE9_1
GPIO_MODER_MODE9_Msk
GPIO_MODER_MODE9_Pos
GPIO_MODER_MODE10
GPIO_MODER_MODE11
GPIO_MODER_MODE12
GPIO_MODER_MODE13
GPIO_MODER_MODE14
GPIO_MODER_MODE15
GPIO_MODER_MODE10_0
GPIO_MODER_MODE10_1
GPIO_MODER_MODE10_Msk
GPIO_MODER_MODE10_Pos
GPIO_MODER_MODE11_0
GPIO_MODER_MODE11_1
GPIO_MODER_MODE11_Msk
GPIO_MODER_MODE11_Pos
GPIO_MODER_MODE12_0
GPIO_MODER_MODE12_1
GPIO_MODER_MODE12_Msk
GPIO_MODER_MODE12_Pos
GPIO_MODER_MODE13_0
GPIO_MODER_MODE13_1
GPIO_MODER_MODE13_Msk
GPIO_MODER_MODE13_Pos
GPIO_MODER_MODE14_0
GPIO_MODER_MODE14_1
GPIO_MODER_MODE14_Msk
GPIO_MODER_MODE14_Pos
GPIO_MODER_MODE15_0
GPIO_MODER_MODE15_1
GPIO_MODER_MODE15_Msk
GPIO_MODER_MODE15_Pos
GPIO_MODE_AF_OD
GPIO_MODE_AF_PP
GPIO_MODE_ANALOG
GPIO_MODE_EVT_FALLING
GPIO_MODE_EVT_RISING
GPIO_MODE_EVT_RISING_FALLING
GPIO_MODE_INPUT
GPIO_MODE_IT_FALLING
GPIO_MODE_IT_RISING
GPIO_MODE_IT_RISING_FALLING
GPIO_MODE_OUTPUT_OD
GPIO_MODE_OUTPUT_PP
GPIO_NOPULL
GPIO_ODR_OD0
GPIO_ODR_OD0_Msk
GPIO_ODR_OD0_Pos
GPIO_ODR_OD1
GPIO_ODR_OD2
GPIO_ODR_OD3
GPIO_ODR_OD4
GPIO_ODR_OD5
GPIO_ODR_OD6
GPIO_ODR_OD7
GPIO_ODR_OD8
GPIO_ODR_OD9
GPIO_ODR_OD1_Msk
GPIO_ODR_OD1_Pos
GPIO_ODR_OD2_Msk
GPIO_ODR_OD2_Pos
GPIO_ODR_OD3_Msk
GPIO_ODR_OD3_Pos
GPIO_ODR_OD4_Msk
GPIO_ODR_OD4_Pos
GPIO_ODR_OD5_Msk
GPIO_ODR_OD5_Pos
GPIO_ODR_OD6_Msk
GPIO_ODR_OD6_Pos
GPIO_ODR_OD7_Msk
GPIO_ODR_OD7_Pos
GPIO_ODR_OD8_Msk
GPIO_ODR_OD8_Pos
GPIO_ODR_OD9_Msk
GPIO_ODR_OD9_Pos
GPIO_ODR_OD10
GPIO_ODR_OD11
GPIO_ODR_OD12
GPIO_ODR_OD13
GPIO_ODR_OD14
GPIO_ODR_OD15
GPIO_ODR_OD10_Msk
GPIO_ODR_OD10_Pos
GPIO_ODR_OD11_Msk
GPIO_ODR_OD11_Pos
GPIO_ODR_OD12_Msk
GPIO_ODR_OD12_Pos
GPIO_ODR_OD13_Msk
GPIO_ODR_OD13_Pos
GPIO_ODR_OD14_Msk
GPIO_ODR_OD14_Pos
GPIO_ODR_OD15_Msk
GPIO_ODR_OD15_Pos
GPIO_OSPEEDR_OSPEED0
GPIO_OSPEEDR_OSPEED0_0
GPIO_OSPEEDR_OSPEED0_1
GPIO_OSPEEDR_OSPEED0_Msk
GPIO_OSPEEDR_OSPEED0_Pos
GPIO_OSPEEDR_OSPEED1
GPIO_OSPEEDR_OSPEED2
GPIO_OSPEEDR_OSPEED3
GPIO_OSPEEDR_OSPEED4
GPIO_OSPEEDR_OSPEED5
GPIO_OSPEEDR_OSPEED6
GPIO_OSPEEDR_OSPEED7
GPIO_OSPEEDR_OSPEED8
GPIO_OSPEEDR_OSPEED9
GPIO_OSPEEDR_OSPEED1_0
GPIO_OSPEEDR_OSPEED1_1
GPIO_OSPEEDR_OSPEED1_Msk
GPIO_OSPEEDR_OSPEED1_Pos
GPIO_OSPEEDR_OSPEED2_0
GPIO_OSPEEDR_OSPEED2_1
GPIO_OSPEEDR_OSPEED2_Msk
GPIO_OSPEEDR_OSPEED2_Pos
GPIO_OSPEEDR_OSPEED3_0
GPIO_OSPEEDR_OSPEED3_1
GPIO_OSPEEDR_OSPEED3_Msk
GPIO_OSPEEDR_OSPEED3_Pos
GPIO_OSPEEDR_OSPEED4_0
GPIO_OSPEEDR_OSPEED4_1
GPIO_OSPEEDR_OSPEED4_Msk
GPIO_OSPEEDR_OSPEED4_Pos
GPIO_OSPEEDR_OSPEED5_0
GPIO_OSPEEDR_OSPEED5_1
GPIO_OSPEEDR_OSPEED5_Msk
GPIO_OSPEEDR_OSPEED5_Pos
GPIO_OSPEEDR_OSPEED6_0
GPIO_OSPEEDR_OSPEED6_1
GPIO_OSPEEDR_OSPEED6_Msk
GPIO_OSPEEDR_OSPEED6_Pos
GPIO_OSPEEDR_OSPEED7_0
GPIO_OSPEEDR_OSPEED7_1
GPIO_OSPEEDR_OSPEED7_Msk
GPIO_OSPEEDR_OSPEED7_Pos
GPIO_OSPEEDR_OSPEED8_0
GPIO_OSPEEDR_OSPEED8_1
GPIO_OSPEEDR_OSPEED8_Msk
GPIO_OSPEEDR_OSPEED8_Pos
GPIO_OSPEEDR_OSPEED9_0
GPIO_OSPEEDR_OSPEED9_1
GPIO_OSPEEDR_OSPEED9_Msk
GPIO_OSPEEDR_OSPEED9_Pos
GPIO_OSPEEDR_OSPEED10
GPIO_OSPEEDR_OSPEED11
GPIO_OSPEEDR_OSPEED12
GPIO_OSPEEDR_OSPEED13
GPIO_OSPEEDR_OSPEED14
GPIO_OSPEEDR_OSPEED15
GPIO_OSPEEDR_OSPEED10_0
GPIO_OSPEEDR_OSPEED10_1
GPIO_OSPEEDR_OSPEED10_Msk
GPIO_OSPEEDR_OSPEED10_Pos
GPIO_OSPEEDR_OSPEED11_0
GPIO_OSPEEDR_OSPEED11_1
GPIO_OSPEEDR_OSPEED11_Msk
GPIO_OSPEEDR_OSPEED11_Pos
GPIO_OSPEEDR_OSPEED12_0
GPIO_OSPEEDR_OSPEED12_1
GPIO_OSPEEDR_OSPEED12_Msk
GPIO_OSPEEDR_OSPEED12_Pos
GPIO_OSPEEDR_OSPEED13_0
GPIO_OSPEEDR_OSPEED13_1
GPIO_OSPEEDR_OSPEED13_Msk
GPIO_OSPEEDR_OSPEED13_Pos
GPIO_OSPEEDR_OSPEED14_0
GPIO_OSPEEDR_OSPEED14_1
GPIO_OSPEEDR_OSPEED14_Msk
GPIO_OSPEEDR_OSPEED14_Pos
GPIO_OSPEEDR_OSPEED15_0
GPIO_OSPEEDR_OSPEED15_1
GPIO_OSPEEDR_OSPEED15_Msk
GPIO_OSPEEDR_OSPEED15_Pos
GPIO_OTYPER_OT0
GPIO_OTYPER_OT0_Msk
GPIO_OTYPER_OT0_Pos
GPIO_OTYPER_OT1
GPIO_OTYPER_OT2
GPIO_OTYPER_OT3
GPIO_OTYPER_OT4
GPIO_OTYPER_OT5
GPIO_OTYPER_OT6
GPIO_OTYPER_OT7
GPIO_OTYPER_OT8
GPIO_OTYPER_OT9
GPIO_OTYPER_OT1_Msk
GPIO_OTYPER_OT1_Pos
GPIO_OTYPER_OT2_Msk
GPIO_OTYPER_OT2_Pos
GPIO_OTYPER_OT3_Msk
GPIO_OTYPER_OT3_Pos
GPIO_OTYPER_OT4_Msk
GPIO_OTYPER_OT4_Pos
GPIO_OTYPER_OT5_Msk
GPIO_OTYPER_OT5_Pos
GPIO_OTYPER_OT6_Msk
GPIO_OTYPER_OT6_Pos
GPIO_OTYPER_OT7_Msk
GPIO_OTYPER_OT7_Pos
GPIO_OTYPER_OT8_Msk
GPIO_OTYPER_OT8_Pos
GPIO_OTYPER_OT9_Msk
GPIO_OTYPER_OT9_Pos
GPIO_OTYPER_OT10
GPIO_OTYPER_OT11
GPIO_OTYPER_OT12
GPIO_OTYPER_OT13
GPIO_OTYPER_OT14
GPIO_OTYPER_OT15
GPIO_OTYPER_OT10_Msk
GPIO_OTYPER_OT10_Pos
GPIO_OTYPER_OT11_Msk
GPIO_OTYPER_OT11_Pos
GPIO_OTYPER_OT12_Msk
GPIO_OTYPER_OT12_Pos
GPIO_OTYPER_OT13_Msk
GPIO_OTYPER_OT13_Pos
GPIO_OTYPER_OT14_Msk
GPIO_OTYPER_OT14_Pos
GPIO_OTYPER_OT15_Msk
GPIO_OTYPER_OT15_Pos
GPIO_PIN_0
GPIO_PIN_1
GPIO_PIN_2
GPIO_PIN_3
GPIO_PIN_4
GPIO_PIN_5
GPIO_PIN_6
GPIO_PIN_7
GPIO_PIN_8
GPIO_PIN_9
GPIO_PIN_10
GPIO_PIN_11
GPIO_PIN_12
GPIO_PIN_13
GPIO_PIN_14
GPIO_PIN_15
GPIO_PIN_All
GPIO_PIN_MASK
GPIO_PULLDOWN
GPIO_PULLUP
GPIO_PUPDR_PUPD0
GPIO_PUPDR_PUPD0_0
GPIO_PUPDR_PUPD0_1
GPIO_PUPDR_PUPD0_Msk
GPIO_PUPDR_PUPD0_Pos
GPIO_PUPDR_PUPD1
GPIO_PUPDR_PUPD2
GPIO_PUPDR_PUPD3
GPIO_PUPDR_PUPD4
GPIO_PUPDR_PUPD5
GPIO_PUPDR_PUPD6
GPIO_PUPDR_PUPD7
GPIO_PUPDR_PUPD8
GPIO_PUPDR_PUPD9
GPIO_PUPDR_PUPD1_0
GPIO_PUPDR_PUPD1_1
GPIO_PUPDR_PUPD1_Msk
GPIO_PUPDR_PUPD1_Pos
GPIO_PUPDR_PUPD2_0
GPIO_PUPDR_PUPD2_1
GPIO_PUPDR_PUPD2_Msk
GPIO_PUPDR_PUPD2_Pos
GPIO_PUPDR_PUPD3_0
GPIO_PUPDR_PUPD3_1
GPIO_PUPDR_PUPD3_Msk
GPIO_PUPDR_PUPD3_Pos
GPIO_PUPDR_PUPD4_0
GPIO_PUPDR_PUPD4_1
GPIO_PUPDR_PUPD4_Msk
GPIO_PUPDR_PUPD4_Pos
GPIO_PUPDR_PUPD5_0
GPIO_PUPDR_PUPD5_1
GPIO_PUPDR_PUPD5_Msk
GPIO_PUPDR_PUPD5_Pos
GPIO_PUPDR_PUPD6_0
GPIO_PUPDR_PUPD6_1
GPIO_PUPDR_PUPD6_Msk
GPIO_PUPDR_PUPD6_Pos
GPIO_PUPDR_PUPD7_0
GPIO_PUPDR_PUPD7_1
GPIO_PUPDR_PUPD7_Msk
GPIO_PUPDR_PUPD7_Pos
GPIO_PUPDR_PUPD8_0
GPIO_PUPDR_PUPD8_1
GPIO_PUPDR_PUPD8_Msk
GPIO_PUPDR_PUPD8_Pos
GPIO_PUPDR_PUPD9_0
GPIO_PUPDR_PUPD9_1
GPIO_PUPDR_PUPD9_Msk
GPIO_PUPDR_PUPD9_Pos
GPIO_PUPDR_PUPD10
GPIO_PUPDR_PUPD11
GPIO_PUPDR_PUPD12
GPIO_PUPDR_PUPD13
GPIO_PUPDR_PUPD14
GPIO_PUPDR_PUPD15
GPIO_PUPDR_PUPD10_0
GPIO_PUPDR_PUPD10_1
GPIO_PUPDR_PUPD10_Msk
GPIO_PUPDR_PUPD10_Pos
GPIO_PUPDR_PUPD11_0
GPIO_PUPDR_PUPD11_1
GPIO_PUPDR_PUPD11_Msk
GPIO_PUPDR_PUPD11_Pos
GPIO_PUPDR_PUPD12_0
GPIO_PUPDR_PUPD12_1
GPIO_PUPDR_PUPD12_Msk
GPIO_PUPDR_PUPD12_Pos
GPIO_PUPDR_PUPD13_0
GPIO_PUPDR_PUPD13_1
GPIO_PUPDR_PUPD13_Msk
GPIO_PUPDR_PUPD13_Pos
GPIO_PUPDR_PUPD14_0
GPIO_PUPDR_PUPD14_1
GPIO_PUPDR_PUPD14_Msk
GPIO_PUPDR_PUPD14_Pos
GPIO_PUPDR_PUPD15_0
GPIO_PUPDR_PUPD15_1
GPIO_PUPDR_PUPD15_Msk
GPIO_PUPDR_PUPD15_Pos
GPIO_PinState_GPIO_PIN_RESET
GPIO_PinState_GPIO_PIN_SET
GPIO_SPEED_FREQ_HIGH
GPIO_SPEED_FREQ_LOW
GPIO_SPEED_FREQ_MEDIUM
GPIO_SPEED_FREQ_VERY_HIGH
HAL_ADC_ERROR_DMA
HAL_ADC_ERROR_INTERNAL
HAL_ADC_ERROR_NONE
HAL_ADC_ERROR_OVR
HAL_ADC_STATE_AWD1
HAL_ADC_STATE_AWD2
HAL_ADC_STATE_AWD3
HAL_ADC_STATE_BUSY_INTERNAL
HAL_ADC_STATE_ERROR_CONFIG
HAL_ADC_STATE_ERROR_DMA
HAL_ADC_STATE_ERROR_INTERNAL
HAL_ADC_STATE_INJ_BUSY
HAL_ADC_STATE_INJ_EOC
HAL_ADC_STATE_INJ_JQOVF
HAL_ADC_STATE_MULTIMODE_SLAVE
HAL_ADC_STATE_READY
HAL_ADC_STATE_REG_BUSY
HAL_ADC_STATE_REG_EOC
HAL_ADC_STATE_REG_EOSMP
HAL_ADC_STATE_REG_OVR
HAL_ADC_STATE_RESET
HAL_ADC_STATE_TIMEOUT
HAL_CRC_StateTypeDef_HAL_CRC_STATE_BUSY
< CRC internal process is ongoing
HAL_CRC_StateTypeDef_HAL_CRC_STATE_ERROR
< CRC error state
HAL_CRC_StateTypeDef_HAL_CRC_STATE_READY
< CRC initialized and ready for use
HAL_CRC_StateTypeDef_HAL_CRC_STATE_RESET
< CRC not yet initialized or disabled
HAL_CRC_StateTypeDef_HAL_CRC_STATE_TIMEOUT
< CRC timeout state
HAL_DMA_CallbackIDTypeDef_HAL_DMA_XFER_ABORT_CB_ID
< Abort
HAL_DMA_CallbackIDTypeDef_HAL_DMA_XFER_ALL_CB_ID
< All
HAL_DMA_CallbackIDTypeDef_HAL_DMA_XFER_CPLT_CB_ID
< Full transfer
HAL_DMA_CallbackIDTypeDef_HAL_DMA_XFER_ERROR_CB_ID
< Error
HAL_DMA_CallbackIDTypeDef_HAL_DMA_XFER_HALFCPLT_CB_ID
< Half transfer
HAL_DMA_ERROR_NONE
HAL_DMA_ERROR_NOT_SUPPORTED
HAL_DMA_ERROR_NO_XFER
HAL_DMA_ERROR_TE
HAL_DMA_ERROR_TIMEOUT
HAL_DMA_LevelCompleteTypeDef_HAL_DMA_FULL_TRANSFER
< Full transfer
HAL_DMA_LevelCompleteTypeDef_HAL_DMA_HALF_TRANSFER
< Half Transfer
HAL_DMA_StateTypeDef_HAL_DMA_STATE_BUSY
< DMA process is ongoing
HAL_DMA_StateTypeDef_HAL_DMA_STATE_READY
< DMA initialized and ready for use
HAL_DMA_StateTypeDef_HAL_DMA_STATE_RESET
< DMA not yet initialized or disabled
HAL_DMA_StateTypeDef_HAL_DMA_STATE_TIMEOUT
< DMA timeout state
HAL_FLASH_ERROR_NONE
HAL_FLASH_ERROR_OPTV
HAL_FLASH_ERROR_WRP
HAL_I2C_ERROR_AF
HAL_I2C_ERROR_ARLO
HAL_I2C_ERROR_BERR
HAL_I2C_ERROR_DMA
HAL_I2C_ERROR_DMA_PARAM
HAL_I2C_ERROR_NONE
HAL_I2C_ERROR_OVR
HAL_I2C_ERROR_SIZE
HAL_I2C_ERROR_TIMEOUT
HAL_I2C_ModeTypeDef_HAL_I2C_MODE_MASTER
< I2C communication is in Master Mode
HAL_I2C_ModeTypeDef_HAL_I2C_MODE_MEM
< I2C communication is in Memory Mode
HAL_I2C_ModeTypeDef_HAL_I2C_MODE_NONE
< No I2C communication on going
HAL_I2C_ModeTypeDef_HAL_I2C_MODE_SLAVE
< I2C communication is in Slave Mode
HAL_I2C_StateTypeDef_HAL_I2C_STATE_ABORT
< Abort user request ongoing
HAL_I2C_StateTypeDef_HAL_I2C_STATE_BUSY
< An internal process is ongoing
HAL_I2C_StateTypeDef_HAL_I2C_STATE_BUSY_RX
< Data Reception process is ongoing
HAL_I2C_StateTypeDef_HAL_I2C_STATE_BUSY_RX_LISTEN
< Address Listen Mode and Data Reception process is ongoing
HAL_I2C_StateTypeDef_HAL_I2C_STATE_BUSY_TX
< Data Transmission process is ongoing
HAL_I2C_StateTypeDef_HAL_I2C_STATE_BUSY_TX_LISTEN
< Address Listen Mode and Data Transmission process is ongoing
HAL_I2C_StateTypeDef_HAL_I2C_STATE_ERROR
< Error
HAL_I2C_StateTypeDef_HAL_I2C_STATE_LISTEN
< Address Listen Mode is ongoing
HAL_I2C_StateTypeDef_HAL_I2C_STATE_READY
< Peripheral Initialized and ready for use
HAL_I2C_StateTypeDef_HAL_I2C_STATE_RESET
< Peripheral is not yet Initialized
HAL_I2C_StateTypeDef_HAL_I2C_STATE_TIMEOUT
< Timeout state
HAL_LED_StateTypeDef_HAL_LED_STATE_BUSY
< an internal process is ongoing
HAL_LED_StateTypeDef_HAL_LED_STATE_ERROR
< Error
HAL_LED_StateTypeDef_HAL_LED_STATE_READY
< Peripheral Initialized and ready for use
HAL_LED_StateTypeDef_HAL_LED_STATE_RESET
< Peripheral is not yet Initialized
HAL_LED_StateTypeDef_HAL_LED_STATE_TIMEOUT
< Timeout state
HAL_LPTIM_StateTypeDef_HAL_LPTIM_STATE_BUSY
< An internal process is ongoing
HAL_LPTIM_StateTypeDef_HAL_LPTIM_STATE_ERROR
< Internal Process is ongoing
HAL_LPTIM_StateTypeDef_HAL_LPTIM_STATE_READY
< Peripheral Initialized and ready for use
HAL_LPTIM_StateTypeDef_HAL_LPTIM_STATE_RESET
< Peripheral not yet initialized or disabled
HAL_LPTIM_StateTypeDef_HAL_LPTIM_STATE_TIMEOUT
< Timeout state
HAL_LockTypeDef_HAL_LOCKED
HAL_LockTypeDef_HAL_UNLOCKED
HAL_MAX_DELAY
HAL_RTCStateTypeDef_HAL_RTC_STATE_BUSY
< RTC process is ongoing
HAL_RTCStateTypeDef_HAL_RTC_STATE_ERROR
< RTC error state
HAL_RTCStateTypeDef_HAL_RTC_STATE_READY
< RTC initialized and ready for use
HAL_RTCStateTypeDef_HAL_RTC_STATE_RESET
< RTC not yet initialized or disabled
HAL_RTCStateTypeDef_HAL_RTC_STATE_TIMEOUT
< RTC timeout state
HAL_SPI_ERROR_ABORT
HAL_SPI_ERROR_DMA
HAL_SPI_ERROR_FLAG
HAL_SPI_ERROR_FRE
HAL_SPI_ERROR_MODF
HAL_SPI_ERROR_NONE
HAL_SPI_ERROR_OVR
HAL_SPI_StateTypeDef_HAL_SPI_STATE_ABORT
< SPI abort is ongoing
HAL_SPI_StateTypeDef_HAL_SPI_STATE_BUSY
< an internal process is ongoing
HAL_SPI_StateTypeDef_HAL_SPI_STATE_BUSY_RX
< Data Reception process is ongoing
HAL_SPI_StateTypeDef_HAL_SPI_STATE_BUSY_TX
< Data Transmission process is ongoing
HAL_SPI_StateTypeDef_HAL_SPI_STATE_BUSY_TX_RX
< Data Transmission and Reception process is ongoing
HAL_SPI_StateTypeDef_HAL_SPI_STATE_ERROR
< SPI error state
HAL_SPI_StateTypeDef_HAL_SPI_STATE_READY
< Peripheral Initialized and ready for use
HAL_SPI_StateTypeDef_HAL_SPI_STATE_RESET
< Peripheral not Initialized
HAL_StatusTypeDef_HAL_BUSY
HAL_StatusTypeDef_HAL_ERROR
HAL_StatusTypeDef_HAL_OK
HAL_StatusTypeDef_HAL_TIMEOUT
HAL_TIM_ActiveChannel_HAL_TIM_ACTIVE_CHANNEL_1
< The active channel is 1
HAL_TIM_ActiveChannel_HAL_TIM_ACTIVE_CHANNEL_2
< The active channel is 2
HAL_TIM_ActiveChannel_HAL_TIM_ACTIVE_CHANNEL_3
< The active channel is 3
HAL_TIM_ActiveChannel_HAL_TIM_ACTIVE_CHANNEL_4
< The active channel is 4
HAL_TIM_ActiveChannel_HAL_TIM_ACTIVE_CHANNEL_CLEARED
< All active channels cleared
HAL_TIM_StateTypeDef_HAL_TIM_STATE_BUSY
< An internal process is ongoing
HAL_TIM_StateTypeDef_HAL_TIM_STATE_ERROR
< Reception process is ongoing
HAL_TIM_StateTypeDef_HAL_TIM_STATE_READY
< Peripheral Initialized and ready for use
HAL_TIM_StateTypeDef_HAL_TIM_STATE_RESET
< Peripheral not yet initialized or disabled
HAL_TIM_StateTypeDef_HAL_TIM_STATE_TIMEOUT
< Timeout state
HAL_TickFreqTypeDef_HAL_TICK_FREQ_1KHZ
HAL_TickFreqTypeDef_HAL_TICK_FREQ_10HZ
HAL_TickFreqTypeDef_HAL_TICK_FREQ_100HZ
HAL_TickFreqTypeDef_HAL_TICK_FREQ_DEFAULT
HAL_UART_ERROR_DMA
HAL_UART_ERROR_FE
HAL_UART_ERROR_NE
HAL_UART_ERROR_NONE
HAL_UART_ERROR_ORE
HAL_UART_ERROR_PE
HAL_UART_StateTypeDef_HAL_UART_STATE_BUSY
< an internal process is ongoing Value is allowed for gState only
HAL_UART_StateTypeDef_HAL_UART_STATE_BUSY_RX
< Data Reception process is ongoing Value is allowed for RxState only
HAL_UART_StateTypeDef_HAL_UART_STATE_BUSY_TX
< Data Transmission process is ongoing Value is allowed for gState only
HAL_UART_StateTypeDef_HAL_UART_STATE_BUSY_TX_RX
< Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values
HAL_UART_StateTypeDef_HAL_UART_STATE_ERROR
< Error Value is allowed for gState only
HAL_UART_StateTypeDef_HAL_UART_STATE_READY
< Peripheral Initialized and ready for use Value is allowed for gState and RxState
HAL_UART_StateTypeDef_HAL_UART_STATE_RESET
< Peripheral is not yet Initialized Value is allowed for gState and RxState
HAL_UART_StateTypeDef_HAL_UART_STATE_TIMEOUT
< Timeout state Value is allowed for gState only
HSE_STARTUP_TIMEOUT
HSE_VALUE
HSI_VALUE
I2C
I2C1
I2C_BASE
I2C_CCR_CCR
I2C_CCR_CCR_Msk
I2C_CCR_CCR_Pos
I2C_CCR_DUTY
I2C_CCR_DUTY_Msk
I2C_CCR_DUTY_Pos
I2C_CCR_FS
I2C_CCR_FS_Msk
I2C_CCR_FS_Pos
I2C_CR1_ACK
I2C_CR1_ACK_Msk
I2C_CR1_ACK_Pos
I2C_CR1_ENGC
I2C_CR1_ENGC_Msk
I2C_CR1_ENGC_Pos
I2C_CR1_NOSTRETCH
I2C_CR1_NOSTRETCH_Msk
I2C_CR1_NOSTRETCH_Pos
I2C_CR1_PE
I2C_CR1_PE_Msk
I2C_CR1_PE_Pos
I2C_CR1_POS
I2C_CR1_POS_Msk
I2C_CR1_POS_Pos
I2C_CR1_START
I2C_CR1_START_Msk
I2C_CR1_START_Pos
I2C_CR1_STOP
I2C_CR1_STOP_Msk
I2C_CR1_STOP_Pos
I2C_CR1_SWRST
I2C_CR1_SWRST_Msk
I2C_CR1_SWRST_Pos
I2C_CR2_DMAEN
I2C_CR2_DMAEN_Msk
I2C_CR2_DMAEN_Pos
I2C_CR2_FREQ
I2C_CR2_FREQ_0
I2C_CR2_FREQ_1
I2C_CR2_FREQ_2
I2C_CR2_FREQ_3
I2C_CR2_FREQ_4
I2C_CR2_FREQ_5
I2C_CR2_FREQ_Msk
I2C_CR2_FREQ_Pos
I2C_CR2_ITBUFEN
I2C_CR2_ITBUFEN_Msk
I2C_CR2_ITBUFEN_Pos
I2C_CR2_ITERREN
I2C_CR2_ITERREN_Msk
I2C_CR2_ITERREN_Pos
I2C_CR2_ITEVTEN
I2C_CR2_ITEVTEN_Msk
I2C_CR2_ITEVTEN_Pos
I2C_CR2_LAST
I2C_CR2_LAST_Msk
I2C_CR2_LAST_Pos
I2C_DIRECTION_RECEIVE
I2C_DIRECTION_TRANSMIT
I2C_DR_DR
I2C_DR_DR_0
I2C_DR_DR_1
I2C_DR_DR_2
I2C_DR_DR_3
I2C_DR_DR_4
I2C_DR_DR_5
I2C_DR_DR_6
I2C_DR_DR_7
I2C_DR_DR_Msk
I2C_DR_DR_Pos
I2C_DUTYCYCLE_2
I2C_DUTYCYCLE_16_9
I2C_FIRST_AND_LAST_FRAME
I2C_FIRST_AND_NEXT_FRAME
I2C_FIRST_FRAME
I2C_FLAG_ADD10
I2C_FLAG_ADDR
I2C_FLAG_AF
I2C_FLAG_ARLO
I2C_FLAG_BERR
I2C_FLAG_BTF
I2C_FLAG_BUSY
I2C_FLAG_DUALF
I2C_FLAG_GENCALL
I2C_FLAG_MASK
I2C_FLAG_MSL
I2C_FLAG_OVR
I2C_FLAG_RXNE
I2C_FLAG_SB
I2C_FLAG_STOPF
I2C_FLAG_TRA
I2C_FLAG_TXE
I2C_GENERALCALL_DISABLE
I2C_GENERALCALL_ENABLE
I2C_IT_BUF
I2C_IT_ERR
I2C_IT_EVT
I2C_LAST_FRAME
I2C_LAST_FRAME_NO_STOP
I2C_MEMADD_SIZE_8BIT
I2C_MEMADD_SIZE_16BIT
I2C_MIN_PCLK_FREQ_FAST
I2C_MIN_PCLK_FREQ_STANDARD
I2C_NEXT_FRAME
I2C_NOSTRETCH_DISABLE
I2C_NOSTRETCH_ENABLE
I2C_OAR1_ADD1
I2C_OAR1_ADD2
I2C_OAR1_ADD3
I2C_OAR1_ADD4
I2C_OAR1_ADD5
I2C_OAR1_ADD6
I2C_OAR1_ADD7
I2C_OAR1_ADD1_7
I2C_OAR1_ADD1_Msk
I2C_OAR1_ADD1_Pos
I2C_OAR1_ADD2_Msk
I2C_OAR1_ADD2_Pos
I2C_OAR1_ADD3_Msk
I2C_OAR1_ADD3_Pos
I2C_OAR1_ADD4_Msk
I2C_OAR1_ADD4_Pos
I2C_OAR1_ADD5_Msk
I2C_OAR1_ADD5_Pos
I2C_OAR1_ADD6_Msk
I2C_OAR1_ADD6_Pos
I2C_OAR1_ADD7_Msk
I2C_OAR1_ADD7_Pos
I2C_OTHER_AND_LAST_FRAME
I2C_OTHER_FRAME
I2C_SR1_ADDR
I2C_SR1_ADDR_Msk
I2C_SR1_ADDR_Pos
I2C_SR1_AF
I2C_SR1_AF_Msk
I2C_SR1_AF_Pos
I2C_SR1_ARLO
I2C_SR1_ARLO_Msk
I2C_SR1_ARLO_Pos
I2C_SR1_BERR
I2C_SR1_BERR_Msk
I2C_SR1_BERR_Pos
I2C_SR1_BTF
I2C_SR1_BTF_Msk
I2C_SR1_BTF_Pos
I2C_SR1_OVR
I2C_SR1_OVR_Msk
I2C_SR1_OVR_Pos
I2C_SR1_PECERR
I2C_SR1_PECERR_Msk
I2C_SR1_PECERR_Pos
I2C_SR1_RXNE
I2C_SR1_RXNE_Msk
I2C_SR1_RXNE_Pos
I2C_SR1_SB
I2C_SR1_SB_Msk
I2C_SR1_SB_Pos
I2C_SR1_STOPF
I2C_SR1_STOPF_Msk
I2C_SR1_STOPF_Pos
I2C_SR1_TXE
I2C_SR1_TXE_Msk
I2C_SR1_TXE_Pos
I2C_SR2_BUSY
I2C_SR2_BUSY_Msk
I2C_SR2_BUSY_Pos
I2C_SR2_GENCALL
I2C_SR2_GENCALL_Msk
I2C_SR2_GENCALL_Pos
I2C_SR2_MSL
I2C_SR2_MSL_Msk
I2C_SR2_MSL_Pos
I2C_SR2_PEC
I2C_SR2_PEC_Msk
I2C_SR2_PEC_Pos
I2C_SR2_TRA
I2C_SR2_TRA_Msk
I2C_SR2_TRA_Pos
I2C_TRISE_TRISE
I2C_TRISE_TRISE_Msk
I2C_TRISE_TRISE_Pos
IOPORT_BASE
IPSR_ISR_Msk
IPSR_ISR_Pos
IRQn_Type_ADC_COMP_IRQn
< ADC&COMP Interrupts
IRQn_Type_DMA1_Channel1_IRQn
< DMA1 Channel 1 Interrupt
IRQn_Type_DMA1_Channel2_3_IRQn
< DMA1 Channel 2 and Channel 3 Interrupts
IRQn_Type_EXTI0_1_IRQn
< EXTI 0 and 1 Interrupts
IRQn_Type_EXTI2_3_IRQn
< EXTI Line 2 and 3 Interrupts
IRQn_Type_EXTI4_15_IRQn
< EXTI Line 4 to 15 Interrupts
IRQn_Type_FLASH_IRQn
< FLASH global Interrupt
IRQn_Type_HardFault_IRQn
< 3 Cortex-M Hard Fault Interrupt
IRQn_Type_I2C1_IRQn
< I2C1 Interrupt (combined with EXTI 23)
IRQn_Type_LED_IRQn
< LED global Interrupt
IRQn_Type_LPTIM1_IRQn
< LPTIM1 global Interrupts
IRQn_Type_NonMaskableInt_IRQn
< 2 Non Maskable Interrupt
IRQn_Type_PVD_IRQn
< PVD through EXTI Line detection Interrupt(EXTI line 16)
IRQn_Type_PendSV_IRQn
< 14 Cortex-M Pend SV Interrupt
IRQn_Type_RCC_IRQn
< RCC global Interrupt
IRQn_Type_RTC_IRQn
< RTC interrupt through the EXTI line 19
IRQn_Type_SPI1_IRQn
< SPI1 Interrupt
IRQn_Type_SPI2_IRQn
< SPI2 Interrupt
IRQn_Type_SVC_IRQn
< 11 Cortex-M SV Call Interrupt
IRQn_Type_SysTick_IRQn
< 15 Cortex-M System Tick Interrupt
IRQn_Type_TIM1_BRK_UP_TRG_COM_IRQn
< TIM1 Break, Update, Trigger and Commutation Interrupts
IRQn_Type_TIM1_CC_IRQn
< TIM1 Capture Compare Interrupt
IRQn_Type_TIM3_IRQn
< TIM3 global Interrupt
IRQn_Type_TIM14_IRQn
< TIM14 global Interrupt
IRQn_Type_TIM16_IRQn
< TIM16 global Interrupt
IRQn_Type_TIM17_IRQn
< TIM17 global Interrupt
IRQn_Type_USART1_IRQn
< USART1 Interrupt
IRQn_Type_USART2_IRQn
< USART2 Interrupt
IRQn_Type_WWDG_IRQn
< Window WatchDog Interrupt
IWDG
IWDG_BASE
IWDG_KEY_ENABLE
IWDG_KEY_RELOAD
IWDG_KEY_WRITE_ACCESS_DISABLE
IWDG_KEY_WRITE_ACCESS_ENABLE
IWDG_KR_KEY
IWDG_KR_KEY_Msk
IWDG_KR_KEY_Pos
IWDG_PRESCALER_4
IWDG_PRESCALER_8
IWDG_PRESCALER_16
IWDG_PRESCALER_32
IWDG_PRESCALER_64
IWDG_PRESCALER_128
IWDG_PRESCALER_256
IWDG_PR_PR
IWDG_PR_PR_0
IWDG_PR_PR_1
IWDG_PR_PR_2
IWDG_PR_PR_Msk
IWDG_PR_PR_Pos
IWDG_RLR_RL
IWDG_RLR_RL_Msk
IWDG_RLR_RL_Pos
IWDG_SR_PVU
IWDG_SR_PVU_Msk
IWDG_SR_PVU_Pos
IWDG_SR_RVU
IWDG_SR_RVU_Msk
IWDG_SR_RVU_Pos
LED
LED_BASE
LED_COM0
LED_COM1
LED_COM2
LED_COM3
LED_COMDRIVE_HIGH
LED_COMDRIVE_LOW
LED_COM_ALL
LED_CR_EHS
LED_CR_EHS_Msk
LED_CR_EHS_Pos
LED_CR_IE
LED_CR_IE_Msk
LED_CR_IE_Pos
LED_CR_LEDON
LED_CR_LEDON_Msk
LED_CR_LEDON_Pos
LED_CR_LED_COM_SEL
LED_CR_LED_COM_SEL_0
LED_CR_LED_COM_SEL_1
LED_CR_LED_COM_SEL_Msk
LED_CR_LED_COM_SEL_Pos
LED_DISP_0
LED_DISP_1
LED_DISP_2
LED_DISP_3
LED_DISP_4
LED_DISP_5
LED_DISP_6
LED_DISP_7
LED_DISP_8
LED_DISP_9
LED_DISP_A
LED_DISP_B
LED_DISP_C
LED_DISP_D
LED_DISP_DOT
LED_DISP_E
LED_DISP_F
LED_DISP_FULL
LED_DISP_H
LED_DISP_NONE
LED_DISP_P
LED_DISP_U
LED_DR0_DATA0
LED_DR0_DATA0_A
LED_DR0_DATA0_B
LED_DR0_DATA0_C
LED_DR0_DATA0_D
LED_DR0_DATA0_DP
LED_DR0_DATA0_E
LED_DR0_DATA0_F
LED_DR0_DATA0_G
LED_DR0_DATA0_Msk
LED_DR0_DATA0_Pos
LED_DR1_DATA1
LED_DR1_DATA1_A
LED_DR1_DATA1_B
LED_DR1_DATA1_C
LED_DR1_DATA1_D
LED_DR1_DATA1_DP
LED_DR1_DATA1_E
LED_DR1_DATA1_F
LED_DR1_DATA1_G
LED_DR1_DATA1_Msk
LED_DR1_DATA1_Pos
LED_DR2_DATA2
LED_DR2_DATA2_A
LED_DR2_DATA2_B
LED_DR2_DATA2_C
LED_DR2_DATA2_D
LED_DR2_DATA2_DP
LED_DR2_DATA2_E
LED_DR2_DATA2_F
LED_DR2_DATA2_G
LED_DR2_DATA2_Msk
LED_DR2_DATA2_Pos
LED_DR3_DATA3
LED_DR3_DATA3_A
LED_DR3_DATA3_B
LED_DR3_DATA3_C
LED_DR3_DATA3_D
LED_DR3_DATA3_DP
LED_DR3_DATA3_E
LED_DR3_DATA3_F
LED_DR3_DATA3_G
LED_DR3_DATA3_Msk
LED_DR3_DATA3_Pos
LED_IR_FLAG
LED_IR_FLAG_Msk
LED_IR_FLAG_Pos
LED_PR_PR
LED_PR_PR_0
LED_PR_PR_1
LED_PR_PR_2
LED_PR_PR_3
LED_PR_PR_4
LED_PR_PR_5
LED_PR_PR_6
LED_PR_PR_7
LED_PR_PR_Msk
LED_PR_PR_Pos
LED_TR_T1
LED_TR_T2
LED_TR_T1_0
LED_TR_T1_1
LED_TR_T1_2
LED_TR_T1_3
LED_TR_T1_4
LED_TR_T1_5
LED_TR_T1_6
LED_TR_T1_7
LED_TR_T1_Msk
LED_TR_T1_Pos
LED_TR_T2_0
LED_TR_T2_1
LED_TR_T2_2
LED_TR_T2_3
LED_TR_T2_4
LED_TR_T2_5
LED_TR_T2_6
LED_TR_T2_7
LED_TR_T2_Msk
LED_TR_T2_Pos
LPTIM
LPTIM1
LPTIM_ARR_ARR
LPTIM_ARR_ARR_Msk
LPTIM_ARR_ARR_Pos
LPTIM_BASE
LPTIM_CFGR_PRELOAD
LPTIM_CFGR_PRELOAD_Msk
LPTIM_CFGR_PRELOAD_Pos
LPTIM_CFGR_PRESC
LPTIM_CFGR_PRESC_0
LPTIM_CFGR_PRESC_1
LPTIM_CFGR_PRESC_2
LPTIM_CFGR_PRESC_Msk
LPTIM_CFGR_PRESC_Pos
LPTIM_CNT_CNT
LPTIM_CNT_CNT_Msk
LPTIM_CNT_CNT_Pos
LPTIM_CR_ENABLE
LPTIM_CR_ENABLE_Msk
LPTIM_CR_ENABLE_Pos
LPTIM_CR_RSTARE
LPTIM_CR_RSTARE_Msk
LPTIM_CR_RSTARE_Pos
LPTIM_CR_SNGSTRT
LPTIM_CR_SNGSTRT_Msk
LPTIM_CR_SNGSTRT_Pos
LPTIM_FLAG_ARRM
LPTIM_ICR_ARRMCF
LPTIM_ICR_ARRMCF_Msk
LPTIM_ICR_ARRMCF_Pos
LPTIM_IER_ARRMIE
LPTIM_IER_ARRMIE_Msk
LPTIM_IER_ARRMIE_Pos
LPTIM_ISR_ARRM
LPTIM_ISR_ARRM_Msk
LPTIM_ISR_ARRM_Pos
LPTIM_IT_ARRM
LPTIM_PRESCALER_DIV1
LPTIM_PRESCALER_DIV2
LPTIM_PRESCALER_DIV4
LPTIM_PRESCALER_DIV8
LPTIM_PRESCALER_DIV16
LPTIM_PRESCALER_DIV32
LPTIM_PRESCALER_DIV64
LPTIM_PRESCALER_DIV128
LPTIM_UPDATE_ENDOFPERIOD
LPTIM_UPDATE_IMMEDIATE
LSE_STARTUP_TIMEOUT
LSE_VALUE
LSI_VALUE
NVIC
NVIC_BASE
OB
OB_BASE
OB_BOOT1_SRAM
OB_BOOT1_SYSTEM
OB_BOR_DISABLE
OB_BOR_ENABLE
OB_BOR_LEVEL_1p7_1p8
OB_BOR_LEVEL_1p9_2p0
OB_BOR_LEVEL_2p1_2p2
OB_BOR_LEVEL_2p3_2p4
OB_BOR_LEVEL_2p5_2p6
OB_BOR_LEVEL_2p7_2p8
OB_BOR_LEVEL_2p9_3p0
OB_BOR_LEVEL_3p1_3p2
OB_IWDG_HW
OB_IWDG_SW
OB_RDP_LEVEL_0
OB_RDP_LEVEL_1
OB_RESET_MODE_GPIO
OB_RESET_MODE_RESET
OB_USER_ALL
OB_USER_BOR_EN
OB_USER_BOR_LEV
OB_USER_IWDG_SW
OB_USER_NRST_MODE
OB_USER_WWDG_SW
OB_USER_nBOOT1
OB_WRPSTATE_DISABLE
OB_WRPSTATE_ENABLE
OB_WRP_AllPages
OB_WRP_Pages0to31
OB_WRP_Pages32to63
OB_WRP_Pages64to95
OB_WRP_Pages96to127
OB_WRP_Pages128to159
OB_WRP_Pages160to191
OB_WRP_Pages192to223
OB_WRP_Pages224to255
OB_WRP_Pages256to287
OB_WRP_Pages288to319
OB_WRP_Pages320to351
OB_WRP_Pages352to383
OB_WRP_Pages384to415
OB_WRP_Pages416to447
OB_WRP_Pages448to479
OB_WRP_Pages480to511
OB_WRP_SECTOR_0
OB_WRP_SECTOR_1
OB_WRP_SECTOR_2
OB_WRP_SECTOR_3
OB_WRP_SECTOR_4
OB_WRP_SECTOR_5
OB_WRP_SECTOR_6
OB_WRP_SECTOR_7
OB_WRP_SECTOR_8
OB_WRP_SECTOR_9
OB_WRP_SECTOR_10
OB_WRP_SECTOR_11
OB_WRP_SECTOR_12
OB_WRP_SECTOR_13
OB_WRP_SECTOR_14
OB_WRP_SECTOR_15
OB_WWDG_HW
OB_WWDG_SW
OPTIONBYTE_ALL
OPTIONBYTE_RDP
OPTIONBYTE_SDK
OPTIONBYTE_USER
OPTIONBYTE_WRP
PERIPH_BASE
PREFETCH_ENABLE
PRIORITY_HIGH
PRIORITY_HIGHEST
PRIORITY_LOW
PRIORITY_LOWEST
PWR
PWR_BASE
PWR_BIAS_CURRENTS_FROM_BIAS_CR
PWR_BIAS_CURRENTS_FROM_FACTORY_BYTES
PWR_CR1_BIAS_CR
PWR_CR1_BIAS_CR_0
PWR_CR1_BIAS_CR_1
PWR_CR1_BIAS_CR_2
PWR_CR1_BIAS_CR_3
PWR_CR1_BIAS_CR_Msk
PWR_CR1_BIAS_CR_Pos
PWR_CR1_BIAS_CR_SEL
PWR_CR1_BIAS_CR_SEL_Msk
PWR_CR1_BIAS_CR_SEL_Pos
PWR_CR1_DBP
PWR_CR1_DBP_Msk
PWR_CR1_DBP_Pos
PWR_CR1_FLS_SLPTIME
PWR_CR1_FLS_SLPTIME_0
PWR_CR1_FLS_SLPTIME_1
PWR_CR1_FLS_SLPTIME_Msk
PWR_CR1_FLS_SLPTIME_Pos
PWR_CR1_HSION_CTRL
PWR_CR1_HSION_CTRL_Msk
PWR_CR1_HSION_CTRL_Pos
PWR_CR1_LPR
PWR_CR1_LPR_Msk
PWR_CR1_LPR_Pos
PWR_CR1_MRRDY_TIME
PWR_CR1_MRRDY_TIME_0
PWR_CR1_MRRDY_TIME_1
PWR_CR1_MRRDY_TIME_Msk
PWR_CR1_MRRDY_TIME_Pos
PWR_CR1_SRAM_RETV
PWR_CR1_SRAM_RETV_0
PWR_CR1_SRAM_RETV_1
PWR_CR1_SRAM_RETV_2
PWR_CR1_SRAM_RETV_Msk
PWR_CR1_SRAM_RETV_Pos
PWR_CR1_VOS
PWR_CR1_VOS_Msk
PWR_CR1_VOS_Pos
PWR_CR2_FLTEN
PWR_CR2_FLTEN_Msk
PWR_CR2_FLTEN_Pos
PWR_CR2_FLT_TIME
PWR_CR2_FLT_TIME_0
PWR_CR2_FLT_TIME_1
PWR_CR2_FLT_TIME_2
PWR_CR2_FLT_TIME_Msk
PWR_CR2_FLT_TIME_Pos
PWR_CR2_PVDE
PWR_CR2_PVDE_Msk
PWR_CR2_PVDE_Pos
PWR_CR2_PVDT
PWR_CR2_PVDT_0
PWR_CR2_PVDT_1
PWR_CR2_PVDT_2
PWR_CR2_PVDT_Msk
PWR_CR2_PVDT_Pos
PWR_CR2_SRCSEL
PWR_CR2_SRCSEL_Msk
PWR_CR2_SRCSEL_Pos
PWR_EVENT_LINE_PVD
PWR_EXTI_LINE_PVD
PWR_FLAG_PVDO
PWR_LOWPOWERREGULATOR_ON
PWR_MAINREGULATOR_ON
PWR_PVDLEVEL_0
PWR_PVDLEVEL_1
PWR_PVDLEVEL_2
PWR_PVDLEVEL_3
PWR_PVDLEVEL_4
PWR_PVDLEVEL_5
PWR_PVDLEVEL_6
PWR_PVDLEVEL_7
PWR_PVD_FILTER_1CLOCK
PWR_PVD_FILTER_2CLOCK
PWR_PVD_FILTER_4CLOCK
PWR_PVD_FILTER_16CLOCK
PWR_PVD_FILTER_64CLOCK
PWR_PVD_FILTER_128CLOCK
PWR_PVD_FILTER_1024CLOCK
PWR_PVD_FILTER_NONE
PWR_PVD_MODE_EVENT_FALLING
PWR_PVD_MODE_EVENT_RISING
PWR_PVD_MODE_EVENT_RISING_FALLING
PWR_PVD_MODE_IT_FALLING
PWR_PVD_MODE_IT_RISING
PWR_PVD_MODE_IT_RISING_FALLING
PWR_PVD_MODE_NORMAL
PWR_PVD_SOURCE_PB07
PWR_PVD_SOURCE_VCC
PWR_SLEEPENTRY_WFE
PWR_SLEEPENTRY_WFI
PWR_SRAM_RETENTION_VOLT_0p9
PWR_SRAM_RETENTION_VOLT_VOS
PWR_SR_PVDO
PWR_SR_PVDO_Msk
PWR_SR_PVDO_Pos
PWR_STOPENTRY_WFE
PWR_STOPENTRY_WFI
PWR_STOPMOD_LPR_VOLT_SCALE1
PWR_STOPMOD_LPR_VOLT_SCALE2
PWR_WAKEUP_FLASH_DELAY_0US
PWR_WAKEUP_FLASH_DELAY_2US
PWR_WAKEUP_FLASH_DELAY_3US
PWR_WAKEUP_FLASH_DELAY_5US
PWR_WAKEUP_HSIEN_AFTER_MR
PWR_WAKEUP_HSIEN_IMMEDIATE
PWR_WAKEUP_LPR_TO_MR_DELAY_2US
PWR_WAKEUP_LPR_TO_MR_DELAY_3US
PWR_WAKEUP_LPR_TO_MR_DELAY_4US
PWR_WAKEUP_LPR_TO_MR_DELAY_5US
PWR_WUP_POLARITY_SHIFT
RCC
RCC_AHBENR_CRCEN
RCC_AHBENR_CRCEN_Msk
RCC_AHBENR_CRCEN_Pos
RCC_AHBENR_DMAEN
RCC_AHBENR_DMAEN_Msk
RCC_AHBENR_DMAEN_Pos
RCC_AHBENR_FLASHEN
RCC_AHBENR_FLASHEN_Msk
RCC_AHBENR_FLASHEN_Pos
RCC_AHBENR_SRAMEN
RCC_AHBENR_SRAMEN_Msk
RCC_AHBENR_SRAMEN_Pos
RCC_AHBRSTR_CRCRST
RCC_AHBRSTR_CRCRST_Msk
RCC_AHBRSTR_CRCRST_Pos
RCC_AHBRSTR_DMARST
RCC_AHBRSTR_DMARST_Msk
RCC_AHBRSTR_DMARST_Pos
RCC_APBENR1_DBGEN
RCC_APBENR1_DBGEN_Msk
RCC_APBENR1_DBGEN_Pos
RCC_APBENR1_I2CEN
RCC_APBENR1_I2CEN_Msk
RCC_APBENR1_I2CEN_Pos
RCC_APBENR1_LPTIMEN
RCC_APBENR1_LPTIMEN_Msk
RCC_APBENR1_LPTIMEN_Pos
RCC_APBENR1_PWREN
RCC_APBENR1_PWREN_Msk
RCC_APBENR1_PWREN_Pos
RCC_APBENR1_RTCAPBEN
RCC_APBENR1_RTCAPBEN_Msk
RCC_APBENR1_RTCAPBEN_Pos
RCC_APBENR1_SPI2EN
RCC_APBENR1_SPI2EN_Msk
RCC_APBENR1_SPI2EN_Pos
RCC_APBENR1_TIM3EN
RCC_APBENR1_TIM3EN_Msk
RCC_APBENR1_TIM3EN_Pos
RCC_APBENR1_USART2EN
RCC_APBENR1_USART2EN_Msk
RCC_APBENR1_USART2EN_Pos
RCC_APBENR1_WWDGEN
RCC_APBENR1_WWDGEN_Msk
RCC_APBENR1_WWDGEN_Pos
RCC_APBENR2_ADCEN
RCC_APBENR2_ADCEN_Msk
RCC_APBENR2_ADCEN_Pos
RCC_APBENR2_COMP1EN
RCC_APBENR2_COMP1EN_Msk
RCC_APBENR2_COMP1EN_Pos
RCC_APBENR2_COMP2EN
RCC_APBENR2_COMP2EN_Msk
RCC_APBENR2_COMP2EN_Pos
RCC_APBENR2_LEDEN
RCC_APBENR2_LEDEN_Msk
RCC_APBENR2_LEDEN_Pos
RCC_APBENR2_SPI1EN
RCC_APBENR2_SPI1EN_Msk
RCC_APBENR2_SPI1EN_Pos
RCC_APBENR2_SYSCFGEN
RCC_APBENR2_SYSCFGEN_Msk
RCC_APBENR2_SYSCFGEN_Pos
RCC_APBENR2_TIM1EN
RCC_APBENR2_TIM1EN_Msk
RCC_APBENR2_TIM1EN_Pos
RCC_APBENR2_TIM14EN
RCC_APBENR2_TIM14EN_Msk
RCC_APBENR2_TIM14EN_Pos
RCC_APBENR2_TIM16EN
RCC_APBENR2_TIM16EN_Msk
RCC_APBENR2_TIM16EN_Pos
RCC_APBENR2_TIM17EN
RCC_APBENR2_TIM17EN_Msk
RCC_APBENR2_TIM17EN_Pos
RCC_APBENR2_USART1EN
RCC_APBENR2_USART1EN_Msk
RCC_APBENR2_USART1EN_Pos
RCC_APBRSTR1_DBGRST
RCC_APBRSTR1_DBGRST_Msk
RCC_APBRSTR1_DBGRST_Pos
RCC_APBRSTR1_I2CRST
RCC_APBRSTR1_I2CRST_Msk
RCC_APBRSTR1_I2CRST_Pos
RCC_APBRSTR1_LPTIMRST
RCC_APBRSTR1_LPTIMRST_Msk
RCC_APBRSTR1_LPTIMRST_Pos
RCC_APBRSTR1_PWRRST
RCC_APBRSTR1_PWRRST_Msk
RCC_APBRSTR1_PWRRST_Pos
RCC_APBRSTR1_SPI2RST
RCC_APBRSTR1_SPI2RST_Msk
RCC_APBRSTR1_SPI2RST_Pos
RCC_APBRSTR1_TIM3RST
RCC_APBRSTR1_TIM3RST_Msk
RCC_APBRSTR1_TIM3RST_Pos
RCC_APBRSTR1_USART2RST
RCC_APBRSTR1_USART2RST_Msk
RCC_APBRSTR1_USART2RST_Pos
RCC_APBRSTR2_ADCRST
RCC_APBRSTR2_ADCRST_Msk
RCC_APBRSTR2_ADCRST_Pos
RCC_APBRSTR2_COMP1RST
RCC_APBRSTR2_COMP1RST_Msk
RCC_APBRSTR2_COMP1RST_Pos
RCC_APBRSTR2_COMP2RST
RCC_APBRSTR2_COMP2RST_Msk
RCC_APBRSTR2_COMP2RST_Pos
RCC_APBRSTR2_LEDRST
RCC_APBRSTR2_LEDRST_Msk
RCC_APBRSTR2_LEDRST_Pos
RCC_APBRSTR2_SPI1RST
RCC_APBRSTR2_SPI1RST_Msk
RCC_APBRSTR2_SPI1RST_Pos
RCC_APBRSTR2_SYSCFGRST
RCC_APBRSTR2_SYSCFGRST_Msk
RCC_APBRSTR2_SYSCFGRST_Pos
RCC_APBRSTR2_TIM1RST
RCC_APBRSTR2_TIM1RST_Msk
RCC_APBRSTR2_TIM1RST_Pos
RCC_APBRSTR2_TIM14RST
RCC_APBRSTR2_TIM14RST_Msk
RCC_APBRSTR2_TIM14RST_Pos
RCC_APBRSTR2_TIM16RST
RCC_APBRSTR2_TIM16RST_Msk
RCC_APBRSTR2_TIM16RST_Pos
RCC_APBRSTR2_TIM17RST
RCC_APBRSTR2_TIM17RST_Msk
RCC_APBRSTR2_TIM17RST_Pos
RCC_APBRSTR2_USART1RST
RCC_APBRSTR2_USART1RST_Msk
RCC_APBRSTR2_USART1RST_Pos
RCC_BASE
RCC_BDCR_BDRST
RCC_BDCR_BDRST_Msk
RCC_BDCR_BDRST_Pos
RCC_BDCR_LSCOEN
RCC_BDCR_LSCOEN_Msk
RCC_BDCR_LSCOEN_Pos
RCC_BDCR_LSCOSEL
RCC_BDCR_LSCOSEL_Msk
RCC_BDCR_LSCOSEL_Pos
RCC_BDCR_LSEBYP
RCC_BDCR_LSEBYP_Msk
RCC_BDCR_LSEBYP_Pos
RCC_BDCR_LSECSSD
RCC_BDCR_LSECSSD_Msk
RCC_BDCR_LSECSSD_Pos
RCC_BDCR_LSECSSON
RCC_BDCR_LSECSSON_Msk
RCC_BDCR_LSECSSON_Pos
RCC_BDCR_LSEON
RCC_BDCR_LSEON_Msk
RCC_BDCR_LSEON_Pos
RCC_BDCR_LSERDY
RCC_BDCR_LSERDY_Msk
RCC_BDCR_LSERDY_Pos
RCC_BDCR_RTCEN
RCC_BDCR_RTCEN_Msk
RCC_BDCR_RTCEN_Pos
RCC_BDCR_RTCSEL
RCC_BDCR_RTCSEL_0
RCC_BDCR_RTCSEL_1
RCC_BDCR_RTCSEL_Msk
RCC_BDCR_RTCSEL_Pos
RCC_CCIPR_COMP1SEL
RCC_CCIPR_COMP1SEL_Msk
RCC_CCIPR_COMP1SEL_Pos
RCC_CCIPR_COMP2SEL
RCC_CCIPR_COMP2SEL_Msk
RCC_CCIPR_COMP2SEL_Pos
RCC_CCIPR_LPTIMSEL
RCC_CCIPR_LPTIMSEL_0
RCC_CCIPR_LPTIMSEL_1
RCC_CCIPR_LPTIMSEL_Msk
RCC_CCIPR_LPTIMSEL_Pos
RCC_CCIPR_PVDSEL
RCC_CCIPR_PVDSEL_Msk
RCC_CCIPR_PVDSEL_Pos
RCC_CFGR_HPRE
RCC_CFGR_HPRE_0
RCC_CFGR_HPRE_1
RCC_CFGR_HPRE_2
RCC_CFGR_HPRE_3
RCC_CFGR_HPRE_Msk
RCC_CFGR_HPRE_Pos
RCC_CFGR_MCOPRE
RCC_CFGR_MCOPRE_0
RCC_CFGR_MCOPRE_1
RCC_CFGR_MCOPRE_2
RCC_CFGR_MCOPRE_Msk
RCC_CFGR_MCOPRE_Pos
RCC_CFGR_MCOSEL
RCC_CFGR_MCOSEL_0
RCC_CFGR_MCOSEL_1
RCC_CFGR_MCOSEL_2
RCC_CFGR_MCOSEL_Msk
RCC_CFGR_MCOSEL_Pos
RCC_CFGR_PPRE
RCC_CFGR_PPRE_0
RCC_CFGR_PPRE_1
RCC_CFGR_PPRE_2
RCC_CFGR_PPRE_Msk
RCC_CFGR_PPRE_Pos
RCC_CFGR_SW
RCC_CFGR_SWS
RCC_CFGR_SWS_0
RCC_CFGR_SWS_1
RCC_CFGR_SWS_2
RCC_CFGR_SWS_HSE
RCC_CFGR_SWS_HSI
RCC_CFGR_SWS_LSE
RCC_CFGR_SWS_LSI
RCC_CFGR_SWS_Msk
RCC_CFGR_SWS_PLL
RCC_CFGR_SWS_Pos
RCC_CFGR_SW_0
RCC_CFGR_SW_1
RCC_CFGR_SW_2
RCC_CFGR_SW_Msk
RCC_CFGR_SW_Pos
RCC_CICR_CSSC
RCC_CICR_CSSC_Msk
RCC_CICR_CSSC_Pos
RCC_CICR_HSERDYC
RCC_CICR_HSERDYC_Msk
RCC_CICR_HSERDYC_Pos
RCC_CICR_HSIRDYC
RCC_CICR_HSIRDYC_Msk
RCC_CICR_HSIRDYC_Pos
RCC_CICR_LSECSSC
RCC_CICR_LSECSSC_Msk
RCC_CICR_LSECSSC_Pos
RCC_CICR_LSERDYC
RCC_CICR_LSERDYC_Msk
RCC_CICR_LSERDYC_Pos
RCC_CICR_LSIRDYC
RCC_CICR_LSIRDYC_Msk
RCC_CICR_LSIRDYC_Pos
RCC_CICR_PLLRDYC
RCC_CICR_PLLRDYC_Msk
RCC_CICR_PLLRDYC_Pos
RCC_CIER_HSERDYIE
RCC_CIER_HSERDYIE_Msk
RCC_CIER_HSERDYIE_Pos
RCC_CIER_HSIRDYIE
RCC_CIER_HSIRDYIE_Msk
RCC_CIER_HSIRDYIE_Pos
RCC_CIER_LSERDYIE
RCC_CIER_LSERDYIE_Msk
RCC_CIER_LSERDYIE_Pos
RCC_CIER_LSIRDYIE
RCC_CIER_LSIRDYIE_Msk
RCC_CIER_LSIRDYIE_Pos
RCC_CIER_PLLRDYIE
RCC_CIER_PLLRDYIE_Msk
RCC_CIER_PLLRDYIE_Pos
RCC_CIFR_CSSF
RCC_CIFR_CSSF_Msk
RCC_CIFR_CSSF_Pos
RCC_CIFR_HSERDYF
RCC_CIFR_HSERDYF_Msk
RCC_CIFR_HSERDYF_Pos
RCC_CIFR_HSIRDYF
RCC_CIFR_HSIRDYF_Msk
RCC_CIFR_HSIRDYF_Pos
RCC_CIFR_LSECSSF
RCC_CIFR_LSECSSF_Msk
RCC_CIFR_LSECSSF_Pos
RCC_CIFR_LSERDYF
RCC_CIFR_LSERDYF_Msk
RCC_CIFR_LSERDYF_Pos
RCC_CIFR_LSIRDYF
RCC_CIFR_LSIRDYF_Msk
RCC_CIFR_LSIRDYF_Pos
RCC_CIFR_PLLRDYF
RCC_CIFR_PLLRDYF_Msk
RCC_CIFR_PLLRDYF_Pos
RCC_CLOCKTYPE_ALL
RCC_CLOCKTYPE_HCLK
RCC_CLOCKTYPE_PCLK1
RCC_CLOCKTYPE_SYSCLK
RCC_COMP1CLKSOURCE_LSC
RCC_COMP1CLKSOURCE_PCLK
RCC_COMP2CLKSOURCE_LSC
RCC_COMP2CLKSOURCE_PCLK
RCC_CR_CSSON
RCC_CR_CSSON_Msk
RCC_CR_CSSON_Pos
RCC_CR_HSEBYP
RCC_CR_HSEBYP_Msk
RCC_CR_HSEBYP_Pos
RCC_CR_HSEON
RCC_CR_HSEON_Msk
RCC_CR_HSEON_Pos
RCC_CR_HSERDY
RCC_CR_HSERDY_Msk
RCC_CR_HSERDY_Pos
RCC_CR_HSIDIV
RCC_CR_HSIDIV_0
RCC_CR_HSIDIV_1
RCC_CR_HSIDIV_2
RCC_CR_HSIDIV_Msk
RCC_CR_HSIDIV_Pos
RCC_CR_HSION
RCC_CR_HSION_Msk
RCC_CR_HSION_Pos
RCC_CR_HSIRDY
RCC_CR_HSIRDY_Msk
RCC_CR_HSIRDY_Pos
RCC_CR_PLLON
RCC_CR_PLLON_Msk
RCC_CR_PLLON_Pos
RCC_CR_PLLRDY
RCC_CR_PLLRDY_Msk
RCC_CR_PLLRDY_Pos
RCC_CSR_IWDGRSTF
RCC_CSR_IWDGRSTF_Msk
RCC_CSR_IWDGRSTF_Pos
RCC_CSR_LSION
RCC_CSR_LSION_Msk
RCC_CSR_LSION_Pos
RCC_CSR_LSIRDY
RCC_CSR_LSIRDY_Msk
RCC_CSR_LSIRDY_Pos
RCC_CSR_NRST_FLTDIS
RCC_CSR_NRST_FLTDIS_Msk
RCC_CSR_NRST_FLTDIS_Pos
RCC_CSR_OBLRSTF
RCC_CSR_OBLRSTF_Msk
RCC_CSR_OBLRSTF_Pos
RCC_CSR_PINRSTF
RCC_CSR_PINRSTF_Msk
RCC_CSR_PINRSTF_Pos
RCC_CSR_PWRRSTF
RCC_CSR_PWRRSTF_Msk
RCC_CSR_PWRRSTF_Pos
RCC_CSR_RMVF
RCC_CSR_RMVF_Msk
RCC_CSR_RMVF_Pos
RCC_CSR_SFTRSTF
RCC_CSR_SFTRSTF_Msk
RCC_CSR_SFTRSTF_Pos
RCC_CSR_WWDGRSTF
RCC_CSR_WWDGRSTF_Msk
RCC_CSR_WWDGRSTF_Pos
RCC_DBP_TIMEOUT_VALUE
RCC_ECSCR_HSE_FREQ
RCC_ECSCR_HSE_FREQ_0
RCC_ECSCR_HSE_FREQ_1
RCC_ECSCR_HSE_FREQ_Msk
RCC_ECSCR_HSE_FREQ_Pos
RCC_ECSCR_LSE_DRIVER
RCC_ECSCR_LSE_DRIVER_0
RCC_ECSCR_LSE_DRIVER_1
RCC_ECSCR_LSE_DRIVER_Msk
RCC_ECSCR_LSE_DRIVER_Pos
RCC_FLAG_HSERDY
RCC_FLAG_HSIRDY
RCC_FLAG_IWDGRST
RCC_FLAG_LSERDY
RCC_FLAG_LSIRDY
RCC_FLAG_MASK
RCC_FLAG_OBLRST
RCC_FLAG_PINRST
RCC_FLAG_PLLRDY
RCC_FLAG_PWRRST
RCC_FLAG_SFTRST
RCC_FLAG_WWDGRST
RCC_HCLK_DIV1
RCC_HCLK_DIV2
RCC_HCLK_DIV4
RCC_HCLK_DIV8
RCC_HCLK_DIV16
RCC_HSE_4_8MHz
RCC_HSE_8_16MHz
RCC_HSE_16_32MHz
RCC_HSE_BYPASS
RCC_HSE_OFF
RCC_HSE_ON
RCC_HSI_DIV1
RCC_HSI_DIV2
RCC_HSI_DIV4
RCC_HSI_DIV8
RCC_HSI_DIV16
RCC_HSI_DIV32
RCC_HSI_DIV64
RCC_HSI_DIV128
RCC_HSI_OFF
RCC_HSI_ON
RCC_ICSCR_HSI_FS
RCC_ICSCR_HSI_FS_0
RCC_ICSCR_HSI_FS_1
RCC_ICSCR_HSI_FS_2
RCC_ICSCR_HSI_FS_Msk
RCC_ICSCR_HSI_FS_Pos
RCC_ICSCR_HSI_TRIM
RCC_ICSCR_HSI_TRIM_0
RCC_ICSCR_HSI_TRIM_1
RCC_ICSCR_HSI_TRIM_2
RCC_ICSCR_HSI_TRIM_3
RCC_ICSCR_HSI_TRIM_4
RCC_ICSCR_HSI_TRIM_5
RCC_ICSCR_HSI_TRIM_6
RCC_ICSCR_HSI_TRIM_7
RCC_ICSCR_HSI_TRIM_8
RCC_ICSCR_HSI_TRIM_9
RCC_ICSCR_HSI_TRIM_10
RCC_ICSCR_HSI_TRIM_11
RCC_ICSCR_HSI_TRIM_12
RCC_ICSCR_HSI_TRIM_Msk
RCC_ICSCR_HSI_TRIM_Pos
RCC_ICSCR_LSI_STARTUP
RCC_ICSCR_LSI_STARTUP_0
RCC_ICSCR_LSI_STARTUP_1
RCC_ICSCR_LSI_STARTUP_Msk
RCC_ICSCR_LSI_STARTUP_Pos
RCC_ICSCR_LSI_TRIM
RCC_ICSCR_LSI_TRIM_0
RCC_ICSCR_LSI_TRIM_1
RCC_ICSCR_LSI_TRIM_2
RCC_ICSCR_LSI_TRIM_3
RCC_ICSCR_LSI_TRIM_4
RCC_ICSCR_LSI_TRIM_5
RCC_ICSCR_LSI_TRIM_6
RCC_ICSCR_LSI_TRIM_7
RCC_ICSCR_LSI_TRIM_8
RCC_ICSCR_LSI_TRIM_Msk
RCC_ICSCR_LSI_TRIM_Pos
RCC_IOPENR_GPIOAEN
RCC_IOPENR_GPIOAEN_Msk
RCC_IOPENR_GPIOAEN_Pos
RCC_IOPENR_GPIOBEN
RCC_IOPENR_GPIOBEN_Msk
RCC_IOPENR_GPIOBEN_Pos
RCC_IOPENR_GPIOFEN
RCC_IOPENR_GPIOFEN_Msk
RCC_IOPENR_GPIOFEN_Pos
RCC_IOPRSTR_GPIOARST
RCC_IOPRSTR_GPIOARST_Msk
RCC_IOPRSTR_GPIOARST_Pos
RCC_IOPRSTR_GPIOBRST
RCC_IOPRSTR_GPIOBRST_Msk
RCC_IOPRSTR_GPIOBRST_Pos
RCC_IOPRSTR_GPIOFRST
RCC_IOPRSTR_GPIOFRST_Msk
RCC_IOPRSTR_GPIOFRST_Pos
RCC_IT_CSS
RCC_IT_HSERDY
RCC_IT_HSIRDY
RCC_IT_LSECSS
RCC_IT_LSERDY
RCC_IT_LSIRDY
RCC_IT_PLLRDY
RCC_LPTIMCLKSOURCE_LSE
RCC_LPTIMCLKSOURCE_LSI
RCC_LPTIMCLKSOURCE_PCLK
RCC_LSCOSOURCE_LSE
RCC_LSCOSOURCE_LSI
RCC_LSEDRIVE_HIGH
RCC_LSEDRIVE_LOW
RCC_LSEDRIVE_MEDIUM
RCC_LSE_BYPASS
RCC_LSE_OFF
RCC_LSE_ON
RCC_LSE_TIMEOUT_VALUE
RCC_LSI_OFF
RCC_LSI_ON
RCC_MCO
RCC_MCO1
RCC_MCO2
RCC_MCO3
RCC_MCO4
RCC_MCO5
RCC_MCO6
RCC_MCO7
RCC_MCO1SOURCE_HSE
RCC_MCO1SOURCE_HSI
RCC_MCO1SOURCE_HSI10M
RCC_MCO1SOURCE_LSE
RCC_MCO1SOURCE_LSI
RCC_MCO1SOURCE_NOCLOCK
RCC_MCO1SOURCE_PLLCLK
RCC_MCO1SOURCE_SYSCLK
RCC_MCODIV_1
RCC_MCODIV_2
RCC_MCODIV_4
RCC_MCODIV_8
RCC_MCODIV_16
RCC_MCODIV_32
RCC_MCODIV_64
RCC_MCODIV_128
RCC_OSCILLATORTYPE_HSE
RCC_OSCILLATORTYPE_HSI
RCC_OSCILLATORTYPE_LSE
RCC_OSCILLATORTYPE_LSI
RCC_OSCILLATORTYPE_NONE
RCC_PERIPHCLK_COMP1
RCC_PERIPHCLK_COMP2
RCC_PERIPHCLK_LPTIM
RCC_PERIPHCLK_PVD
RCC_PERIPHCLK_RTC
RCC_PLLCFGR_PLLSRC
RCC_PLLCFGR_PLLSRC_HSE
RCC_PLLCFGR_PLLSRC_HSE_Msk
RCC_PLLCFGR_PLLSRC_HSE_Pos
RCC_PLLCFGR_PLLSRC_HSI
RCC_PLLCFGR_PLLSRC_HSI_Msk
RCC_PLLCFGR_PLLSRC_HSI_Pos
RCC_PLLCFGR_PLLSRC_Msk
RCC_PLLCFGR_PLLSRC_NONE
RCC_PLLCFGR_PLLSRC_Pos
RCC_PLLSOURCE_HSE
RCC_PLLSOURCE_HSI
RCC_PLLSOURCE_NONE
RCC_PLL_NONE
RCC_PLL_OFF
RCC_PLL_ON
RCC_PVDCLKSOURCE_LSC
RCC_PVDCLKSOURCE_PCLK
RCC_RTCCLKSOURCE_HSE_DIV128
RCC_RTCCLKSOURCE_LSE
RCC_RTCCLKSOURCE_LSI
RCC_RTCCLKSOURCE_NONE
RCC_SYSCLKSOURCE_HSE
RCC_SYSCLKSOURCE_HSI
RCC_SYSCLKSOURCE_LSE
RCC_SYSCLKSOURCE_LSI
RCC_SYSCLKSOURCE_PLLCLK
RCC_SYSCLKSOURCE_STATUS_HSE
RCC_SYSCLKSOURCE_STATUS_HSI
RCC_SYSCLKSOURCE_STATUS_LSE
RCC_SYSCLKSOURCE_STATUS_LSI
RCC_SYSCLKSOURCE_STATUS_PLLCLK
RCC_SYSCLK_DIV1
RCC_SYSCLK_DIV2
RCC_SYSCLK_DIV4
RCC_SYSCLK_DIV8
RCC_SYSCLK_DIV16
RCC_SYSCLK_DIV64
RCC_SYSCLK_DIV128
RCC_SYSCLK_DIV256
RCC_SYSCLK_DIV512
RTC
RTC_ALARM_A
RTC_ALRH_RTC_ALR
RTC_ALRH_RTC_ALR_Msk
RTC_ALRH_RTC_ALR_Pos
RTC_ALRL_RTC_ALR
RTC_ALRL_RTC_ALR_Msk
RTC_ALRL_RTC_ALR_Pos
RTC_AUTO_1_SECOND
RTC_BASE
RTC_CNTH_RTC_CNT
RTC_CNTH_RTC_CNT_Msk
RTC_CNTH_RTC_CNT_Pos
RTC_CNTL_RTC_CNT
RTC_CNTL_RTC_CNT_Msk
RTC_CNTL_RTC_CNT_Pos
RTC_CRH_ALRIE
RTC_CRH_ALRIE_Msk
RTC_CRH_ALRIE_Pos
RTC_CRH_OWIE
RTC_CRH_OWIE_Msk
RTC_CRH_OWIE_Pos
RTC_CRH_SECIE
RTC_CRH_SECIE_Msk
RTC_CRH_SECIE_Pos
RTC_CRL_ALRF
RTC_CRL_ALRF_Msk
RTC_CRL_ALRF_Pos
RTC_CRL_CNF
RTC_CRL_CNF_Msk
RTC_CRL_CNF_Pos
RTC_CRL_OWF
RTC_CRL_OWF_Msk
RTC_CRL_OWF_Pos
RTC_CRL_RSF
RTC_CRL_RSF_Msk
RTC_CRL_RSF_Pos
RTC_CRL_RTOFF
RTC_CRL_RTOFF_Msk
RTC_CRL_RTOFF_Pos
RTC_CRL_SECF
RTC_CRL_SECF_Msk
RTC_CRL_SECF_Pos
RTC_DIVH_RTC_DIV
RTC_DIVH_RTC_DIV_Msk
RTC_DIVH_RTC_DIV_Pos
RTC_DIVL_RTC_DIV
RTC_DIVL_RTC_DIV_Msk
RTC_DIVL_RTC_DIV_Pos
RTC_EXTI_LINE_ALARM_EVENT
RTC_FLAG_ALRAF
RTC_FLAG_OW
RTC_FLAG_RSF
RTC_FLAG_RTOFF
RTC_FLAG_SEC
RTC_FORMAT_BCD
RTC_FORMAT_BIN
RTC_IT_ALRA
RTC_IT_OW
RTC_IT_SEC
RTC_MONTH_APRIL
RTC_MONTH_AUGUST
RTC_MONTH_DECEMBER
RTC_MONTH_FEBRUARY
RTC_MONTH_JANUARY
RTC_MONTH_JULY
RTC_MONTH_JUNE
RTC_MONTH_MARCH
RTC_MONTH_MAY
RTC_MONTH_NOVEMBER
RTC_MONTH_OCTOBER
RTC_MONTH_SEPTEMBER
RTC_OUTPUTSOURCE_ALARM
RTC_OUTPUTSOURCE_CALIBCLOCK
RTC_OUTPUTSOURCE_NONE
RTC_OUTPUTSOURCE_SECOND
RTC_PRLH_PRL
RTC_PRLH_PRL_Msk
RTC_PRLH_PRL_Pos
RTC_PRLL_PRL
RTC_PRLL_PRL_Msk
RTC_PRLL_PRL_Pos
RTC_RTOFF_RESET_TIMEOUT_VALUE
RTC_TIMEOUT_VALUE
RTC_WEEKDAY_FRIDAY
RTC_WEEKDAY_MONDAY
RTC_WEEKDAY_SATURDAY
RTC_WEEKDAY_SUNDAY
RTC_WEEKDAY_THURSDAY
RTC_WEEKDAY_TUESDAY
RTC_WEEKDAY_WEDNESDAY
SCB
SCB_AIRCR_ENDIANESS_Msk
SCB_AIRCR_ENDIANESS_Pos
SCB_AIRCR_SYSRESETREQ_Msk
SCB_AIRCR_SYSRESETREQ_Pos
SCB_AIRCR_VECTCLRACTIVE_Msk
SCB_AIRCR_VECTCLRACTIVE_Pos
SCB_AIRCR_VECTKEYSTAT_Msk
SCB_AIRCR_VECTKEYSTAT_Pos
SCB_AIRCR_VECTKEY_Msk
SCB_AIRCR_VECTKEY_Pos
SCB_BASE
SCB_CCR_STKALIGN_Msk
SCB_CCR_STKALIGN_Pos
SCB_CCR_UNALIGN_TRP_Msk
SCB_CCR_UNALIGN_TRP_Pos
SCB_CPUID_ARCHITECTURE_Msk
SCB_CPUID_ARCHITECTURE_Pos
SCB_CPUID_IMPLEMENTER_Msk
SCB_CPUID_IMPLEMENTER_Pos
SCB_CPUID_PARTNO_Msk
SCB_CPUID_PARTNO_Pos
SCB_CPUID_REVISION_Msk
SCB_CPUID_REVISION_Pos
SCB_CPUID_VARIANT_Msk
SCB_CPUID_VARIANT_Pos
SCB_ICSR_ISRPENDING_Msk
SCB_ICSR_ISRPENDING_Pos
SCB_ICSR_ISRPREEMPT_Msk
SCB_ICSR_ISRPREEMPT_Pos
SCB_ICSR_NMIPENDSET_Msk
SCB_ICSR_NMIPENDSET_Pos
SCB_ICSR_PENDSTCLR_Msk
SCB_ICSR_PENDSTCLR_Pos
SCB_ICSR_PENDSTSET_Msk
SCB_ICSR_PENDSTSET_Pos
SCB_ICSR_PENDSVCLR_Msk
SCB_ICSR_PENDSVCLR_Pos
SCB_ICSR_PENDSVSET_Msk
SCB_ICSR_PENDSVSET_Pos
SCB_ICSR_VECTACTIVE_Msk
SCB_ICSR_VECTACTIVE_Pos
SCB_ICSR_VECTPENDING_Msk
SCB_ICSR_VECTPENDING_Pos
SCB_SCR_SEVONPEND_Msk
SCB_SCR_SEVONPEND_Pos
SCB_SCR_SLEEPDEEP_Msk
SCB_SCR_SLEEPDEEP_Pos
SCB_SCR_SLEEPONEXIT_Msk
SCB_SCR_SLEEPONEXIT_Pos
SCB_SHCSR_SVCALLPENDED_Msk
SCB_SHCSR_SVCALLPENDED_Pos
SCB_VTOR_TBLOFF_Msk
SCB_VTOR_TBLOFF_Pos
SCS_BASE
SPI1
SPI2
SPI1_BASE
SPI2_BASE
SPI_BAUDRATEPRESCALER_2
SPI_BAUDRATEPRESCALER_4
SPI_BAUDRATEPRESCALER_8
SPI_BAUDRATEPRESCALER_16
SPI_BAUDRATEPRESCALER_32
SPI_BAUDRATEPRESCALER_64
SPI_BAUDRATEPRESCALER_128
SPI_BAUDRATEPRESCALER_256
SPI_CR1_BIDIMODE
SPI_CR1_BIDIMODE_Msk
SPI_CR1_BIDIMODE_Pos
SPI_CR1_BIDIOE
SPI_CR1_BIDIOE_Msk
SPI_CR1_BIDIOE_Pos
SPI_CR1_BR
SPI_CR1_BR_0
SPI_CR1_BR_1
SPI_CR1_BR_2
SPI_CR1_BR_Msk
SPI_CR1_BR_Pos
SPI_CR1_CPHA
SPI_CR1_CPHA_Msk
SPI_CR1_CPHA_Pos
SPI_CR1_CPOL
SPI_CR1_CPOL_Msk
SPI_CR1_CPOL_Pos
SPI_CR1_LSBFIRST
SPI_CR1_LSBFIRST_Msk
SPI_CR1_LSBFIRST_Pos
SPI_CR1_MSTR
SPI_CR1_MSTR_Msk
SPI_CR1_MSTR_Pos
SPI_CR1_RXONLY
SPI_CR1_RXONLY_Msk
SPI_CR1_RXONLY_Pos
SPI_CR1_SPE
SPI_CR1_SPE_Msk
SPI_CR1_SPE_Pos
SPI_CR1_SSI
SPI_CR1_SSI_Msk
SPI_CR1_SSI_Pos
SPI_CR1_SSM
SPI_CR1_SSM_Msk
SPI_CR1_SSM_Pos
SPI_CR2_DS
SPI_CR2_DS_Msk
SPI_CR2_DS_Pos
SPI_CR2_ERRIE
SPI_CR2_ERRIE_Msk
SPI_CR2_ERRIE_Pos
SPI_CR2_FRXTH
SPI_CR2_FRXTH_Msk
SPI_CR2_FRXTH_Pos
SPI_CR2_LDMA_RX
SPI_CR2_LDMA_RX_Msk
SPI_CR2_LDMA_RX_Pos
SPI_CR2_LDMA_TX
SPI_CR2_LDMA_TX_Msk
SPI_CR2_LDMA_TX_Pos
SPI_CR2_RXDMAEN
SPI_CR2_RXDMAEN_Msk
SPI_CR2_RXDMAEN_Pos
SPI_CR2_RXNEIE
SPI_CR2_RXNEIE_Msk
SPI_CR2_RXNEIE_Pos
SPI_CR2_SLVFM
SPI_CR2_SLVFM_Msk
SPI_CR2_SLVFM_Pos
SPI_CR2_SSOE
SPI_CR2_SSOE_Msk
SPI_CR2_SSOE_Pos
SPI_CR2_TXDMAEN
SPI_CR2_TXDMAEN_Msk
SPI_CR2_TXDMAEN_Pos
SPI_CR2_TXEIE
SPI_CR2_TXEIE_Msk
SPI_CR2_TXEIE_Pos
SPI_DATASIZE_8BIT
SPI_DATASIZE_16BIT
SPI_DIRECTION_1LINE
SPI_DIRECTION_2LINES
SPI_DIRECTION_2LINES_RXONLY
SPI_DR_DR
SPI_DR_DR_Msk
SPI_DR_DR_Pos
SPI_FIRSTBIT_LSB
SPI_FIRSTBIT_MSB
SPI_FLAG_BSY
SPI_FLAG_FRLVL
SPI_FLAG_FTLVL
SPI_FLAG_MASK
SPI_FLAG_MODF
SPI_FLAG_OVR
SPI_FLAG_RXNE
SPI_FLAG_TXE
SPI_FRLVL_EMPTY
SPI_FRLVL_FULL
SPI_FRLVL_HALF_FULL
SPI_FRLVL_QUARTER_FULL
SPI_FTLVL_EMPTY
SPI_FTLVL_FULL
SPI_FTLVL_HALF_FULL
SPI_FTLVL_QUARTER_FULL
SPI_IT_ERR
SPI_IT_RXNE
SPI_IT_TXE
SPI_MODE_MASTER
SPI_MODE_SLAVE
SPI_NSS_HARD_INPUT
SPI_NSS_HARD_OUTPUT
SPI_NSS_SOFT
SPI_PHASE_1EDGE
SPI_PHASE_2EDGE
SPI_POLARITY_HIGH
SPI_POLARITY_LOW
SPI_RXFIFO_THRESHOLD
SPI_RXFIFO_THRESHOLD_HF
SPI_RXFIFO_THRESHOLD_QF
SPI_SLAVE_FAST_MODE_DISABLE
SPI_SLAVE_FAST_MODE_ENABLE
SPI_SR_BSY
SPI_SR_BSY_Msk
SPI_SR_BSY_Pos
SPI_SR_FRLVL
SPI_SR_FRLVL_0
SPI_SR_FRLVL_1
SPI_SR_FRLVL_Msk
SPI_SR_FRLVL_Pos
SPI_SR_FTLVL
SPI_SR_FTLVL_0
SPI_SR_FTLVL_1
SPI_SR_FTLVL_Msk
SPI_SR_FTLVL_Pos
SPI_SR_MODF
SPI_SR_MODF_Msk
SPI_SR_MODF_Pos
SPI_SR_OVR
SPI_SR_OVR_Msk
SPI_SR_OVR_Pos
SPI_SR_RXNE
SPI_SR_RXNE_Msk
SPI_SR_RXNE_Pos
SPI_SR_TXE
SPI_SR_TXE_Msk
SPI_SR_TXE_Pos
SRAM_BASE
SRAM_END
SYSCFG
SYSCFG_BASE
SYSCFG_BOOT_MAINFLASH
SYSCFG_BOOT_SRAM
SYSCFG_BOOT_SYSTEMFLASH
SYSCFG_CFGR1_I2C_PA2_ANF
SYSCFG_CFGR1_I2C_PA2_ANF_Msk
SYSCFG_CFGR1_I2C_PA2_ANF_Pos
SYSCFG_CFGR1_I2C_PA3_ANF
SYSCFG_CFGR1_I2C_PA3_ANF_Msk
SYSCFG_CFGR1_I2C_PA3_ANF_Pos
SYSCFG_CFGR1_I2C_PA7_ANF
SYSCFG_CFGR1_I2C_PA7_ANF_Msk
SYSCFG_CFGR1_I2C_PA7_ANF_Pos
SYSCFG_CFGR1_I2C_PA8_ANF
SYSCFG_CFGR1_I2C_PA8_ANF_Msk
SYSCFG_CFGR1_I2C_PA8_ANF_Pos
SYSCFG_CFGR1_I2C_PA9_ANF
SYSCFG_CFGR1_I2C_PA9_ANF_Msk
SYSCFG_CFGR1_I2C_PA9_ANF_Pos
SYSCFG_CFGR1_I2C_PA10_ANF
SYSCFG_CFGR1_I2C_PA10_ANF_Msk
SYSCFG_CFGR1_I2C_PA10_ANF_Pos
SYSCFG_CFGR1_I2C_PA11_ANF
SYSCFG_CFGR1_I2C_PA11_ANF_Msk
SYSCFG_CFGR1_I2C_PA11_ANF_Pos
SYSCFG_CFGR1_I2C_PA12_ANF
SYSCFG_CFGR1_I2C_PA12_ANF_Msk
SYSCFG_CFGR1_I2C_PA12_ANF_Pos
SYSCFG_CFGR1_I2C_PB6_ANF
SYSCFG_CFGR1_I2C_PB6_ANF_Msk
SYSCFG_CFGR1_I2C_PB6_ANF_Pos
SYSCFG_CFGR1_I2C_PB7_ANF
SYSCFG_CFGR1_I2C_PB7_ANF_Msk
SYSCFG_CFGR1_I2C_PB7_ANF_Pos
SYSCFG_CFGR1_I2C_PB8_ANF
SYSCFG_CFGR1_I2C_PB8_ANF_Msk
SYSCFG_CFGR1_I2C_PB8_ANF_Pos
SYSCFG_CFGR1_I2C_PF0_ANF
SYSCFG_CFGR1_I2C_PF0_ANF_Msk
SYSCFG_CFGR1_I2C_PF0_ANF_Pos
SYSCFG_CFGR1_I2C_PF1_ANF
SYSCFG_CFGR1_I2C_PF1_ANF_Msk
SYSCFG_CFGR1_I2C_PF1_ANF_Pos
SYSCFG_CFGR1_MEM_MODE
SYSCFG_CFGR1_MEM_MODE_0
SYSCFG_CFGR1_MEM_MODE_1
SYSCFG_CFGR1_MEM_MODE_Msk
SYSCFG_CFGR1_MEM_MODE_Pos
SYSCFG_CFGR2_COMP1_BRK_TIM1
SYSCFG_CFGR2_COMP1_BRK_TIM1_Msk
SYSCFG_CFGR2_COMP1_BRK_TIM1_Pos
SYSCFG_CFGR2_COMP1_BRK_TIM16
SYSCFG_CFGR2_COMP1_BRK_TIM17
SYSCFG_CFGR2_COMP1_BRK_TIM16_Msk
SYSCFG_CFGR2_COMP1_BRK_TIM16_Pos
SYSCFG_CFGR2_COMP1_BRK_TIM17_Msk
SYSCFG_CFGR2_COMP1_BRK_TIM17_Pos
SYSCFG_CFGR2_COMP2_BRK_TIM1
SYSCFG_CFGR2_COMP2_BRK_TIM1_Msk
SYSCFG_CFGR2_COMP2_BRK_TIM1_Pos
SYSCFG_CFGR2_COMP2_BRK_TIM16
SYSCFG_CFGR2_COMP2_BRK_TIM17
SYSCFG_CFGR2_COMP2_BRK_TIM16_Msk
SYSCFG_CFGR2_COMP2_BRK_TIM16_Pos
SYSCFG_CFGR2_COMP2_BRK_TIM17_Msk
SYSCFG_CFGR2_COMP2_BRK_TIM17_Pos
SYSCFG_CFGR2_ETR_SRC_TIM1
SYSCFG_CFGR2_ETR_SRC_TIM1_0
SYSCFG_CFGR2_ETR_SRC_TIM1_1
SYSCFG_CFGR2_ETR_SRC_TIM1_Msk
SYSCFG_CFGR2_ETR_SRC_TIM1_Pos
SYSCFG_CFGR2_LOCKUP_LOCK
SYSCFG_CFGR2_LOCKUP_LOCK_Msk
SYSCFG_CFGR2_LOCKUP_LOCK_Pos
SYSCFG_CFGR2_PVD_LOCK
SYSCFG_CFGR2_PVD_LOCK_Msk
SYSCFG_CFGR2_PVD_LOCK_Pos
SYSCFG_CFGR3_DMA1_ACKLVL
SYSCFG_CFGR3_DMA1_ACKLVL_Msk
SYSCFG_CFGR3_DMA1_ACKLVL_Pos
SYSCFG_CFGR3_DMA1_MAP
SYSCFG_CFGR3_DMA1_MAP_0
SYSCFG_CFGR3_DMA1_MAP_1
SYSCFG_CFGR3_DMA1_MAP_2
SYSCFG_CFGR3_DMA1_MAP_3
SYSCFG_CFGR3_DMA1_MAP_4
SYSCFG_CFGR3_DMA1_MAP_Msk
SYSCFG_CFGR3_DMA1_MAP_Pos
SYSCFG_CFGR3_DMA2_ACKLVL
SYSCFG_CFGR3_DMA2_ACKLVL_Msk
SYSCFG_CFGR3_DMA2_ACKLVL_Pos
SYSCFG_CFGR3_DMA2_MAP
SYSCFG_CFGR3_DMA2_MAP_0
SYSCFG_CFGR3_DMA2_MAP_1
SYSCFG_CFGR3_DMA2_MAP_2
SYSCFG_CFGR3_DMA2_MAP_3
SYSCFG_CFGR3_DMA2_MAP_4
SYSCFG_CFGR3_DMA2_MAP_Msk
SYSCFG_CFGR3_DMA2_MAP_Pos
SYSCFG_CFGR3_DMA3_ACKLVL
SYSCFG_CFGR3_DMA3_ACKLVL_Msk
SYSCFG_CFGR3_DMA3_ACKLVL_Pos
SYSCFG_CFGR3_DMA3_MAP
SYSCFG_CFGR3_DMA3_MAP_0
SYSCFG_CFGR3_DMA3_MAP_1
SYSCFG_CFGR3_DMA3_MAP_2
SYSCFG_CFGR3_DMA3_MAP_3
SYSCFG_CFGR3_DMA3_MAP_4
SYSCFG_CFGR3_DMA3_MAP_Msk
SYSCFG_CFGR3_DMA3_MAP_Pos
SYSTICK_CLKSOURCE_HCLK
SYSTICK_CLKSOURCE_HCLK_DIV8
SysTick
SysTick_BASE
SysTick_CALIB_NOREF_Msk
SysTick_CALIB_NOREF_Pos
SysTick_CALIB_SKEW_Msk
SysTick_CALIB_SKEW_Pos
SysTick_CALIB_TENMS_Msk
SysTick_CALIB_TENMS_Pos
SysTick_CTRL_CLKSOURCE_Msk
SysTick_CTRL_CLKSOURCE_Pos
SysTick_CTRL_COUNTFLAG_Msk
SysTick_CTRL_COUNTFLAG_Pos
SysTick_CTRL_ENABLE_Msk
SysTick_CTRL_ENABLE_Pos
SysTick_CTRL_TICKINT_Msk
SysTick_CTRL_TICKINT_Pos
SysTick_LOAD_RELOAD_Msk
SysTick_LOAD_RELOAD_Pos
SysTick_VAL_CURRENT_Msk
SysTick_VAL_CURRENT_Pos
TICK_INT_PRIORITY
TIM1
TIM3
TIM1_BASE
TIM3_BASE
TIM14
TIM16
TIM17
TIM14_BASE
TIM14_OR_TI1_RMP
TIM14_OR_TI1_RMP_0
TIM14_OR_TI1_RMP_1
TIM14_OR_TI1_RMP_Msk
TIM14_OR_TI1_RMP_Pos
TIM16_BASE
TIM17_BASE
TIM_ARR_ARR
TIM_ARR_ARR_Msk
TIM_ARR_ARR_Pos
TIM_AUTOMATICOUTPUT_DISABLE
TIM_AUTOMATICOUTPUT_ENABLE
TIM_AUTORELOAD_PRELOAD_DISABLE
TIM_AUTORELOAD_PRELOAD_ENABLE
TIM_BDTR_AOE
TIM_BDTR_AOE_Msk
TIM_BDTR_AOE_Pos
TIM_BDTR_BKE
TIM_BDTR_BKE_Msk
TIM_BDTR_BKE_Pos
TIM_BDTR_BKP
TIM_BDTR_BKP_Msk
TIM_BDTR_BKP_Pos
TIM_BDTR_DTG
TIM_BDTR_DTG_0
TIM_BDTR_DTG_1
TIM_BDTR_DTG_2
TIM_BDTR_DTG_3
TIM_BDTR_DTG_4
TIM_BDTR_DTG_5
TIM_BDTR_DTG_6
TIM_BDTR_DTG_7
TIM_BDTR_DTG_Msk
TIM_BDTR_DTG_Pos
TIM_BDTR_LOCK
TIM_BDTR_LOCK_0
TIM_BDTR_LOCK_1
TIM_BDTR_LOCK_Msk
TIM_BDTR_LOCK_Pos
TIM_BDTR_MOE
TIM_BDTR_MOE_Msk
TIM_BDTR_MOE_Pos
TIM_BDTR_OSSI
TIM_BDTR_OSSI_Msk
TIM_BDTR_OSSI_Pos
TIM_BDTR_OSSR
TIM_BDTR_OSSR_Msk
TIM_BDTR_OSSR_Pos
TIM_BREAKPOLARITY_HIGH
TIM_BREAKPOLARITY_LOW
TIM_BREAK_DISABLE
TIM_BREAK_ENABLE
TIM_CCER_CC1E
TIM_CCER_CC1E_Msk
TIM_CCER_CC1E_Pos
TIM_CCER_CC1NE
TIM_CCER_CC1NE_Msk
TIM_CCER_CC1NE_Pos
TIM_CCER_CC1NP
TIM_CCER_CC1NP_Msk
TIM_CCER_CC1NP_Pos
TIM_CCER_CC1P
TIM_CCER_CC1P_Msk
TIM_CCER_CC1P_Pos
TIM_CCER_CC2E
TIM_CCER_CC2E_Msk
TIM_CCER_CC2E_Pos
TIM_CCER_CC2NE
TIM_CCER_CC2NE_Msk
TIM_CCER_CC2NE_Pos
TIM_CCER_CC2NP
TIM_CCER_CC2NP_Msk
TIM_CCER_CC2NP_Pos
TIM_CCER_CC2P
TIM_CCER_CC2P_Msk
TIM_CCER_CC2P_Pos
TIM_CCER_CC3E
TIM_CCER_CC3E_Msk
TIM_CCER_CC3E_Pos
TIM_CCER_CC3NE
TIM_CCER_CC3NE_Msk
TIM_CCER_CC3NE_Pos
TIM_CCER_CC3NP
TIM_CCER_CC3NP_Msk
TIM_CCER_CC3NP_Pos
TIM_CCER_CC3P
TIM_CCER_CC3P_Msk
TIM_CCER_CC3P_Pos
TIM_CCER_CC4E
TIM_CCER_CC4E_Msk
TIM_CCER_CC4E_Pos
TIM_CCER_CC4NP
TIM_CCER_CC4NP_Msk
TIM_CCER_CC4NP_Pos
TIM_CCER_CC4P
TIM_CCER_CC4P_Msk
TIM_CCER_CC4P_Pos
TIM_CCER_CCxE_MASK
TIM_CCER_CCxNE_MASK
TIM_CCMR1_CC1S
TIM_CCMR1_CC1S_0
TIM_CCMR1_CC1S_1
TIM_CCMR1_CC1S_Msk
TIM_CCMR1_CC1S_Pos
TIM_CCMR1_CC2S
TIM_CCMR1_CC2S_0
TIM_CCMR1_CC2S_1
TIM_CCMR1_CC2S_Msk
TIM_CCMR1_CC2S_Pos
TIM_CCMR1_IC1F
TIM_CCMR1_IC1F_0
TIM_CCMR1_IC1F_1
TIM_CCMR1_IC1F_2
TIM_CCMR1_IC1F_3
TIM_CCMR1_IC1F_Msk
TIM_CCMR1_IC1F_Pos
TIM_CCMR1_IC1PSC
TIM_CCMR1_IC1PSC_0
TIM_CCMR1_IC1PSC_1
TIM_CCMR1_IC1PSC_Msk
TIM_CCMR1_IC1PSC_Pos
TIM_CCMR1_IC2F
TIM_CCMR1_IC2F_0
TIM_CCMR1_IC2F_1
TIM_CCMR1_IC2F_2
TIM_CCMR1_IC2F_3
TIM_CCMR1_IC2F_Msk
TIM_CCMR1_IC2F_Pos
TIM_CCMR1_IC2PSC
TIM_CCMR1_IC2PSC_0
TIM_CCMR1_IC2PSC_1
TIM_CCMR1_IC2PSC_Msk
TIM_CCMR1_IC2PSC_Pos
TIM_CCMR1_OC1CE
TIM_CCMR1_OC1CE_Msk
TIM_CCMR1_OC1CE_Pos
TIM_CCMR1_OC1FE
TIM_CCMR1_OC1FE_Msk
TIM_CCMR1_OC1FE_Pos
TIM_CCMR1_OC1M
TIM_CCMR1_OC1M_0
TIM_CCMR1_OC1M_1
TIM_CCMR1_OC1M_2
TIM_CCMR1_OC1M_Msk
TIM_CCMR1_OC1M_Pos
TIM_CCMR1_OC1PE
TIM_CCMR1_OC1PE_Msk
TIM_CCMR1_OC1PE_Pos
TIM_CCMR1_OC2CE
TIM_CCMR1_OC2CE_Msk
TIM_CCMR1_OC2CE_Pos
TIM_CCMR1_OC2FE
TIM_CCMR1_OC2FE_Msk
TIM_CCMR1_OC2FE_Pos
TIM_CCMR1_OC2M
TIM_CCMR1_OC2M_0
TIM_CCMR1_OC2M_1
TIM_CCMR1_OC2M_2
TIM_CCMR1_OC2M_Msk
TIM_CCMR1_OC2M_Pos
TIM_CCMR1_OC2PE
TIM_CCMR1_OC2PE_Msk
TIM_CCMR1_OC2PE_Pos
TIM_CCMR2_CC3S
TIM_CCMR2_CC3S_0
TIM_CCMR2_CC3S_1
TIM_CCMR2_CC3S_Msk
TIM_CCMR2_CC3S_Pos
TIM_CCMR2_CC4S
TIM_CCMR2_CC4S_0
TIM_CCMR2_CC4S_1
TIM_CCMR2_CC4S_Msk
TIM_CCMR2_CC4S_Pos
TIM_CCMR2_IC3F
TIM_CCMR2_IC3F_0
TIM_CCMR2_IC3F_1
TIM_CCMR2_IC3F_2
TIM_CCMR2_IC3F_3
TIM_CCMR2_IC3F_Msk
TIM_CCMR2_IC3F_Pos
TIM_CCMR2_IC3PSC
TIM_CCMR2_IC3PSC_0
TIM_CCMR2_IC3PSC_1
TIM_CCMR2_IC3PSC_Msk
TIM_CCMR2_IC3PSC_Pos
TIM_CCMR2_IC4F
TIM_CCMR2_IC4F_0
TIM_CCMR2_IC4F_1
TIM_CCMR2_IC4F_2
TIM_CCMR2_IC4F_3
TIM_CCMR2_IC4F_Msk
TIM_CCMR2_IC4F_Pos
TIM_CCMR2_IC4PSC
TIM_CCMR2_IC4PSC_0
TIM_CCMR2_IC4PSC_1
TIM_CCMR2_IC4PSC_Msk
TIM_CCMR2_IC4PSC_Pos
TIM_CCMR2_OC3CE
TIM_CCMR2_OC3CE_Msk
TIM_CCMR2_OC3CE_Pos
TIM_CCMR2_OC3FE
TIM_CCMR2_OC3FE_Msk
TIM_CCMR2_OC3FE_Pos
TIM_CCMR2_OC3M
TIM_CCMR2_OC3M_0
TIM_CCMR2_OC3M_1
TIM_CCMR2_OC3M_2
TIM_CCMR2_OC3M_Msk
TIM_CCMR2_OC3M_Pos
TIM_CCMR2_OC3PE
TIM_CCMR2_OC3PE_Msk
TIM_CCMR2_OC3PE_Pos
TIM_CCMR2_OC4CE
TIM_CCMR2_OC4CE_Msk
TIM_CCMR2_OC4CE_Pos
TIM_CCMR2_OC4FE
TIM_CCMR2_OC4FE_Msk
TIM_CCMR2_OC4FE_Pos
TIM_CCMR2_OC4M
TIM_CCMR2_OC4M_0
TIM_CCMR2_OC4M_1
TIM_CCMR2_OC4M_2
TIM_CCMR2_OC4M_Msk
TIM_CCMR2_OC4M_Pos
TIM_CCMR2_OC4PE
TIM_CCMR2_OC4PE_Msk
TIM_CCMR2_OC4PE_Pos
TIM_CCR1_CCR1
TIM_CCR1_CCR1_Msk
TIM_CCR1_CCR1_Pos
TIM_CCR2_CCR2
TIM_CCR2_CCR2_Msk
TIM_CCR2_CCR2_Pos
TIM_CCR3_CCR3
TIM_CCR3_CCR3_Msk
TIM_CCR3_CCR3_Pos
TIM_CCR4_CCR4
TIM_CCR4_CCR4_Msk
TIM_CCR4_CCR4_Pos
TIM_CCxN_DISABLE
TIM_CCxN_ENABLE
TIM_CCx_DISABLE
TIM_CCx_ENABLE
TIM_CHANNEL_1
TIM_CHANNEL_2
TIM_CHANNEL_3
TIM_CHANNEL_4
TIM_CHANNEL_ALL
TIM_CLEARINPUTPOLARITY_INVERTED
TIM_CLEARINPUTPOLARITY_NONINVERTED
TIM_CLEARINPUTPRESCALER_DIV1
TIM_CLEARINPUTPRESCALER_DIV2
TIM_CLEARINPUTPRESCALER_DIV4
TIM_CLEARINPUTPRESCALER_DIV8
TIM_CLEARINPUTSOURCE_ETR
TIM_CLEARINPUTSOURCE_NONE
TIM_CLEARINPUTSOURCE_OCREFCLR
TIM_CLOCKDIVISION_DIV1
TIM_CLOCKDIVISION_DIV2
TIM_CLOCKDIVISION_DIV4
TIM_CLOCKPOLARITY_BOTHEDGE
TIM_CLOCKPOLARITY_FALLING
TIM_CLOCKPOLARITY_INVERTED
TIM_CLOCKPOLARITY_NONINVERTED
TIM_CLOCKPOLARITY_RISING
TIM_CLOCKPRESCALER_DIV1
TIM_CLOCKPRESCALER_DIV2
TIM_CLOCKPRESCALER_DIV4
TIM_CLOCKPRESCALER_DIV8
TIM_CLOCKSOURCE_ETRMODE1
TIM_CLOCKSOURCE_ETRMODE2
TIM_CLOCKSOURCE_INTERNAL
TIM_CLOCKSOURCE_ITR0
TIM_CLOCKSOURCE_ITR1
TIM_CLOCKSOURCE_ITR2
TIM_CLOCKSOURCE_ITR3
TIM_CLOCKSOURCE_TI1
TIM_CLOCKSOURCE_TI2
TIM_CLOCKSOURCE_TI1ED
TIM_CNT_CNT
TIM_CNT_CNT_Msk
TIM_CNT_CNT_Pos
TIM_COMMUTATION_SOFTWARE
TIM_COMMUTATION_TRGI
TIM_COUNTERMODE_CENTERALIGNED1
TIM_COUNTERMODE_CENTERALIGNED2
TIM_COUNTERMODE_CENTERALIGNED3
TIM_COUNTERMODE_DOWN
TIM_COUNTERMODE_UP
TIM_CR1_ARPE
TIM_CR1_ARPE_Msk
TIM_CR1_ARPE_Pos
TIM_CR1_CEN
TIM_CR1_CEN_Msk
TIM_CR1_CEN_Pos
TIM_CR1_CKD
TIM_CR1_CKD_0
TIM_CR1_CKD_1
TIM_CR1_CKD_Msk
TIM_CR1_CKD_Pos
TIM_CR1_CMS
TIM_CR1_CMS_0
TIM_CR1_CMS_1
TIM_CR1_CMS_Msk
TIM_CR1_CMS_Pos
TIM_CR1_DIR
TIM_CR1_DIR_Msk
TIM_CR1_DIR_Pos
TIM_CR1_OPM
TIM_CR1_OPM_Msk
TIM_CR1_OPM_Pos
TIM_CR1_UDIS
TIM_CR1_UDIS_Msk
TIM_CR1_UDIS_Pos
TIM_CR1_URS
TIM_CR1_URS_Msk
TIM_CR1_URS_Pos
TIM_CR2_CCDS
TIM_CR2_CCDS_Msk
TIM_CR2_CCDS_Pos
TIM_CR2_CCPC
TIM_CR2_CCPC_Msk
TIM_CR2_CCPC_Pos
TIM_CR2_CCUS
TIM_CR2_CCUS_Msk
TIM_CR2_CCUS_Pos
TIM_CR2_MMS
TIM_CR2_MMS_0
TIM_CR2_MMS_1
TIM_CR2_MMS_2
TIM_CR2_MMS_Msk
TIM_CR2_MMS_Pos
TIM_CR2_OIS1
TIM_CR2_OIS2
TIM_CR2_OIS3
TIM_CR2_OIS4
TIM_CR2_OIS1N
TIM_CR2_OIS1N_Msk
TIM_CR2_OIS1N_Pos
TIM_CR2_OIS1_Msk
TIM_CR2_OIS1_Pos
TIM_CR2_OIS2N
TIM_CR2_OIS2N_Msk
TIM_CR2_OIS2N_Pos
TIM_CR2_OIS2_Msk
TIM_CR2_OIS2_Pos
TIM_CR2_OIS3N
TIM_CR2_OIS3N_Msk
TIM_CR2_OIS3N_Pos
TIM_CR2_OIS3_Msk
TIM_CR2_OIS3_Pos
TIM_CR2_OIS4_Msk
TIM_CR2_OIS4_Pos
TIM_CR2_TI1S
TIM_CR2_TI1S_Msk
TIM_CR2_TI1S_Pos
TIM_DCR_DBA
TIM_DCR_DBA_0
TIM_DCR_DBA_1
TIM_DCR_DBA_2
TIM_DCR_DBA_3
TIM_DCR_DBA_4
TIM_DCR_DBA_Msk
TIM_DCR_DBA_Pos
TIM_DCR_DBL
TIM_DCR_DBL_0
TIM_DCR_DBL_1
TIM_DCR_DBL_2
TIM_DCR_DBL_3
TIM_DCR_DBL_4
TIM_DCR_DBL_Msk
TIM_DCR_DBL_Pos
TIM_DIER_BIE
TIM_DIER_BIE_Msk
TIM_DIER_BIE_Pos
TIM_DIER_CC1DE
TIM_DIER_CC1DE_Msk
TIM_DIER_CC1DE_Pos
TIM_DIER_CC1IE
TIM_DIER_CC1IE_Msk
TIM_DIER_CC1IE_Pos
TIM_DIER_CC2DE
TIM_DIER_CC2DE_Msk
TIM_DIER_CC2DE_Pos
TIM_DIER_CC2IE
TIM_DIER_CC2IE_Msk
TIM_DIER_CC2IE_Pos
TIM_DIER_CC3DE
TIM_DIER_CC3DE_Msk
TIM_DIER_CC3DE_Pos
TIM_DIER_CC3IE
TIM_DIER_CC3IE_Msk
TIM_DIER_CC3IE_Pos
TIM_DIER_CC4DE
TIM_DIER_CC4DE_Msk
TIM_DIER_CC4DE_Pos
TIM_DIER_CC4IE
TIM_DIER_CC4IE_Msk
TIM_DIER_CC4IE_Pos
TIM_DIER_COMDE
TIM_DIER_COMDE_Msk
TIM_DIER_COMDE_Pos
TIM_DIER_COMIE
TIM_DIER_COMIE_Msk
TIM_DIER_COMIE_Pos
TIM_DIER_TDE
TIM_DIER_TDE_Msk
TIM_DIER_TDE_Pos
TIM_DIER_TIE
TIM_DIER_TIE_Msk
TIM_DIER_TIE_Pos
TIM_DIER_UDE
TIM_DIER_UDE_Msk
TIM_DIER_UDE_Pos
TIM_DIER_UIE
TIM_DIER_UIE_Msk
TIM_DIER_UIE_Pos
TIM_DMABASE_ARR
TIM_DMABASE_BDTR
TIM_DMABASE_CCER
TIM_DMABASE_CCMR1
TIM_DMABASE_CCMR2
TIM_DMABASE_CCR1
TIM_DMABASE_CCR2
TIM_DMABASE_CCR3
TIM_DMABASE_CCR4
TIM_DMABASE_CNT
TIM_DMABASE_CR1
TIM_DMABASE_CR2
TIM_DMABASE_DCR
TIM_DMABASE_DIER
TIM_DMABASE_DMAR
TIM_DMABASE_EGR
TIM_DMABASE_PSC
TIM_DMABASE_RCR
TIM_DMABASE_SMCR
TIM_DMABASE_SR
TIM_DMABURSTLENGTH_1TRANSFER
TIM_DMABURSTLENGTH_2TRANSFERS
TIM_DMABURSTLENGTH_3TRANSFERS
TIM_DMABURSTLENGTH_4TRANSFERS
TIM_DMABURSTLENGTH_5TRANSFERS
TIM_DMABURSTLENGTH_6TRANSFERS
TIM_DMABURSTLENGTH_7TRANSFERS
TIM_DMABURSTLENGTH_8TRANSFERS
TIM_DMABURSTLENGTH_9TRANSFERS
TIM_DMABURSTLENGTH_10TRANSFERS
TIM_DMABURSTLENGTH_11TRANSFERS
TIM_DMABURSTLENGTH_12TRANSFERS
TIM_DMABURSTLENGTH_13TRANSFERS
TIM_DMABURSTLENGTH_14TRANSFERS
TIM_DMABURSTLENGTH_15TRANSFERS
TIM_DMABURSTLENGTH_16TRANSFERS
TIM_DMABURSTLENGTH_17TRANSFERS
TIM_DMABURSTLENGTH_18TRANSFERS
TIM_DMAR_DMAB
TIM_DMAR_DMAB_Msk
TIM_DMAR_DMAB_Pos
TIM_DMA_CC1
TIM_DMA_CC2
TIM_DMA_CC3
TIM_DMA_CC4
TIM_DMA_COM
TIM_DMA_ID_CC1
TIM_DMA_ID_CC2
TIM_DMA_ID_CC3
TIM_DMA_ID_CC4
TIM_DMA_ID_COMMUTATION
TIM_DMA_ID_TRIGGER
TIM_DMA_ID_UPDATE
TIM_DMA_TRIGGER
TIM_DMA_UPDATE
TIM_EGR_BG
TIM_EGR_BG_Msk
TIM_EGR_BG_Pos
TIM_EGR_CC1G
TIM_EGR_CC1G_Msk
TIM_EGR_CC1G_Pos
TIM_EGR_CC2G
TIM_EGR_CC2G_Msk
TIM_EGR_CC2G_Pos
TIM_EGR_CC3G
TIM_EGR_CC3G_Msk
TIM_EGR_CC3G_Pos
TIM_EGR_CC4G
TIM_EGR_CC4G_Msk
TIM_EGR_CC4G_Pos
TIM_EGR_COMG
TIM_EGR_COMG_Msk
TIM_EGR_COMG_Pos
TIM_EGR_TG
TIM_EGR_TG_Msk
TIM_EGR_TG_Pos
TIM_EGR_UG
TIM_EGR_UG_Msk
TIM_EGR_UG_Pos
TIM_ENCODERINPUTPOLARITY_BOTHEDGE
TIM_ENCODERINPUTPOLARITY_FALLING
TIM_ENCODERINPUTPOLARITY_RISING
TIM_ENCODERMODE_TI1
TIM_ENCODERMODE_TI2
TIM_ENCODERMODE_TI12
TIM_ETRPOLARITY_INVERTED
TIM_ETRPOLARITY_NONINVERTED
TIM_ETRPRESCALER_DIV1
TIM_ETRPRESCALER_DIV2
TIM_ETRPRESCALER_DIV4
TIM_ETRPRESCALER_DIV8
TIM_EVENTSOURCE_BREAK
TIM_EVENTSOURCE_CC1
TIM_EVENTSOURCE_CC2
TIM_EVENTSOURCE_CC3
TIM_EVENTSOURCE_CC4
TIM_EVENTSOURCE_COM
TIM_EVENTSOURCE_TRIGGER
TIM_EVENTSOURCE_UPDATE
TIM_FLAG_BREAK
TIM_FLAG_CC1
TIM_FLAG_CC2
TIM_FLAG_CC3
TIM_FLAG_CC4
TIM_FLAG_CC1OF
TIM_FLAG_CC2OF
TIM_FLAG_CC3OF
TIM_FLAG_CC4OF
TIM_FLAG_COM
TIM_FLAG_TRIGGER
TIM_FLAG_UPDATE
TIM_ICPOLARITY_BOTHEDGE
TIM_ICPOLARITY_FALLING
TIM_ICPOLARITY_RISING
TIM_ICPSC_DIV1
TIM_ICPSC_DIV2
TIM_ICPSC_DIV4
TIM_ICPSC_DIV8
TIM_ICSELECTION_DIRECTTI
TIM_ICSELECTION_INDIRECTTI
TIM_ICSELECTION_TRC
TIM_INPUTCHANNELPOLARITY_BOTHEDGE
TIM_INPUTCHANNELPOLARITY_FALLING
TIM_INPUTCHANNELPOLARITY_RISING
TIM_IT_BREAK
TIM_IT_CC1
TIM_IT_CC2
TIM_IT_CC3
TIM_IT_CC4
TIM_IT_COM
TIM_IT_TRIGGER
TIM_IT_UPDATE
TIM_LOCKLEVEL_1
TIM_LOCKLEVEL_2
TIM_LOCKLEVEL_3
TIM_LOCKLEVEL_OFF
TIM_MASTERSLAVEMODE_DISABLE
TIM_MASTERSLAVEMODE_ENABLE
TIM_OCFAST_DISABLE
TIM_OCFAST_ENABLE
TIM_OCIDLESTATE_RESET
TIM_OCIDLESTATE_SET
TIM_OCMODE_ACTIVE
TIM_OCMODE_FORCED_ACTIVE
TIM_OCMODE_FORCED_INACTIVE
TIM_OCMODE_INACTIVE
TIM_OCMODE_PWM1
TIM_OCMODE_PWM2
TIM_OCMODE_TIMING
TIM_OCMODE_TOGGLE
TIM_OCNIDLESTATE_RESET
TIM_OCNIDLESTATE_SET
TIM_OCNPOLARITY_HIGH
TIM_OCNPOLARITY_LOW
TIM_OCPOLARITY_HIGH
TIM_OCPOLARITY_LOW
TIM_OPMODE_REPETITIVE
TIM_OPMODE_SINGLE
TIM_OSSI_DISABLE
TIM_OSSI_ENABLE
TIM_OSSR_DISABLE
TIM_OSSR_ENABLE
TIM_OUTPUTNSTATE_DISABLE
TIM_OUTPUTNSTATE_ENABLE
TIM_OUTPUTSTATE_DISABLE
TIM_OUTPUTSTATE_ENABLE
TIM_PSC_PSC
TIM_PSC_PSC_Msk
TIM_PSC_PSC_Pos
TIM_RCR_REP
TIM_RCR_REP_Msk
TIM_RCR_REP_Pos
TIM_SLAVEMODE_DISABLE
TIM_SLAVEMODE_EXTERNAL1
TIM_SLAVEMODE_GATED
TIM_SLAVEMODE_RESET
TIM_SLAVEMODE_TRIGGER
TIM_SMCR_ECE
TIM_SMCR_ECE_Msk
TIM_SMCR_ECE_Pos
TIM_SMCR_ETF
TIM_SMCR_ETF_0
TIM_SMCR_ETF_1
TIM_SMCR_ETF_2
TIM_SMCR_ETF_3
TIM_SMCR_ETF_Msk
TIM_SMCR_ETF_Pos
TIM_SMCR_ETP
TIM_SMCR_ETPS
TIM_SMCR_ETPS_0
TIM_SMCR_ETPS_1
TIM_SMCR_ETPS_Msk
TIM_SMCR_ETPS_Pos
TIM_SMCR_ETP_Msk
TIM_SMCR_ETP_Pos
TIM_SMCR_MSM
TIM_SMCR_MSM_Msk
TIM_SMCR_MSM_Pos
TIM_SMCR_OCCS
TIM_SMCR_OCCS_Msk
TIM_SMCR_OCCS_Pos
TIM_SMCR_SMS
TIM_SMCR_SMS_0
TIM_SMCR_SMS_1
TIM_SMCR_SMS_2
TIM_SMCR_SMS_Msk
TIM_SMCR_SMS_Pos
TIM_SMCR_TS
TIM_SMCR_TS_0
TIM_SMCR_TS_1
TIM_SMCR_TS_2
TIM_SMCR_TS_Msk
TIM_SMCR_TS_Pos
TIM_SR_BIF
TIM_SR_BIF_Msk
TIM_SR_BIF_Pos
TIM_SR_CC1IF
TIM_SR_CC1IF_Msk
TIM_SR_CC1IF_Pos
TIM_SR_CC1OF
TIM_SR_CC1OF_Msk
TIM_SR_CC1OF_Pos
TIM_SR_CC2IF
TIM_SR_CC2IF_Msk
TIM_SR_CC2IF_Pos
TIM_SR_CC2OF
TIM_SR_CC2OF_Msk
TIM_SR_CC2OF_Pos
TIM_SR_CC3IF
TIM_SR_CC3IF_Msk
TIM_SR_CC3IF_Pos
TIM_SR_CC3OF
TIM_SR_CC3OF_Msk
TIM_SR_CC3OF_Pos
TIM_SR_CC4IF
TIM_SR_CC4IF_Msk
TIM_SR_CC4IF_Pos
TIM_SR_CC4OF
TIM_SR_CC4OF_Msk
TIM_SR_CC4OF_Pos
TIM_SR_COMIF
TIM_SR_COMIF_Msk
TIM_SR_COMIF_Pos
TIM_SR_TIF
TIM_SR_TIF_Msk
TIM_SR_TIF_Pos
TIM_SR_UIF
TIM_SR_UIF_Msk
TIM_SR_UIF_Pos
TIM_TI1SELECTION_CH1
TIM_TI1SELECTION_XORCOMBINATION
TIM_TIM14_GPIO
TIM_TIM14_HSE
TIM_TIM14_MCO
TIM_TIM14_RTC
TIM_TRGO_ENABLE
TIM_TRGO_OC1
TIM_TRGO_OC1REF
TIM_TRGO_OC2REF
TIM_TRGO_OC3REF
TIM_TRGO_OC4REF
TIM_TRGO_RESET
TIM_TRGO_UPDATE
TIM_TRIGGERPOLARITY_BOTHEDGE
TIM_TRIGGERPOLARITY_FALLING
TIM_TRIGGERPOLARITY_INVERTED
TIM_TRIGGERPOLARITY_NONINVERTED
TIM_TRIGGERPOLARITY_RISING
TIM_TRIGGERPRESCALER_DIV1
TIM_TRIGGERPRESCALER_DIV2
TIM_TRIGGERPRESCALER_DIV4
TIM_TRIGGERPRESCALER_DIV8
TIM_TS_ETRF
TIM_TS_ITR0
TIM_TS_ITR1
TIM_TS_ITR2
TIM_TS_ITR3
TIM_TS_NONE
TIM_TS_TI1FP1
TIM_TS_TI1F_ED
TIM_TS_TI2FP2
UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
UART_ADVFEATURE_AUTOBAUDRATE_ENABLE
UART_ADVFEATURE_AUTOBAUDRATE_INIT
UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE
UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT
UART_ADVFEATURE_NO_INIT
UART_CR1_REG_INDEX
UART_CR2_REG_INDEX
UART_CR3_REG_INDEX
UART_FLAG_ABRE
UART_FLAG_ABRF
UART_FLAG_CTS
UART_FLAG_FE
UART_FLAG_IDLE
UART_FLAG_NE
UART_FLAG_ORE
UART_FLAG_PE
UART_FLAG_RXNE
UART_FLAG_TC
UART_FLAG_TXE
UART_HWCONTROL_CTS
UART_HWCONTROL_NONE
UART_HWCONTROL_RTS
UART_HWCONTROL_RTS_CTS
UART_IT_CTS
UART_IT_ERR
UART_IT_IDLE
UART_IT_MASK
UART_IT_PE
UART_IT_RXNE
UART_IT_TC
UART_IT_TXE
UART_LINBREAKDETECTLENGTH_10B
UART_MODE_RX
UART_MODE_TX
UART_MODE_TX_RX
UART_OVERSAMPLING_8
UART_OVERSAMPLING_16
UART_PARITY_EVEN
UART_PARITY_NONE
UART_PARITY_ODD
UART_STATE_DISABLE
UART_STATE_ENABLE
UART_STOPBITS_1
UART_STOPBITS_2
UART_WAKEUPMETHOD_ADDRESSMARK
UART_WAKEUPMETHOD_IDLELINE
UART_WORDLENGTH_8B
UART_WORDLENGTH_9B
UID_BASE
USART1
USART2
USART1_BASE
USART2_BASE
USART_BRR_DIV_Fraction
USART_BRR_DIV_Fraction_Msk
USART_BRR_DIV_Fraction_Pos
USART_BRR_DIV_Mantissa
USART_BRR_DIV_Mantissa_Msk
USART_BRR_DIV_Mantissa_Pos
USART_CR1_IDLEIE
USART_CR1_IDLEIE_Msk
USART_CR1_IDLEIE_Pos
USART_CR1_M
USART_CR1_M_Msk
USART_CR1_M_Pos
USART_CR1_PCE
USART_CR1_PCE_Msk
USART_CR1_PCE_Pos
USART_CR1_PEIE
USART_CR1_PEIE_Msk
USART_CR1_PEIE_Pos
USART_CR1_PS
USART_CR1_PS_Msk
USART_CR1_PS_Pos
USART_CR1_RE
USART_CR1_RE_Msk
USART_CR1_RE_Pos
USART_CR1_RWU
USART_CR1_RWU_Msk
USART_CR1_RWU_Pos
USART_CR1_RXNEIE
USART_CR1_RXNEIE_Msk
USART_CR1_RXNEIE_Pos
USART_CR1_SBK
USART_CR1_SBK_Msk
USART_CR1_SBK_Pos
USART_CR1_TCIE
USART_CR1_TCIE_Msk
USART_CR1_TCIE_Pos
USART_CR1_TE
USART_CR1_TE_Msk
USART_CR1_TE_Pos
USART_CR1_TXEIE
USART_CR1_TXEIE_Msk
USART_CR1_TXEIE_Pos
USART_CR1_UE
USART_CR1_UE_Msk
USART_CR1_UE_Pos
USART_CR1_WAKE
USART_CR1_WAKE_Msk
USART_CR1_WAKE_Pos
USART_CR2_ADD
USART_CR2_ADD_Msk
USART_CR2_ADD_Pos
USART_CR2_CLKEN
USART_CR2_CLKEN_Msk
USART_CR2_CLKEN_Pos
USART_CR2_CPHA
USART_CR2_CPHA_Msk
USART_CR2_CPHA_Pos
USART_CR2_CPOL
USART_CR2_CPOL_Msk
USART_CR2_CPOL_Pos
USART_CR2_LBCL
USART_CR2_LBCL_Msk
USART_CR2_LBCL_Pos
USART_CR2_STOP
USART_CR2_STOP_Msk
USART_CR2_STOP_Pos
USART_CR3_ABREN
USART_CR3_ABREN_Msk
USART_CR3_ABREN_Pos
USART_CR3_ABRMODE
USART_CR3_ABRMODE_0
USART_CR3_ABRMODE_1
USART_CR3_ABRMODE_Msk
USART_CR3_ABRMODE_Pos
USART_CR3_CTSE
USART_CR3_CTSE_Msk
USART_CR3_CTSE_Pos
USART_CR3_CTSIE
USART_CR3_CTSIE_Msk
USART_CR3_CTSIE_Pos
USART_CR3_DMAR
USART_CR3_DMAR_Msk
USART_CR3_DMAR_Pos
USART_CR3_DMAT
USART_CR3_DMAT_Msk
USART_CR3_DMAT_Pos
USART_CR3_EIE
USART_CR3_EIE_Msk
USART_CR3_EIE_Pos
USART_CR3_HDSEL
USART_CR3_HDSEL_Msk
USART_CR3_HDSEL_Pos
USART_CR3_OVER8
USART_CR3_OVER8_Msk
USART_CR3_OVER8_Pos
USART_CR3_RTSE
USART_CR3_RTSE_Msk
USART_CR3_RTSE_Pos
USART_DR_DR
USART_DR_DR_Msk
USART_DR_DR_Pos
USART_SR_ABRE
USART_SR_ABRE_Msk
USART_SR_ABRE_Pos
USART_SR_ABRF
USART_SR_ABRF_Msk
USART_SR_ABRF_Pos
USART_SR_ABRRQ
USART_SR_ABRRQ_Msk
USART_SR_ABRRQ_Pos
USART_SR_CTS
USART_SR_CTS_Msk
USART_SR_CTS_Pos
USART_SR_FE
USART_SR_FE_Msk
USART_SR_FE_Pos
USART_SR_IDLE
USART_SR_IDLE_Msk
USART_SR_IDLE_Pos
USART_SR_NE
USART_SR_NE_Msk
USART_SR_NE_Pos
USART_SR_ORE
USART_SR_ORE_Msk
USART_SR_ORE_Pos
USART_SR_PE
USART_SR_PE_Msk
USART_SR_PE_Pos
USART_SR_RXNE
USART_SR_RXNE_Msk
USART_SR_RXNE_Pos
USART_SR_TC
USART_SR_TC_Msk
USART_SR_TC_Pos
USART_SR_TXE
USART_SR_TXE_Msk
USART_SR_TXE_Pos
USE_RTOS
VDD_VALUE
WWDG
WWDG_BASE
WWDG_CFR_EWI
WWDG_CFR_EWI_Msk
WWDG_CFR_EWI_Pos
WWDG_CFR_W
WWDG_CFR_WDGTB
WWDG_CFR_WDGTB_0
WWDG_CFR_WDGTB_1
WWDG_CFR_WDGTB_Msk
WWDG_CFR_WDGTB_Pos
WWDG_CFR_W_0
WWDG_CFR_W_1
WWDG_CFR_W_2
WWDG_CFR_W_3
WWDG_CFR_W_4
WWDG_CFR_W_5
WWDG_CFR_W_6
WWDG_CFR_W_Msk
WWDG_CFR_W_Pos
WWDG_CR_T
WWDG_CR_T_0
WWDG_CR_T_1
WWDG_CR_T_2
WWDG_CR_T_3
WWDG_CR_T_4
WWDG_CR_T_5
WWDG_CR_T_6
WWDG_CR_T_Msk
WWDG_CR_T_Pos
WWDG_CR_WDGA
WWDG_CR_WDGA_Msk
WWDG_CR_WDGA_Pos
WWDG_EWI_DISABLE
WWDG_EWI_ENABLE
WWDG_FLAG_EWIF
WWDG_IT_EWI
WWDG_PRESCALER_1
WWDG_PRESCALER_2
WWDG_PRESCALER_4
WWDG_PRESCALER_8
WWDG_SR_EWIF
WWDG_SR_EWIF_Msk
WWDG_SR_EWIF_Pos
__CM0PLUS_CMSIS_VERSION
__CM0PLUS_CMSIS_VERSION_MAIN
__CM0PLUS_CMSIS_VERSION_SUB
__CM0PLUS_REV
__CORTEX_M
__FPU_USED
__MPU_PRESENT
__NVIC_PRIO_BITS
__PY32F0_DEVICE_VERSION
__PY32F0_DEVICE_VERSION_MAIN
__PY32F0_DEVICE_VERSION_RC
__PY32F0_DEVICE_VERSION_SUB1
__PY32F0_DEVICE_VERSION_SUB2
__VTOR_PRESENT
__Vendor_SysTickConfig
xPSR_C_Msk
xPSR_C_Pos
xPSR_ISR_Msk
xPSR_ISR_Pos
xPSR_N_Msk
xPSR_N_Pos
xPSR_T_Msk
xPSR_T_Pos
xPSR_V_Msk
xPSR_V_Pos
xPSR_Z_Msk
xPSR_Z_Pos

Statics§

AHBPrescTable
< AHB prescalers table values
APBPrescTable
< APB prescalers table values
HSIFreqTable
< HSI frequency table values
SystemCoreClock
< System Clock Frequency (Core Clock)
pFlash
@defgroup FLASH_Exported_Variables FLASH Exported Variables @{
uwTickFreq
uwTickPrio
@}

Functions§

FLASH_WaitForLastOperation
@defgroup FLASH_Private_types FLASH Private Types @{
HAL_ADC_AnalogWDGConfig
HAL_ADC_Calibration_Start
HAL_ADC_ConfigChannel
@addtogroup ADC_Exported_Functions_Group3 @{
HAL_ADC_ConvCpltCallback
HAL_ADC_ConvHalfCpltCallback
HAL_ADC_DeInit
HAL_ADC_ErrorCallback
HAL_ADC_GetCalibStatus
HAL_ADC_GetError
HAL_ADC_GetState
@addtogroup ADC_Exported_Functions_Group4 @{
HAL_ADC_GetValue
HAL_ADC_IRQHandler
HAL_ADC_Init
@addtogroup ADC_Exported_Functions_Group1 @{
HAL_ADC_LevelOutOfWindowCallback
HAL_ADC_MspDeInit
HAL_ADC_MspInit
HAL_ADC_PollForConversion
HAL_ADC_PollForEvent
HAL_ADC_SetCalibration
HAL_ADC_Start
@addtogroup ADC_Exported_Functions_Group2 @{
HAL_ADC_Start_DMA
HAL_ADC_Start_IT
HAL_ADC_Stop
HAL_ADC_Stop_DMA
HAL_ADC_Stop_IT
HAL_CRC_Accumulate
@defgroup CRC_Exported_Functions_Group2 Peripheral Control functions @{
HAL_CRC_Calculate
HAL_CRC_DeInit
HAL_CRC_GetState
@defgroup CRC_Exported_Functions_Group3 Peripheral State functions @{
HAL_CRC_Init
@defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions @{
HAL_CRC_MspDeInit
HAL_CRC_MspInit
HAL_DBGMCU_DisableDBGSleepMode
HAL_DBGMCU_DisableDBGStopMode
HAL_DBGMCU_EnableDBGSleepMode
HAL_DBGMCU_EnableDBGStopMode
HAL_DMA_Abort
HAL_DMA_Abort_IT
HAL_DMA_ChannelMap
HAL_DMA_DeInit
HAL_DMA_GetError
HAL_DMA_GetState
@addtogroup DMA_Exported_Functions_Group3 @{
HAL_DMA_IRQHandler
HAL_DMA_Init
@addtogroup DMA_Exported_Functions_Group1 @{
HAL_DMA_PollForTransfer
HAL_DMA_RegisterCallback
HAL_DMA_Start
@addtogroup DMA_Exported_Functions_Group2 @{
HAL_DMA_Start_IT
HAL_DMA_UnRegisterCallback
HAL_DeInit
HAL_Delay
HAL_EXTI_ClearConfigLine
HAL_EXTI_ClearPending
HAL_EXTI_GenerateSWI
HAL_EXTI_GetConfigLine
HAL_EXTI_GetHandle
HAL_EXTI_GetPending
HAL_EXTI_IRQHandler
@defgroup EXTI_Exported_Functions_Group2 IO operation functions @brief IO operation functions @{
HAL_EXTI_RegisterCallback
HAL_EXTI_SetConfigLine
@defgroup EXTI_Exported_Functions_Group1 Configuration functions @brief Configuration functions @{
HAL_FLASH_EndOfOperationCallback
HAL_FLASH_Erase
HAL_FLASH_Erase_IT
HAL_FLASH_GetError
@addtogroup FLASH_Exported_Functions_Group3 @{
HAL_FLASH_IRQHandler
HAL_FLASH_Lock
HAL_FLASH_OBGetConfig
HAL_FLASH_OBProgram
HAL_FLASH_OB_Launch
HAL_FLASH_OB_Lock
HAL_FLASH_OB_RDP_LevelConfig
HAL_FLASH_OB_Unlock
HAL_FLASH_OperationErrorCallback
HAL_FLASH_PageProgram
HAL_FLASH_PageProgram_IT
HAL_FLASH_Program
@addtogroup FLASH_Exported_Functions_Group1 @{
HAL_FLASH_Program_IT
HAL_FLASH_Unlock
@addtogroup FLASH_Exported_Functions_Group2 @{
HAL_GET_ADC_TSCAL1
HAL_GET_ADC_TSCAL2
HAL_GPIO_DeInit
HAL_GPIO_EXTI_Callback
HAL_GPIO_EXTI_IRQHandler
HAL_GPIO_Init
@defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions @brief Initialization and Configuration functions @{
HAL_GPIO_LockPin
HAL_GPIO_ReadPin
@defgroup GPIO_Exported_Functions_Group2 IO operation functions @brief IO operation functions @{
HAL_GPIO_TogglePin
HAL_GPIO_WritePin
HAL_GetDEVID
HAL_GetHalVersion
HAL_GetREVID
HAL_GetTick
HAL_GetTickFreq
HAL_GetTickPrio
HAL_GetUIDw0
HAL_GetUIDw1
HAL_GetUIDw2
HAL_HalfDuplex_EnableReceiver
HAL_HalfDuplex_EnableTransmitter
HAL_HalfDuplex_Init
HAL_I2C_AbortCpltCallback
HAL_I2C_AddrCallback
HAL_I2C_DeInit
HAL_I2C_DisableListen_IT
HAL_I2C_ER_IRQHandler
HAL_I2C_EV_IRQHandler
@addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks @{ / /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA)
HAL_I2C_EnableListen_IT
HAL_I2C_ErrorCallback
HAL_I2C_GetError
HAL_I2C_GetMode
HAL_I2C_GetState
@addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions @{
HAL_I2C_Init
@addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions @{
HAL_I2C_IsDeviceReady
HAL_I2C_ListenCpltCallback
HAL_I2C_MasterRxCpltCallback
HAL_I2C_MasterTxCpltCallback
HAL_I2C_Master_Abort_IT
HAL_I2C_Master_Receive
HAL_I2C_Master_Receive_DMA
HAL_I2C_Master_Receive_IT
HAL_I2C_Master_Seq_Receive_DMA
HAL_I2C_Master_Seq_Receive_IT
HAL_I2C_Master_Seq_Transmit_DMA
HAL_I2C_Master_Seq_Transmit_IT
HAL_I2C_Master_Transmit
Blocking mode: Polling
HAL_I2C_Master_Transmit_DMA
Non-Blocking mode: DMA
HAL_I2C_Master_Transmit_IT
Non-Blocking mode: Interrupt
HAL_I2C_MemRxCpltCallback
HAL_I2C_MemTxCpltCallback
HAL_I2C_Mem_Read
HAL_I2C_Mem_Read_DMA
HAL_I2C_Mem_Read_IT
HAL_I2C_Mem_Write
HAL_I2C_Mem_Write_DMA
HAL_I2C_Mem_Write_IT
HAL_I2C_MspDeInit
HAL_I2C_MspInit
HAL_I2C_SlaveRxCpltCallback
HAL_I2C_SlaveTxCpltCallback
HAL_I2C_Slave_Receive
HAL_I2C_Slave_Receive_DMA
HAL_I2C_Slave_Receive_IT
HAL_I2C_Slave_Seq_Receive_DMA
HAL_I2C_Slave_Seq_Receive_IT
HAL_I2C_Slave_Seq_Transmit_DMA
HAL_I2C_Slave_Seq_Transmit_IT
HAL_I2C_Slave_Transmit
HAL_I2C_Slave_Transmit_DMA
HAL_I2C_Slave_Transmit_IT
HAL_IWDG_Init
@defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions @{
HAL_IWDG_Refresh
@defgroup IWDG_Exported_Functions_Group2 IO operation functions @{
HAL_IncTick
@addtogroup HAL_Exported_Functions_Group2 @{
HAL_Init
HAL_InitTick
HAL_LED_IRQHandler
HAL_LED_Init
@defgroup LED_Exported_Functions_Group LED operation functions @brief LED operation functions @{
HAL_LED_LightCpltCallback
HAL_LED_MspInit
HAL_LED_SetComDisplay
HAL_LPTIM_AutoReloadMatchCallback
HAL_LPTIM_DeInit
HAL_LPTIM_GetState
HAL_LPTIM_IRQHandler
HAL_LPTIM_Init
@defgroup LPTIM_Exported_Functions LPTIM Exported Functions @{
HAL_LPTIM_MspDeInit
HAL_LPTIM_MspInit
HAL_LPTIM_ReadAutoReload
HAL_LPTIM_ReadCounter
HAL_LPTIM_SetOnce_Start
HAL_LPTIM_SetOnce_Start_IT
HAL_LPTIM_SetOnce_Stop
HAL_LPTIM_SetOnce_Stop_IT
HAL_MspDeInit
HAL_MspInit
HAL_MultiProcessor_EnterMuteMode
HAL_MultiProcessor_ExitMuteMode
HAL_MultiProcessor_Init
HAL_NVIC_ClearPendingIRQ
HAL_NVIC_DisableIRQ
HAL_NVIC_EnableIRQ
HAL_NVIC_GetPendingIRQ
HAL_NVIC_GetPriority
@defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions @brief Cortex control functions @{
HAL_NVIC_SetPendingIRQ
HAL_NVIC_SetPriority
@defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions @brief Initialization and Configuration functions @{
HAL_NVIC_SystemReset
HAL_PWR_ConfigBIAS
HAL_PWR_ConfigPVD
HAL_PWR_ConfigStopMode
HAL_PWR_DeInit
@defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions @{
HAL_PWR_DisableBkUpAccess
HAL_PWR_DisablePVD
HAL_PWR_DisableSEVOnPend
HAL_PWR_DisableSleepOnExit
HAL_PWR_EnableBkUpAccess
@defgroup PWR_Exported_Functions_Group2 Peripheral Control functions @{
HAL_PWR_EnablePVD
HAL_PWR_EnableSEVOnPend
HAL_PWR_EnableSleepOnExit
HAL_PWR_EnterSLEEPMode
HAL_PWR_EnterSTOPMode
HAL_PWR_PVD_Callback
HAL_PWR_PVD_IRQHandler
HAL_RCCEx_DisableLSCO
HAL_RCCEx_EnableLSCO
HAL_RCCEx_GetPeriphCLKConfig
HAL_RCCEx_GetPeriphCLKFreq
HAL_RCCEx_PeriphCLKConfig
@addtogroup RCCEx_Exported_Functions_Group1 @{
HAL_RCC_ADC_CLK_DISABLE
HAL_RCC_ADC_CLK_ENABLE
HAL_RCC_ADC_FORCE_RESET
HAL_RCC_ADC_IS_CLK_DISABLED
HAL_RCC_ADC_IS_CLK_ENABLED
HAL_RCC_ADC_RELEASE_RESET
HAL_RCC_AHB_FORCE_RESET
HAL_RCC_AHB_RELEASE_RESET
HAL_RCC_APB1_FORCE_RESET
HAL_RCC_APB1_RELEASE_RESET
HAL_RCC_APB2_FORCE_RESET
HAL_RCC_APB2_RELEASE_RESET
HAL_RCC_BACKUPRESET_FORCE
HAL_RCC_BACKUPRESET_RELEASE
HAL_RCC_CLEAR_RESET_FLAGS
HAL_RCC_COMP1_CLK_DISABLE
HAL_RCC_COMP1_CLK_ENABLE
HAL_RCC_COMP1_FORCE_RESET
HAL_RCC_COMP1_IS_CLK_DISABLED
HAL_RCC_COMP1_IS_CLK_ENABLED
HAL_RCC_COMP1_RELEASE_RESET
HAL_RCC_COMP2_CLK_DISABLE
HAL_RCC_COMP2_CLK_ENABLE
HAL_RCC_COMP2_FORCE_RESET
HAL_RCC_COMP2_IS_CLK_DISABLED
HAL_RCC_COMP2_IS_CLK_ENABLED
HAL_RCC_COMP2_RELEASE_RESET
HAL_RCC_CRC_CLK_DISABLE
HAL_RCC_CRC_CLK_ENABLE
HAL_RCC_CRC_FORCE_RESET
HAL_RCC_CRC_IS_CLK_DISABLED
HAL_RCC_CRC_IS_CLK_ENABLED
HAL_RCC_CRC_RELEASE_RESET
HAL_RCC_CSSCallback
HAL_RCC_ClockConfig
HAL_RCC_DBGMCU_CLK_DISABLE
HAL_RCC_DBGMCU_CLK_ENABLE
HAL_RCC_DBGMCU_FORCE_RESET
HAL_RCC_DBGMCU_IS_CLK_DISABLED
HAL_RCC_DBGMCU_IS_CLK_ENABLED
HAL_RCC_DBGMCU_RELEASE_RESET
HAL_RCC_DMA_CLK_DISABLE
HAL_RCC_DMA_CLK_ENABLE
HAL_RCC_DMA_FORCE_RESET
HAL_RCC_DMA_IS_CLK_DISABLED
HAL_RCC_DMA_IS_CLK_ENABLED
HAL_RCC_DMA_RELEASE_RESET
HAL_RCC_DeInit
@addtogroup RCC_Exported_Functions_Group1 @{
HAL_RCC_DisableLSECSS
HAL_RCC_EnableCSS
HAL_RCC_EnableLSECSS
HAL_RCC_FLASH_CLK_DISABLE
HAL_RCC_FLASH_CLK_ENABLE
HAL_RCC_FLASH_IS_CLK_DISABLED
HAL_RCC_FLASH_IS_CLK_ENABLED
HAL_RCC_GET_PLL_OSCSOURCE
HAL_RCC_GET_RTC_SOURCE
HAL_RCC_GET_SYSCLK_SOURCE
HAL_RCC_GPIOA_CLK_DISABLE
HAL_RCC_GPIOA_CLK_ENABLE
HAL_RCC_GPIOA_FORCE_RESET
HAL_RCC_GPIOA_IS_CLK_DISABLED
HAL_RCC_GPIOA_IS_CLK_ENABLED
HAL_RCC_GPIOA_RELEASE_RESET
HAL_RCC_GPIOB_CLK_DISABLE
HAL_RCC_GPIOB_CLK_ENABLE
HAL_RCC_GPIOB_FORCE_RESET
HAL_RCC_GPIOB_IS_CLK_DISABLED
HAL_RCC_GPIOB_IS_CLK_ENABLED
HAL_RCC_GPIOB_RELEASE_RESET
HAL_RCC_GPIOF_CLK_DISABLE
HAL_RCC_GPIOF_CLK_ENABLE
HAL_RCC_GPIOF_FORCE_RESET
HAL_RCC_GPIOF_IS_CLK_DISABLED
HAL_RCC_GPIOF_IS_CLK_ENABLED
HAL_RCC_GPIOF_RELEASE_RESET
HAL_RCC_GetClockConfig
HAL_RCC_GetHCLKFreq
HAL_RCC_GetOscConfig
HAL_RCC_GetPCLK1Freq
HAL_RCC_GetSysClockFreq
HAL_RCC_HSI_DISABLE
HAL_RCC_HSI_ENABLE
HAL_RCC_I2C1_IS_CLK_DISABLED
HAL_RCC_I2C_CLK_DISABLE
HAL_RCC_I2C_CLK_ENABLE
HAL_RCC_I2C_FORCE_RESET
HAL_RCC_I2C_IS_CLK_ENABLED
HAL_RCC_I2C_RELEASE_RESET
HAL_RCC_IOP_FORCE_RESET
HAL_RCC_IOP_RELEASE_RESET
HAL_RCC_LED_CLK_DISABLE
HAL_RCC_LED_CLK_ENABLE
HAL_RCC_LED_FORCE_RESET
HAL_RCC_LED_IS_CLK_DISABLED
HAL_RCC_LED_IS_CLK_ENABLED
HAL_RCC_LED_RELEASE_RESET
HAL_RCC_LPTIM_CLK_DISABLE
HAL_RCC_LPTIM_CLK_ENABLE
HAL_RCC_LPTIM_FORCE_RESET
HAL_RCC_LPTIM_IS_CLK_DISABLED
HAL_RCC_LPTIM_IS_CLK_ENABLED
HAL_RCC_LPTIM_RELEASE_RESET
HAL_RCC_LSECSSCallback
HAL_RCC_LSI_DISABLE
HAL_RCC_LSI_ENABLE
HAL_RCC_MCOConfig
@addtogroup RCC_Exported_Functions_Group2 @{
HAL_RCC_NMI_IRQHandler
HAL_RCC_OscConfig
HAL_RCC_PLL_DISABLE
HAL_RCC_PLL_ENABLE
HAL_RCC_PWR_CLK_DISABLE
HAL_RCC_PWR_CLK_ENABLE
HAL_RCC_PWR_FORCE_RESET
HAL_RCC_PWR_IS_CLK_DISABLED
HAL_RCC_PWR_IS_CLK_ENABLED
HAL_RCC_PWR_RELEASE_RESET
HAL_RCC_RTCAPB_CLK_DISABLE
HAL_RCC_RTCAPB_CLK_ENABLE
HAL_RCC_RTCAPB_IS_CLK_DISABLED
HAL_RCC_RTCAPB_IS_CLK_ENABLED
HAL_RCC_RTC_DISABLE
HAL_RCC_RTC_ENABLE
HAL_RCC_SPI1_CLK_DISABLE
HAL_RCC_SPI1_CLK_ENABLE
HAL_RCC_SPI1_FORCE_RESET
HAL_RCC_SPI1_IS_CLK_DISABLED
HAL_RCC_SPI1_IS_CLK_ENABLED
HAL_RCC_SPI1_RELEASE_RESET
HAL_RCC_SPI2_CLK_DISABLE
HAL_RCC_SPI2_CLK_ENABLE
HAL_RCC_SPI2_FORCE_RESET
HAL_RCC_SPI2_IS_CLK_DISABLED
HAL_RCC_SPI2_IS_CLK_ENABLED
HAL_RCC_SPI2_RELEASE_RESET
HAL_RCC_SRAM_CLK_DISABLE
HAL_RCC_SRAM_CLK_ENABLE
HAL_RCC_SYSCFG_CLK_DISABLE
HAL_RCC_SYSCFG_CLK_ENABLE
HAL_RCC_SYSCFG_FORCE_RESET
HAL_RCC_SYSCFG_IS_CLK_DISABLED
HAL_RCC_SYSCFG_IS_CLK_ENABLED
HAL_RCC_SYSCFG_RELEASE_RESET
HAL_RCC_TIM1_CLK_DISABLE
HAL_RCC_TIM1_CLK_ENABLE
HAL_RCC_TIM1_FORCE_RESET
HAL_RCC_TIM1_IS_CLK_DISABLED
HAL_RCC_TIM1_IS_CLK_ENABLED
HAL_RCC_TIM1_RELEASE_RESET
HAL_RCC_TIM3_CLK_DISABLE
HAL_RCC_TIM3_CLK_ENABLE
HAL_RCC_TIM3_FORCE_RESET
HAL_RCC_TIM3_IS_CLK_DISABLED
HAL_RCC_TIM3_IS_CLK_ENABLED
HAL_RCC_TIM3_RELEASE_RESET
HAL_RCC_TIM14_CLK_DISABLE
HAL_RCC_TIM14_CLK_ENABLE
HAL_RCC_TIM14_FORCE_RESET
HAL_RCC_TIM14_IS_CLK_DISABLED
HAL_RCC_TIM14_IS_CLK_ENABLED
HAL_RCC_TIM14_RELEASE_RESET
HAL_RCC_TIM16_CLK_DISABLE
HAL_RCC_TIM16_CLK_ENABLE
HAL_RCC_TIM16_FORCE_RESET
HAL_RCC_TIM16_IS_CLK_DISABLED
HAL_RCC_TIM16_IS_CLK_ENABLED
HAL_RCC_TIM16_RELEASE_RESET
HAL_RCC_TIM17_CLK_DISABLE
HAL_RCC_TIM17_CLK_ENABLE
HAL_RCC_TIM17_FORCE_RESET
HAL_RCC_TIM17_IS_CLK_DISABLED
HAL_RCC_TIM17_IS_CLK_ENABLED
HAL_RCC_TIM17_RELEASE_RESET
HAL_RCC_USART1_CLK_DISABLE
HAL_RCC_USART1_CLK_ENABLE
HAL_RCC_USART1_FORCE_RESET
HAL_RCC_USART1_IS_CLK_DISABLED
HAL_RCC_USART1_IS_CLK_ENABLED
HAL_RCC_USART1_RELEASE_RESET
HAL_RCC_USART2_CLK_DISABLE
HAL_RCC_USART2_CLK_ENABLE
HAL_RCC_USART2_FORCE_RESET
HAL_RCC_USART2_IS_CLK_DISABLED
HAL_RCC_USART2_IS_CLK_ENABLED
HAL_RCC_USART2_RELEASE_RESET
HAL_RCC_WWDG_CLK_ENABLE
HAL_RCC_WWDG_IS_CLK_DISABLED
HAL_RCC_WWDG_IS_CLK_ENABLED
HAL_RTCEx_DeactivateSecond
HAL_RTCEx_RTCEventCallback
HAL_RTCEx_RTCEventErrorCallback
HAL_RTCEx_RTCIRQHandler
HAL_RTCEx_SetSecond_IT
@addtogroup RTCEx_Exported_Functions_Group2 @{
HAL_RTCEx_SetSmoothCalib
@addtogroup RTCEx_Exported_Functions_Group3 @{
HAL_RTC_AlarmAEventCallback
HAL_RTC_AlarmIRQHandler
HAL_RTC_DeInit
HAL_RTC_DeactivateAlarm
HAL_RTC_GetAlarm
HAL_RTC_GetDate
HAL_RTC_GetState
@addtogroup RTC_Exported_Functions_Group4 @{
HAL_RTC_GetTime
HAL_RTC_Init
@addtogroup RTC_Exported_Functions_Group1 @{
HAL_RTC_MspDeInit
HAL_RTC_MspInit
HAL_RTC_PollForAlarmAEvent
HAL_RTC_SetAlarm
@addtogroup RTC_Exported_Functions_Group3 @{
HAL_RTC_SetAlarm_IT
HAL_RTC_SetDate
HAL_RTC_SetTime
@addtogroup RTC_Exported_Functions_Group2 @{
HAL_RTC_WaitForSynchro
@addtogroup RTC_Exported_Functions_Group5 @{
HAL_ResumeTick
HAL_SPI_Abort
HAL_SPI_AbortCpltCallback
HAL_SPI_Abort_IT
HAL_SPI_DMAPause
HAL_SPI_DMAResume
HAL_SPI_DMAStop
HAL_SPI_DeInit
HAL_SPI_ErrorCallback
HAL_SPI_GetError
HAL_SPI_GetState
@addtogroup SPI_Exported_Functions_Group3 @{
HAL_SPI_IRQHandler
HAL_SPI_Init
@addtogroup SPI_Exported_Functions_Group1 @{
HAL_SPI_MspDeInit
HAL_SPI_MspInit
HAL_SPI_Receive
HAL_SPI_Receive_DMA
HAL_SPI_Receive_IT
HAL_SPI_RxCpltCallback
HAL_SPI_RxHalfCpltCallback
HAL_SPI_Transmit
@addtogroup SPI_Exported_Functions_Group2 @{
HAL_SPI_TransmitReceive
HAL_SPI_TransmitReceive_DMA
HAL_SPI_TransmitReceive_IT
HAL_SPI_Transmit_DMA
HAL_SPI_Transmit_IT
HAL_SPI_TxCpltCallback
HAL_SPI_TxHalfCpltCallback
HAL_SPI_TxRxCpltCallback
HAL_SPI_TxRxHalfCpltCallback
HAL_SYSCFG_DMA_Req
HAL_SYSTICK_CLKSourceConfig
HAL_SYSTICK_Callback
HAL_SYSTICK_Config
HAL_SYSTICK_IRQHandler
HAL_SetTickFreq
HAL_SuspendTick
HAL_TIMEx_BreakCallback
HAL_TIMEx_CommutCallback
@addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions @brief Extended Callbacks functions @{
HAL_TIMEx_CommutHalfCpltCallback
HAL_TIMEx_ConfigBreakDeadTime
HAL_TIMEx_ConfigCommutEvent
@addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions @brief Peripheral Control functions @{
HAL_TIMEx_ConfigCommutEvent_DMA
HAL_TIMEx_ConfigCommutEvent_IT
HAL_TIMEx_HallSensor_DeInit
HAL_TIMEx_HallSensor_GetState
@addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions @brief Extended Peripheral State functions @{
HAL_TIMEx_HallSensor_Init
@addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions @brief Timer Hall Sensor functions @{
HAL_TIMEx_HallSensor_MspDeInit
HAL_TIMEx_HallSensor_MspInit
HAL_TIMEx_HallSensor_Start
HAL_TIMEx_HallSensor_Start_DMA
HAL_TIMEx_HallSensor_Start_IT
HAL_TIMEx_HallSensor_Stop
HAL_TIMEx_HallSensor_Stop_DMA
HAL_TIMEx_HallSensor_Stop_IT
HAL_TIMEx_MasterConfigSynchronization
HAL_TIMEx_OCN_Start
@addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions @brief Timer Complementary Output Compare functions @{
HAL_TIMEx_OCN_Start_DMA
HAL_TIMEx_OCN_Start_IT
HAL_TIMEx_OCN_Stop
HAL_TIMEx_OCN_Stop_DMA
HAL_TIMEx_OCN_Stop_IT
HAL_TIMEx_OnePulseN_Start
@addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions @brief Timer Complementary One Pulse functions @{
HAL_TIMEx_OnePulseN_Start_IT
HAL_TIMEx_OnePulseN_Stop
HAL_TIMEx_OnePulseN_Stop_IT
HAL_TIMEx_PWMN_Start
@addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions @brief Timer Complementary PWM functions @{
HAL_TIMEx_PWMN_Start_DMA
HAL_TIMEx_PWMN_Start_IT
HAL_TIMEx_PWMN_Stop
HAL_TIMEx_PWMN_Stop_DMA
HAL_TIMEx_PWMN_Stop_IT
HAL_TIMEx_RemapConfig
HAL_TIM_Base_DeInit
HAL_TIM_Base_GetState
@defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions @brief Peripheral State functions @{
HAL_TIM_Base_Init
@addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions @brief Time Base functions @{
HAL_TIM_Base_MspDeInit
HAL_TIM_Base_MspInit
HAL_TIM_Base_Start
HAL_TIM_Base_Start_DMA
HAL_TIM_Base_Start_IT
HAL_TIM_Base_Stop
HAL_TIM_Base_Stop_DMA
HAL_TIM_Base_Stop_IT
HAL_TIM_ConfigClockSource
HAL_TIM_ConfigOCrefClear
HAL_TIM_ConfigTI1Input
HAL_TIM_DMABurst_MultiReadStart
HAL_TIM_DMABurst_MultiWriteStart
HAL_TIM_DMABurst_ReadStart
HAL_TIM_DMABurst_ReadStop
HAL_TIM_DMABurst_WriteStart
HAL_TIM_DMABurst_WriteStop
HAL_TIM_Encoder_DeInit
HAL_TIM_Encoder_GetState
HAL_TIM_Encoder_Init
@addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions @brief TIM Encoder functions @{
HAL_TIM_Encoder_MspDeInit
HAL_TIM_Encoder_MspInit
HAL_TIM_Encoder_Start
HAL_TIM_Encoder_Start_DMA
HAL_TIM_Encoder_Start_IT
HAL_TIM_Encoder_Stop
HAL_TIM_Encoder_Stop_DMA
HAL_TIM_Encoder_Stop_IT
HAL_TIM_ErrorCallback
HAL_TIM_GenerateEvent
HAL_TIM_IC_CaptureCallback
HAL_TIM_IC_CaptureHalfCpltCallback
HAL_TIM_IC_ConfigChannel
HAL_TIM_IC_DeInit
HAL_TIM_IC_GetState
HAL_TIM_IC_Init
@addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions @brief TIM Input Capture functions @{
HAL_TIM_IC_MspDeInit
HAL_TIM_IC_MspInit
HAL_TIM_IC_Start
HAL_TIM_IC_Start_DMA
HAL_TIM_IC_Start_IT
HAL_TIM_IC_Stop
HAL_TIM_IC_Stop_DMA
HAL_TIM_IC_Stop_IT
HAL_TIM_IRQHandler
@addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management @brief IRQ handler management @{
HAL_TIM_OC_ConfigChannel
@defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions @brief Peripheral Control functions @{
HAL_TIM_OC_DeInit
HAL_TIM_OC_DelayElapsedCallback
HAL_TIM_OC_GetState
HAL_TIM_OC_Init
@addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions @brief TIM Output Compare functions @{
HAL_TIM_OC_MspDeInit
HAL_TIM_OC_MspInit
HAL_TIM_OC_Start
HAL_TIM_OC_Start_DMA
HAL_TIM_OC_Start_IT
HAL_TIM_OC_Stop
HAL_TIM_OC_Stop_DMA
HAL_TIM_OC_Stop_IT
HAL_TIM_OnePulse_ConfigChannel
HAL_TIM_OnePulse_DeInit
HAL_TIM_OnePulse_GetState
HAL_TIM_OnePulse_Init
@addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions @brief TIM One Pulse functions @{
HAL_TIM_OnePulse_MspDeInit
HAL_TIM_OnePulse_MspInit
HAL_TIM_OnePulse_Start
HAL_TIM_OnePulse_Start_IT
HAL_TIM_OnePulse_Stop
HAL_TIM_OnePulse_Stop_IT
HAL_TIM_PWM_ConfigChannel
HAL_TIM_PWM_DeInit
HAL_TIM_PWM_GetState
HAL_TIM_PWM_Init
@addtogroup TIM_Exported_Functions_Group3 TIM PWM functions @brief TIM PWM functions @{
HAL_TIM_PWM_MspDeInit
HAL_TIM_PWM_MspInit
HAL_TIM_PWM_PulseFinishedCallback
HAL_TIM_PWM_PulseFinishedHalfCpltCallback
HAL_TIM_PWM_Start
HAL_TIM_PWM_Start_DMA
HAL_TIM_PWM_Start_IT
HAL_TIM_PWM_Stop
HAL_TIM_PWM_Stop_DMA
HAL_TIM_PWM_Stop_IT
HAL_TIM_PeriodElapsedCallback
@defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions @brief TIM Callbacks functions @{
HAL_TIM_PeriodElapsedHalfCpltCallback
HAL_TIM_ReadCapturedValue
HAL_TIM_SlaveConfigSynchro
HAL_TIM_SlaveConfigSynchro_IT
HAL_TIM_TriggerCallback
HAL_TIM_TriggerHalfCpltCallback
HAL_UART_Abort
HAL_UART_AbortCpltCallback
HAL_UART_AbortReceive
HAL_UART_AbortReceiveCpltCallback
HAL_UART_AbortReceive_IT
HAL_UART_AbortTransmit
HAL_UART_AbortTransmitCpltCallback
HAL_UART_AbortTransmit_IT
HAL_UART_Abort_IT
HAL_UART_DMAPause
HAL_UART_DMAResume
HAL_UART_DMAStop
HAL_UART_DeInit
HAL_UART_ErrorCallback
HAL_UART_GetError
HAL_UART_GetState
@addtogroup UART_Exported_Functions_Group4 @{
HAL_UART_IRQHandler
HAL_UART_IdleFrameDetectCpltCallback
HAL_UART_Init
@addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions @{
HAL_UART_MspDeInit
HAL_UART_MspInit
HAL_UART_Receive
HAL_UART_Receive_DMA
HAL_UART_Receive_IT
HAL_UART_RxCpltCallback
HAL_UART_RxHalfCpltCallback
HAL_UART_SendBreak
@addtogroup UART_Exported_Functions_Group3 @{
HAL_UART_Transmit
@addtogroup UART_Exported_Functions_Group IO operation functions @{
HAL_UART_Transmit_DMA
HAL_UART_Transmit_IT
HAL_UART_TxCpltCallback
HAL_UART_TxHalfCpltCallback
HAL_WWDG_EarlyWakeupCallback
HAL_WWDG_IRQHandler
HAL_WWDG_Init
@addtogroup WWDG_Exported_Functions_Group1 @{
HAL_WWDG_MspInit
HAL_WWDG_Refresh
@addtogroup WWDG_Exported_Functions_Group2 @{
RCC_GET_HSICALIBRATION_4MHz
RCC_GET_HSICALIBRATION_8MHz
RCC_GET_HSICALIBRATION_16MHz
RCC_GET_HSICALIBRATION_22p12MHz
RCC_GET_HSICALIBRATION_24MHz
SystemCoreClockUpdate
SystemInit
@addtogroup PY32F0xx_System_Exported_Functions @{
TIMEx_DMACommutationCplt
TIMEx_DMACommutationHalfCplt
TIM_Base_SetConfig
@defgroup TIM_Private_Functions TIM Private Functions @{
TIM_CCxChannelCmd
TIM_DMACaptureCplt
TIM_DMACaptureHalfCplt
TIM_DMADelayPulseCplt
TIM_DMADelayPulseHalfCplt
TIM_DMAError
TIM_ETR_SetConfig
TIM_OC2_SetConfig
TIM_TI1_SetConfig

Type Aliases§

ADC_HandleTypeDef
@brief ADC handle Structure definition
DMA_HandleTypeDef
@brief DMA handle Structure definition
EXTI_CallbackIDTypeDef
@defgroup EXTI_Exported_Types EXTI Exported Types @{
ErrorStatus
FlagStatus
@brief Exported_types
FunctionalState
GPIO_PinState
@brief GPIO Bit SET and Bit RESET enumeration
HAL_CRC_StateTypeDef
@brief CRC HAL State Structure definition
HAL_DMA_CallbackIDTypeDef
@brief HAL DMA Callback ID structure definition
HAL_DMA_LevelCompleteTypeDef
@brief HAL DMA Error Code structure definition
HAL_DMA_StateTypeDef
@brief HAL DMA State structures definition
HAL_I2C_ModeTypeDef
@defgroup HAL_mode_structure_definition HAL mode structure definition @brief HAL Mode structure definition @note HAL I2C Mode value coding follow below described bitmap :\n b7 (not used)\n x : Should be set to 0\n b6\n 0 : None\n 1 : Memory (HAL I2C communication is in Memory Mode)\n b5\n 0 : None\n 1 : Slave (HAL I2C communication is in Slave Mode)\n b4\n 0 : None\n 1 : Master (HAL I2C communication is in Master Mode)\n b3-b2-b1-b0 (not used)\n xxxx : Should be set to 0000 @{
HAL_I2C_StateTypeDef
@defgroup HAL_state_structure_definition HAL state structure definition @brief HAL State structure definition @note HAL I2C State value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : Abort (Abort user request on going) 10 : Timeout 11 : Error b5 Peripheral initilisation status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called) b4 (not used) x : Should be set to 0 b3 0 : Ready or Busy (No Listen mode ongoing) 1 : Listen (Peripheral in Address Listen Mode) b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing) @{
HAL_LED_StateTypeDef
@brief HAL LED State structures definition
HAL_LPTIM_StateTypeDef
@brief HAL LPTIM State structure definition
HAL_LockTypeDef
@brief HAL Lock structures definition
HAL_RTCStateTypeDef
@brief HAL State structures definition
HAL_SPI_StateTypeDef
@brief HAL SPI State structure definition
HAL_StatusTypeDef
@brief HAL Status structures definition
HAL_TIM_ActiveChannel
@brief HAL Active channel structures definition
HAL_TIM_StateTypeDef
@brief HAL State structures definition
HAL_TickFreqTypeDef
@defgroup HAL_TICK_FREQ Tick Frequency @{
HAL_UART_StateTypeDef
@brief HAL UART State structures definition @note HAL UART State value is a combination of 2 different substates: gState and RxState. - gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (Peripheral busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing) - RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 Peripheral initialization status 0 : Reset (Peripheral not initialized) 1 : Init done (Peripheral not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
I2C_HandleTypeDef
@defgroup I2C_handle_Structure_definition I2C handle Structure definition @brief I2C handle Structure definition @{
IRQn_Type
SPI_HandleTypeDef
@brief SPI handle Structure definition
UART_HandleTypeDef
@brief UART handle Structure definition
int_fast8_t
int_fast16_t
int_fast32_t
int_fast64_t
int_least8_t
int_least16_t
int_least32_t
int_least64_t
intmax_t
uint_fast8_t
uint_fast16_t
uint_fast32_t
uint_fast64_t
uint_least8_t
uint_least16_t
uint_least32_t
uint_least64_t
uintmax_t

Unions§

APSR_Type
\brief Union type to access the Application Program Status Register (APSR).
CONTROL_Type
\brief Union type to access the Control Registers (CONTROL).
IPSR_Type
\brief Union type to access the Interrupt Program Status Register (IPSR).
xPSR_Type
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).