py32_hal/usart/
buffered.rs

1//! Buffered UART driver
2
3// The following code is modified from embassy-stm32
4// https://github.com/embassy-rs/embassy/tree/main/embassy-stm32
5// Special thanks to the Embassy Project and its contributors for their work!
6
7use core::future::poll_fn;
8use core::marker::PhantomData;
9use core::slice;
10use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
11use core::task::Poll;
12
13use embassy_embedded_hal::SetConfig;
14use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
15use embassy_hal_internal::{Peripheral, PeripheralRef};
16use embassy_sync::waitqueue::AtomicWaker;
17
18use super::{
19    clear_interrupt_flags, configure, rdr, reconfigure, send_break, sr, tdr, Config, ConfigError,
20    CtsPin, Error, Info, Instance, Regs, RtsPin, RxPin, TxPin,
21};
22use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
23use crate::interrupt::{self, InterruptExt};
24use crate::time::Hertz;
25
26/// Interrupt handler.
27pub struct InterruptHandler<T: Instance> {
28    _phantom: PhantomData<T>,
29}
30
31impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
32    unsafe fn on_interrupt() {
33        on_interrupt(T::info().regs, T::buffered_state())
34    }
35}
36
37unsafe fn on_interrupt(r: Regs, state: &'static State) {
38    // RX
39    let sr_val = sr(r).read();
40    // On v1 & v2, reading DR clears the rxne, error and idle interrupt
41    // flags. Keep this close to the SR read to reduce the chance of a
42    // flag being set in-between.
43    let dr = if sr_val.rxne() || (sr_val.ore() || sr_val.idle()) {
44        Some(rdr(r).read_volatile())
45    } else {
46        None
47    };
48    clear_interrupt_flags(r, sr_val);
49
50    if sr_val.pe() {
51        warn!("Parity error");
52    }
53    if sr_val.fe() {
54        warn!("Framing error");
55    }
56    if sr_val.ne() {
57        warn!("Noise error");
58    }
59    if sr_val.ore() {
60        warn!("Overrun error");
61    }
62    if sr_val.rxne() {
63        let mut rx_writer = state.rx_buf.writer();
64        let buf = rx_writer.push_slice();
65        if !buf.is_empty() {
66            if let Some(byte) = dr {
67                buf[0] = byte;
68                rx_writer.push_done(1);
69            }
70        } else {
71            // FIXME: Should we disable any further RX interrupts when the buffer becomes full.
72        }
73
74        if !state.rx_buf.is_empty() {
75            state.rx_waker.wake();
76        }
77    }
78
79    if sr_val.idle() {
80        state.rx_waker.wake();
81    }
82
83    // With `usart_v4` hardware FIFO is enabled and Transmission complete (TC)
84    // indicates that all bytes are pushed out from the FIFO.
85    // For other usart variants it shows that last byte from the buffer was just sent.
86    if sr_val.tc() {
87        // For others it is cleared above with `clear_interrupt_flags`.
88        sr(r).modify(|w| w.set_tc(false));
89
90        r.cr1().modify(|w| {
91            w.set_tcie(false);
92        });
93
94        state.tx_done.store(true, Ordering::Release);
95        state.tx_waker.wake();
96    }
97
98    // TX
99    if sr(r).read().txe() {
100        let mut tx_reader = state.tx_buf.reader();
101        let buf = tx_reader.pop_slice();
102        if !buf.is_empty() {
103            r.cr1().modify(|w| {
104                w.set_txeie(true);
105            });
106
107            // Enable transmission complete interrupt when last byte is going to be sent out.
108            if buf.len() == 1 {
109                r.cr1().modify(|w| {
110                    w.set_tcie(true);
111                });
112            }
113
114            tdr(r).write_volatile(buf[0].into());
115            tx_reader.pop_done(1);
116        } else {
117            // Disable interrupt until we have something to transmit again.
118            r.cr1().modify(|w| {
119                w.set_txeie(false);
120            });
121        }
122    }
123}
124
125pub(super) struct State {
126    rx_waker: AtomicWaker,
127    rx_buf: RingBuffer,
128    tx_waker: AtomicWaker,
129    tx_buf: RingBuffer,
130    tx_done: AtomicBool,
131    tx_rx_refcount: AtomicU8,
132}
133
134impl State {
135    pub(super) const fn new() -> Self {
136        Self {
137            rx_buf: RingBuffer::new(),
138            tx_buf: RingBuffer::new(),
139            rx_waker: AtomicWaker::new(),
140            tx_waker: AtomicWaker::new(),
141            tx_done: AtomicBool::new(true),
142            tx_rx_refcount: AtomicU8::new(0),
143        }
144    }
145}
146
147/// Bidirectional buffered UART
148pub struct BufferedUart<'d> {
149    rx: BufferedUartRx<'d>,
150    tx: BufferedUartTx<'d>,
151}
152
153/// Tx-only buffered UART
154///
155/// Created with [BufferedUart::split]
156pub struct BufferedUartTx<'d> {
157    info: &'static Info,
158    state: &'static State,
159    kernel_clock: Hertz,
160    tx: Option<PeripheralRef<'d, AnyPin>>,
161    cts: Option<PeripheralRef<'d, AnyPin>>,
162    de: Option<PeripheralRef<'d, AnyPin>>,
163}
164
165/// Rx-only buffered UART
166///
167/// Created with [BufferedUart::split]
168pub struct BufferedUartRx<'d> {
169    info: &'static Info,
170    state: &'static State,
171    kernel_clock: Hertz,
172    rx: Option<PeripheralRef<'d, AnyPin>>,
173    rts: Option<PeripheralRef<'d, AnyPin>>,
174}
175
176impl<'d> SetConfig for BufferedUart<'d> {
177    type Config = Config;
178    type ConfigError = ConfigError;
179
180    fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
181        self.set_config(config)
182    }
183}
184
185impl<'d> SetConfig for BufferedUartRx<'d> {
186    type Config = Config;
187    type ConfigError = ConfigError;
188
189    fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
190        self.set_config(config)
191    }
192}
193
194impl<'d> SetConfig for BufferedUartTx<'d> {
195    type Config = Config;
196    type ConfigError = ConfigError;
197
198    fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
199        self.set_config(config)
200    }
201}
202
203impl<'d> BufferedUart<'d> {
204    /// Create a new bidirectional buffered UART driver
205    pub fn new<T: Instance>(
206        peri: impl Peripheral<P = T> + 'd,
207        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
208        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
209        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
210        tx_buffer: &'d mut [u8],
211        rx_buffer: &'d mut [u8],
212        config: Config,
213    ) -> Result<Self, ConfigError> {
214        Self::new_inner(
215            peri,
216            new_pin!(rx, AfType::input(config.rx_pull)),
217            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
218            None,
219            None,
220            None,
221            tx_buffer,
222            rx_buffer,
223            config,
224        )
225    }
226
227    /// Create a new bidirectional buffered UART driver with request-to-send and clear-to-send pins
228    pub fn new_with_rtscts<T: Instance>(
229        peri: impl Peripheral<P = T> + 'd,
230        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
231        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
232        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
233        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
234        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
235        tx_buffer: &'d mut [u8],
236        rx_buffer: &'d mut [u8],
237        config: Config,
238    ) -> Result<Self, ConfigError> {
239        Self::new_inner(
240            peri,
241            new_pin!(rx, AfType::input(Pull::None)),
242            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
243            new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)),
244            new_pin!(cts, AfType::input(Pull::None)),
245            None,
246            tx_buffer,
247            rx_buffer,
248            config,
249        )
250    }
251
252    /// Create a new bidirectional buffered UART driver with only the RTS pin as the DE pin
253    pub fn new_with_rts_as_de<T: Instance>(
254        peri: impl Peripheral<P = T> + 'd,
255        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
256        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
257        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
258        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
259        tx_buffer: &'d mut [u8],
260        rx_buffer: &'d mut [u8],
261        config: Config,
262    ) -> Result<Self, ConfigError> {
263        Self::new_inner(
264            peri,
265            new_pin!(rx, AfType::input(Pull::None)),
266            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
267            None,
268            None,
269            new_pin!(rts, AfType::input(Pull::None)), // RTS mapped used as DE
270            tx_buffer,
271            rx_buffer,
272            config,
273        )
274    }
275
276    /// Create a new bidirectional buffered UART driver with only the request-to-send pin
277    pub fn new_with_rts<T: Instance>(
278        peri: impl Peripheral<P = T> + 'd,
279        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
280        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
281        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
282        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
283        tx_buffer: &'d mut [u8],
284        rx_buffer: &'d mut [u8],
285        config: Config,
286    ) -> Result<Self, ConfigError> {
287        Self::new_inner(
288            peri,
289            new_pin!(rx, AfType::input(Pull::None)),
290            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
291            new_pin!(rts, AfType::input(Pull::None)),
292            None, // no CTS
293            None, // no DE
294            tx_buffer,
295            rx_buffer,
296            config,
297        )
298    }
299
300    fn new_inner<T: Instance>(
301        _peri: impl Peripheral<P = T> + 'd,
302        rx: Option<PeripheralRef<'d, AnyPin>>,
303        tx: Option<PeripheralRef<'d, AnyPin>>,
304        rts: Option<PeripheralRef<'d, AnyPin>>,
305        cts: Option<PeripheralRef<'d, AnyPin>>,
306        de: Option<PeripheralRef<'d, AnyPin>>,
307        tx_buffer: &'d mut [u8],
308        rx_buffer: &'d mut [u8],
309        config: Config,
310    ) -> Result<Self, ConfigError> {
311        let info = T::info();
312        let state = T::buffered_state();
313        let kernel_clock = T::frequency();
314
315        let mut this = Self {
316            rx: BufferedUartRx {
317                info,
318                state,
319                kernel_clock,
320                rx,
321                rts,
322            },
323            tx: BufferedUartTx {
324                info,
325                state,
326                kernel_clock,
327                tx,
328                cts,
329                de,
330            },
331        };
332        this.enable_and_configure(tx_buffer, rx_buffer, &config)?;
333        Ok(this)
334    }
335
336    fn enable_and_configure(
337        &mut self,
338        tx_buffer: &'d mut [u8],
339        rx_buffer: &'d mut [u8],
340        config: &Config,
341    ) -> Result<(), ConfigError> {
342        let info = self.rx.info;
343        let state = self.rx.state;
344        state.tx_rx_refcount.store(2, Ordering::Relaxed);
345
346        info.rcc.enable_and_reset();
347
348        let len = tx_buffer.len();
349        unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
350        let len = rx_buffer.len();
351        unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
352
353        info.regs.cr3().write(|w| {
354            w.set_rtse(self.rx.rts.is_some());
355            w.set_ctse(self.tx.cts.is_some());
356        });
357        configure(info, self.rx.kernel_clock, &config, true, true)?;
358
359        info.regs.cr1().modify(|w| {
360            w.set_rxneie(true);
361            w.set_idleie(true);
362        });
363
364        info.interrupt.unpend();
365        unsafe { info.interrupt.enable() };
366
367        Ok(())
368    }
369
370    /// Split the driver into a Tx and Rx part (useful for sending to separate tasks)
371    pub fn split(self) -> (BufferedUartTx<'d>, BufferedUartRx<'d>) {
372        (self.tx, self.rx)
373    }
374
375    /// Reconfigure the driver
376    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
377        reconfigure(self.rx.info, self.rx.kernel_clock, config)?;
378
379        self.rx.info.regs.cr1().modify(|w| {
380            w.set_rxneie(true);
381            w.set_idleie(true);
382        });
383
384        Ok(())
385    }
386
387    /// Send break character
388    pub fn send_break(&self) {
389        self.tx.send_break()
390    }
391}
392
393impl<'d> BufferedUartRx<'d> {
394    async fn read(&self, buf: &mut [u8]) -> Result<usize, Error> {
395        poll_fn(move |cx| {
396            let state = self.state;
397            let mut rx_reader = unsafe { state.rx_buf.reader() };
398            let data = rx_reader.pop_slice();
399
400            if !data.is_empty() {
401                let len = data.len().min(buf.len());
402                buf[..len].copy_from_slice(&data[..len]);
403
404                let do_pend = state.rx_buf.is_full();
405                rx_reader.pop_done(len);
406
407                if do_pend {
408                    self.info.interrupt.pend();
409                }
410
411                return Poll::Ready(Ok(len));
412            }
413
414            state.rx_waker.register(cx.waker());
415            Poll::Pending
416        })
417        .await
418    }
419
420    fn blocking_read(&self, buf: &mut [u8]) -> Result<usize, Error> {
421        loop {
422            let state = self.state;
423            let mut rx_reader = unsafe { state.rx_buf.reader() };
424            let data = rx_reader.pop_slice();
425
426            if !data.is_empty() {
427                let len = data.len().min(buf.len());
428                buf[..len].copy_from_slice(&data[..len]);
429
430                let do_pend = state.rx_buf.is_full();
431                rx_reader.pop_done(len);
432
433                if do_pend {
434                    self.info.interrupt.pend();
435                }
436
437                return Ok(len);
438            }
439        }
440    }
441
442    async fn fill_buf(&self) -> Result<&[u8], Error> {
443        poll_fn(move |cx| {
444            let state = self.state;
445            let mut rx_reader = unsafe { state.rx_buf.reader() };
446            let (p, n) = rx_reader.pop_buf();
447            if n == 0 {
448                state.rx_waker.register(cx.waker());
449                return Poll::Pending;
450            }
451
452            let buf = unsafe { slice::from_raw_parts(p, n) };
453            Poll::Ready(Ok(buf))
454        })
455        .await
456    }
457
458    fn consume(&self, amt: usize) {
459        let state = self.state;
460        let mut rx_reader = unsafe { state.rx_buf.reader() };
461        let full = state.rx_buf.is_full();
462        rx_reader.pop_done(amt);
463        if full {
464            self.info.interrupt.pend();
465        }
466    }
467
468    /// we are ready to read if there is data in the buffer
469    fn read_ready(&mut self) -> Result<bool, Error> {
470        let state = self.state;
471        Ok(!state.rx_buf.is_empty())
472    }
473
474    /// Reconfigure the driver
475    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
476        reconfigure(self.info, self.kernel_clock, config)?;
477
478        self.info.regs.cr1().modify(|w| {
479            w.set_rxneie(true);
480            w.set_idleie(true);
481        });
482
483        Ok(())
484    }
485}
486
487impl<'d> BufferedUartTx<'d> {
488    async fn write(&self, buf: &[u8]) -> Result<usize, Error> {
489        poll_fn(move |cx| {
490            let state = self.state;
491            state.tx_done.store(false, Ordering::Release);
492
493            let empty = state.tx_buf.is_empty();
494
495            let mut tx_writer = unsafe { state.tx_buf.writer() };
496            let data = tx_writer.push_slice();
497            if data.is_empty() {
498                state.tx_waker.register(cx.waker());
499                return Poll::Pending;
500            }
501
502            let n = data.len().min(buf.len());
503            data[..n].copy_from_slice(&buf[..n]);
504            tx_writer.push_done(n);
505
506            if empty {
507                self.info.interrupt.pend();
508            }
509
510            Poll::Ready(Ok(n))
511        })
512        .await
513    }
514
515    async fn flush(&self) -> Result<(), Error> {
516        poll_fn(move |cx| {
517            let state = self.state;
518
519            if !state.tx_done.load(Ordering::Acquire) {
520                state.tx_waker.register(cx.waker());
521                return Poll::Pending;
522            }
523
524            Poll::Ready(Ok(()))
525        })
526        .await
527    }
528
529    fn blocking_write(&self, buf: &[u8]) -> Result<usize, Error> {
530        loop {
531            let state = self.state;
532            let empty = state.tx_buf.is_empty();
533
534            let mut tx_writer = unsafe { state.tx_buf.writer() };
535            let data = tx_writer.push_slice();
536            if !data.is_empty() {
537                let n = data.len().min(buf.len());
538                data[..n].copy_from_slice(&buf[..n]);
539                tx_writer.push_done(n);
540
541                if empty {
542                    self.info.interrupt.pend();
543                }
544
545                return Ok(n);
546            }
547        }
548    }
549
550    fn blocking_flush(&self) -> Result<(), Error> {
551        loop {
552            let state = self.state;
553            if state.tx_buf.is_empty() {
554                return Ok(());
555            }
556        }
557    }
558
559    /// Reconfigure the driver
560    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
561        reconfigure(self.info, self.kernel_clock, config)?;
562
563        self.info.regs.cr1().modify(|w| {
564            w.set_rxneie(true);
565            w.set_idleie(true);
566        });
567
568        Ok(())
569    }
570
571    /// Send break character
572    pub fn send_break(&self) {
573        send_break(&self.info.regs);
574    }
575}
576
577impl<'d> Drop for BufferedUartRx<'d> {
578    fn drop(&mut self) {
579        let state = self.state;
580        unsafe {
581            state.rx_buf.deinit();
582
583            // TX is inactive if the the buffer is not available.
584            // We can now unregister the interrupt handler
585            if state.tx_buf.len() == 0 {
586                self.info.interrupt.disable();
587            }
588        }
589
590        self.rx.as_ref().map(|x| x.set_as_disconnected());
591        self.rts.as_ref().map(|x| x.set_as_disconnected());
592        drop_tx_rx(self.info, state);
593    }
594}
595
596impl<'d> Drop for BufferedUartTx<'d> {
597    fn drop(&mut self) {
598        let state = self.state;
599        unsafe {
600            state.tx_buf.deinit();
601
602            // RX is inactive if the the buffer is not available.
603            // We can now unregister the interrupt handler
604            if state.rx_buf.len() == 0 {
605                self.info.interrupt.disable();
606            }
607        }
608
609        self.tx.as_ref().map(|x| x.set_as_disconnected());
610        self.cts.as_ref().map(|x| x.set_as_disconnected());
611        self.de.as_ref().map(|x| x.set_as_disconnected());
612        drop_tx_rx(self.info, state);
613    }
614}
615
616fn drop_tx_rx(info: &Info, state: &State) {
617    // We cannot use atomic subtraction here, because it's not supported for all targets
618    let is_last_drop = critical_section::with(|_| {
619        let refcount = state.tx_rx_refcount.load(Ordering::Relaxed);
620        assert!(refcount >= 1);
621        state.tx_rx_refcount.store(refcount - 1, Ordering::Relaxed);
622        refcount == 1
623    });
624    if is_last_drop {
625        info.rcc.disable();
626    }
627}
628
629impl<'d> embedded_io_async::ErrorType for BufferedUart<'d> {
630    type Error = Error;
631}
632
633impl<'d> embedded_io_async::ErrorType for BufferedUartRx<'d> {
634    type Error = Error;
635}
636
637impl<'d> embedded_io_async::ErrorType for BufferedUartTx<'d> {
638    type Error = Error;
639}
640
641impl<'d> embedded_io_async::Read for BufferedUart<'d> {
642    async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
643        self.rx.read(buf).await
644    }
645}
646
647impl<'d> embedded_io_async::Read for BufferedUartRx<'d> {
648    async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
649        Self::read(self, buf).await
650    }
651}
652
653impl<'d> embedded_io_async::ReadReady for BufferedUart<'d> {
654    fn read_ready(&mut self) -> Result<bool, Self::Error> {
655        BufferedUartRx::<'d>::read_ready(&mut self.rx)
656    }
657}
658
659impl<'d> embedded_io_async::ReadReady for BufferedUartRx<'d> {
660    fn read_ready(&mut self) -> Result<bool, Self::Error> {
661        Self::read_ready(self)
662    }
663}
664
665impl<'d> embedded_io_async::BufRead for BufferedUart<'d> {
666    async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
667        self.rx.fill_buf().await
668    }
669
670    fn consume(&mut self, amt: usize) {
671        self.rx.consume(amt)
672    }
673}
674
675impl<'d> embedded_io_async::BufRead for BufferedUartRx<'d> {
676    async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
677        Self::fill_buf(self).await
678    }
679
680    fn consume(&mut self, amt: usize) {
681        Self::consume(self, amt)
682    }
683}
684
685impl<'d> embedded_io_async::Write for BufferedUart<'d> {
686    async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
687        self.tx.write(buf).await
688    }
689
690    async fn flush(&mut self) -> Result<(), Self::Error> {
691        self.tx.flush().await
692    }
693}
694
695impl<'d> embedded_io_async::Write for BufferedUartTx<'d> {
696    async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
697        Self::write(self, buf).await
698    }
699
700    async fn flush(&mut self) -> Result<(), Self::Error> {
701        Self::flush(self).await
702    }
703}
704
705impl<'d> embedded_io::Read for BufferedUart<'d> {
706    fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
707        self.rx.blocking_read(buf)
708    }
709}
710
711impl<'d> embedded_io::Read for BufferedUartRx<'d> {
712    fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
713        self.blocking_read(buf)
714    }
715}
716
717impl<'d> embedded_io::Write for BufferedUart<'d> {
718    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
719        self.tx.blocking_write(buf)
720    }
721
722    fn flush(&mut self) -> Result<(), Self::Error> {
723        self.tx.blocking_flush()
724    }
725}
726
727impl<'d> embedded_io::Write for BufferedUartTx<'d> {
728    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
729        Self::blocking_write(self, buf)
730    }
731
732    fn flush(&mut self) -> Result<(), Self::Error> {
733        Self::blocking_flush(self)
734    }
735}
736
737impl<'d> embedded_hal_02::serial::Read<u8> for BufferedUartRx<'d> {
738    type Error = Error;
739
740    fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
741        let r = self.info.regs;
742        unsafe {
743            let sr = sr(r).read();
744            if sr.pe() {
745                rdr(r).read_volatile();
746                Err(nb::Error::Other(Error::Parity))
747            } else if sr.fe() {
748                rdr(r).read_volatile();
749                Err(nb::Error::Other(Error::Framing))
750            } else if sr.ne() {
751                rdr(r).read_volatile();
752                Err(nb::Error::Other(Error::Noise))
753            } else if sr.ore() {
754                rdr(r).read_volatile();
755                Err(nb::Error::Other(Error::Overrun))
756            } else if sr.rxne() {
757                Ok(rdr(r).read_volatile())
758            } else {
759                Err(nb::Error::WouldBlock)
760            }
761        }
762    }
763}
764
765impl<'d> embedded_hal_02::blocking::serial::Write<u8> for BufferedUartTx<'d> {
766    type Error = Error;
767
768    fn bwrite_all(&mut self, mut buffer: &[u8]) -> Result<(), Self::Error> {
769        while !buffer.is_empty() {
770            match self.blocking_write(buffer) {
771                Ok(0) => panic!("zero-length write."),
772                Ok(n) => buffer = &buffer[n..],
773                Err(e) => return Err(e),
774            }
775        }
776        Ok(())
777    }
778
779    fn bflush(&mut self) -> Result<(), Self::Error> {
780        self.blocking_flush()
781    }
782}
783
784impl<'d> embedded_hal_02::serial::Read<u8> for BufferedUart<'d> {
785    type Error = Error;
786
787    fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
788        embedded_hal_02::serial::Read::read(&mut self.rx)
789    }
790}
791
792impl<'d> embedded_hal_02::blocking::serial::Write<u8> for BufferedUart<'d> {
793    type Error = Error;
794
795    fn bwrite_all(&mut self, mut buffer: &[u8]) -> Result<(), Self::Error> {
796        while !buffer.is_empty() {
797            match self.tx.blocking_write(buffer) {
798                Ok(0) => panic!("zero-length write."),
799                Ok(n) => buffer = &buffer[n..],
800                Err(e) => return Err(e),
801            }
802        }
803        Ok(())
804    }
805
806    fn bflush(&mut self) -> Result<(), Self::Error> {
807        self.tx.blocking_flush()
808    }
809}
810
811impl<'d> embedded_hal_nb::serial::ErrorType for BufferedUart<'d> {
812    type Error = Error;
813}
814
815impl<'d> embedded_hal_nb::serial::ErrorType for BufferedUartTx<'d> {
816    type Error = Error;
817}
818
819impl<'d> embedded_hal_nb::serial::ErrorType for BufferedUartRx<'d> {
820    type Error = Error;
821}
822
823impl<'d> embedded_hal_nb::serial::Read for BufferedUartRx<'d> {
824    fn read(&mut self) -> nb::Result<u8, Self::Error> {
825        embedded_hal_02::serial::Read::read(self)
826    }
827}
828
829impl<'d> embedded_hal_nb::serial::Write for BufferedUartTx<'d> {
830    fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
831        self.blocking_write(&[char])
832            .map(drop)
833            .map_err(nb::Error::Other)
834    }
835
836    fn flush(&mut self) -> nb::Result<(), Self::Error> {
837        self.blocking_flush().map_err(nb::Error::Other)
838    }
839}
840
841impl<'d> embedded_hal_nb::serial::Read for BufferedUart<'d> {
842    fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
843        embedded_hal_02::serial::Read::read(&mut self.rx)
844    }
845}
846
847impl<'d> embedded_hal_nb::serial::Write for BufferedUart<'d> {
848    fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
849        self.tx
850            .blocking_write(&[char])
851            .map(drop)
852            .map_err(nb::Error::Other)
853    }
854
855    fn flush(&mut self) -> nb::Result<(), Self::Error> {
856        self.tx.blocking_flush().map_err(nb::Error::Other)
857    }
858}
py32_hal/usart/buffered.rs

py32_hal/usart/
buffered.rs
