psoc_pac_psoc6_02/
lib.rs

1/*
2(c) 2016-2026, Infineon Technologies AG or an affiliate of Infineon Technologies AG.
3
4
5
6    SPDX-License-Identifier: Apache-2.0
7
8
9
10    Licensed under the Apache License, Version 2.0 (the "License");
11
12    you may not use this file except in compliance with the License.
13
14    You may obtain a copy of the License at
15
16
17
18      http://www.apache.org/licenses/LICENSE-2.0
19
20
21
22    Unless required by applicable law or agreed to in writing, software
23
24    distributed under the License is distributed on an "AS IS" BASIS,
25
26    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
27
28    See the License for the specific language governing permissions and
29
30    limitations under the License.
31*/
32// Generated from SVD 1.0, with svd2pac 0.7.0 on Fri, 15 May 2026 21:08:51 +0000
33#![no_std]
34#![allow(non_camel_case_types)]
35#![allow(non_snake_case)]
36#![doc = "PSOC6_02"]
37pub mod common;
38pub use common::*;
39
40#[cfg(feature = "backup")]
41pub mod backup;
42#[cfg(feature = "cpuss")]
43pub mod cpuss;
44#[cfg(feature = "crypto")]
45pub mod crypto;
46#[cfg(feature = "csd0")]
47pub mod csd;
48#[cfg(feature = "dmac")]
49pub mod dmac;
50#[cfg(feature = "dw0")]
51pub mod dw;
52#[cfg(feature = "efuse")]
53pub mod efuse;
54#[cfg(feature = "fault")]
55pub mod fault;
56#[cfg(feature = "flashc")]
57pub mod flashc;
58#[cfg(feature = "gpio")]
59pub mod gpio;
60#[cfg(feature = "hsiom")]
61pub mod hsiom;
62#[cfg(feature = "i2s0")]
63pub mod i2s;
64#[cfg(feature = "ipc")]
65pub mod ipc;
66#[cfg(feature = "lcd0")]
67pub mod lcd;
68#[cfg(feature = "lpcomp")]
69pub mod lpcomp;
70#[cfg(feature = "pass")]
71pub mod pass;
72#[cfg(feature = "pdm0")]
73pub mod pdm;
74#[cfg(feature = "peri")]
75pub mod peri;
76#[cfg(feature = "peri_ms")]
77pub mod peri_ms;
78#[cfg(feature = "profile")]
79pub mod profile;
80#[cfg(feature = "prot")]
81pub mod prot;
82#[cfg(feature = "sar")]
83pub mod sar;
84#[cfg(feature = "scb0")]
85pub mod scb;
86#[cfg(feature = "sdhc0")]
87pub mod sdhc;
88#[cfg(feature = "smartio")]
89pub mod smartio;
90#[cfg(feature = "smif0")]
91pub mod smif;
92#[cfg(feature = "srss")]
93pub mod srss;
94#[cfg(feature = "tcpwm0")]
95pub mod tcpwm;
96#[cfg(feature = "usbfs0")]
97pub mod usbfs;
98
99#[cfg(feature = "peri")]
100#[derive(Copy, Clone, Eq, PartialEq)]
101pub struct Peri {
102    ptr: *mut u8,
103}
104#[cfg(feature = "peri")]
105pub const PERI: self::Peri = self::Peri {
106    ptr: 0x40000000u32 as _,
107};
108#[cfg(feature = "peri_ms")]
109#[derive(Copy, Clone, Eq, PartialEq)]
110pub struct PeriMs {
111    ptr: *mut u8,
112}
113#[cfg(feature = "peri_ms")]
114pub const PERI_MS: self::PeriMs = self::PeriMs {
115    ptr: 0x40010000u32 as _,
116};
117#[cfg(feature = "crypto")]
118#[derive(Copy, Clone, Eq, PartialEq)]
119pub struct Crypto {
120    ptr: *mut u8,
121}
122#[cfg(feature = "crypto")]
123pub const CRYPTO: self::Crypto = self::Crypto {
124    ptr: 0x40100000u32 as _,
125};
126#[cfg(feature = "cpuss")]
127#[derive(Copy, Clone, Eq, PartialEq)]
128pub struct Cpuss {
129    ptr: *mut u8,
130}
131#[cfg(feature = "cpuss")]
132pub const CPUSS: self::Cpuss = self::Cpuss {
133    ptr: 0x40200000u32 as _,
134};
135#[cfg(feature = "fault")]
136#[derive(Copy, Clone, Eq, PartialEq)]
137pub struct Fault {
138    ptr: *mut u8,
139}
140#[cfg(feature = "fault")]
141pub const FAULT: self::Fault = self::Fault {
142    ptr: 0x40210000u32 as _,
143};
144#[cfg(feature = "ipc")]
145#[derive(Copy, Clone, Eq, PartialEq)]
146pub struct Ipc {
147    ptr: *mut u8,
148}
149#[cfg(feature = "ipc")]
150pub const IPC: self::Ipc = self::Ipc {
151    ptr: 0x40220000u32 as _,
152};
153#[cfg(feature = "prot")]
154#[derive(Copy, Clone, Eq, PartialEq)]
155pub struct Prot {
156    ptr: *mut u8,
157}
158#[cfg(feature = "prot")]
159pub const PROT: self::Prot = self::Prot {
160    ptr: 0x40230000u32 as _,
161};
162#[cfg(feature = "flashc")]
163#[derive(Copy, Clone, Eq, PartialEq)]
164pub struct Flashc {
165    ptr: *mut u8,
166}
167#[cfg(feature = "flashc")]
168pub const FLASHC: self::Flashc = self::Flashc {
169    ptr: 0x40240000u32 as _,
170};
171#[cfg(feature = "srss")]
172#[derive(Copy, Clone, Eq, PartialEq)]
173pub struct Srss {
174    ptr: *mut u8,
175}
176#[cfg(feature = "srss")]
177pub const SRSS: self::Srss = self::Srss {
178    ptr: 0x40260000u32 as _,
179};
180#[cfg(feature = "backup")]
181#[derive(Copy, Clone, Eq, PartialEq)]
182pub struct Backup {
183    ptr: *mut u8,
184}
185#[cfg(feature = "backup")]
186pub const BACKUP: self::Backup = self::Backup {
187    ptr: 0x40270000u32 as _,
188};
189#[cfg(feature = "dw0")]
190#[derive(Copy, Clone, Eq, PartialEq)]
191pub struct Dw {
192    ptr: *mut u8,
193}
194#[cfg(feature = "dw0")]
195pub const DW0: self::Dw = self::Dw {
196    ptr: 0x40280000u32 as _,
197};
198#[cfg(feature = "dw1")]
199pub const DW1: self::Dw = self::Dw {
200    ptr: 0x40290000u32 as _,
201};
202#[cfg(feature = "dmac")]
203#[derive(Copy, Clone, Eq, PartialEq)]
204pub struct Dmac {
205    ptr: *mut u8,
206}
207#[cfg(feature = "dmac")]
208pub const DMAC: self::Dmac = self::Dmac {
209    ptr: 0x402a0000u32 as _,
210};
211#[cfg(feature = "efuse")]
212#[derive(Copy, Clone, Eq, PartialEq)]
213pub struct Efuse {
214    ptr: *mut u8,
215}
216#[cfg(feature = "efuse")]
217pub const EFUSE: self::Efuse = self::Efuse {
218    ptr: 0x402c0000u32 as _,
219};
220#[cfg(feature = "profile")]
221#[derive(Copy, Clone, Eq, PartialEq)]
222pub struct Profile {
223    ptr: *mut u8,
224}
225#[cfg(feature = "profile")]
226pub const PROFILE: self::Profile = self::Profile {
227    ptr: 0x402d0000u32 as _,
228};
229#[cfg(feature = "hsiom")]
230#[derive(Copy, Clone, Eq, PartialEq)]
231pub struct Hsiom {
232    ptr: *mut u8,
233}
234#[cfg(feature = "hsiom")]
235pub const HSIOM: self::Hsiom = self::Hsiom {
236    ptr: 0x40300000u32 as _,
237};
238#[cfg(feature = "gpio")]
239#[derive(Copy, Clone, Eq, PartialEq)]
240pub struct Gpio {
241    ptr: *mut u8,
242}
243#[cfg(feature = "gpio")]
244pub const GPIO: self::Gpio = self::Gpio {
245    ptr: 0x40310000u32 as _,
246};
247#[cfg(feature = "smartio")]
248#[derive(Copy, Clone, Eq, PartialEq)]
249pub struct Smartio {
250    ptr: *mut u8,
251}
252#[cfg(feature = "smartio")]
253pub const SMARTIO: self::Smartio = self::Smartio {
254    ptr: 0x40320000u32 as _,
255};
256#[cfg(feature = "lpcomp")]
257#[derive(Copy, Clone, Eq, PartialEq)]
258pub struct Lpcomp {
259    ptr: *mut u8,
260}
261#[cfg(feature = "lpcomp")]
262pub const LPCOMP: self::Lpcomp = self::Lpcomp {
263    ptr: 0x40350000u32 as _,
264};
265#[cfg(feature = "csd0")]
266#[derive(Copy, Clone, Eq, PartialEq)]
267pub struct Csd {
268    ptr: *mut u8,
269}
270#[cfg(feature = "csd0")]
271pub const CSD0: self::Csd = self::Csd {
272    ptr: 0x40360000u32 as _,
273};
274#[cfg(feature = "tcpwm0")]
275#[derive(Copy, Clone, Eq, PartialEq)]
276pub struct Tcpwm {
277    ptr: *mut u8,
278}
279#[cfg(feature = "tcpwm0")]
280pub const TCPWM0: self::Tcpwm = self::Tcpwm {
281    ptr: 0x40380000u32 as _,
282};
283#[cfg(feature = "tcpwm1")]
284pub const TCPWM1: self::Tcpwm = self::Tcpwm {
285    ptr: 0x40390000u32 as _,
286};
287#[cfg(feature = "lcd0")]
288#[derive(Copy, Clone, Eq, PartialEq)]
289pub struct Lcd {
290    ptr: *mut u8,
291}
292#[cfg(feature = "lcd0")]
293pub const LCD0: self::Lcd = self::Lcd {
294    ptr: 0x403b0000u32 as _,
295};
296#[cfg(feature = "usbfs0")]
297#[derive(Copy, Clone, Eq, PartialEq)]
298pub struct Usbfs {
299    ptr: *mut u8,
300}
301#[cfg(feature = "usbfs0")]
302pub const USBFS0: self::Usbfs = self::Usbfs {
303    ptr: 0x403f0000u32 as _,
304};
305#[cfg(feature = "smif0")]
306#[derive(Copy, Clone, Eq, PartialEq)]
307pub struct Smif {
308    ptr: *mut u8,
309}
310#[cfg(feature = "smif0")]
311pub const SMIF0: self::Smif = self::Smif {
312    ptr: 0x40420000u32 as _,
313};
314#[cfg(feature = "sdhc0")]
315#[derive(Copy, Clone, Eq, PartialEq)]
316pub struct Sdhc {
317    ptr: *mut u8,
318}
319#[cfg(feature = "sdhc0")]
320pub const SDHC0: self::Sdhc = self::Sdhc {
321    ptr: 0x40460000u32 as _,
322};
323#[cfg(feature = "sdhc1")]
324pub const SDHC1: self::Sdhc = self::Sdhc {
325    ptr: 0x40470000u32 as _,
326};
327#[cfg(feature = "scb0")]
328#[derive(Copy, Clone, Eq, PartialEq)]
329pub struct Scb {
330    ptr: *mut u8,
331}
332#[cfg(feature = "scb0")]
333pub const SCB0: self::Scb = self::Scb {
334    ptr: 0x40600000u32 as _,
335};
336#[cfg(feature = "scb1")]
337pub const SCB1: self::Scb = self::Scb {
338    ptr: 0x40610000u32 as _,
339};
340#[cfg(feature = "scb2")]
341pub const SCB2: self::Scb = self::Scb {
342    ptr: 0x40620000u32 as _,
343};
344#[cfg(feature = "scb3")]
345pub const SCB3: self::Scb = self::Scb {
346    ptr: 0x40630000u32 as _,
347};
348#[cfg(feature = "scb4")]
349pub const SCB4: self::Scb = self::Scb {
350    ptr: 0x40640000u32 as _,
351};
352#[cfg(feature = "scb5")]
353pub const SCB5: self::Scb = self::Scb {
354    ptr: 0x40650000u32 as _,
355};
356#[cfg(feature = "scb6")]
357pub const SCB6: self::Scb = self::Scb {
358    ptr: 0x40660000u32 as _,
359};
360#[cfg(feature = "scb7")]
361pub const SCB7: self::Scb = self::Scb {
362    ptr: 0x40670000u32 as _,
363};
364#[cfg(feature = "scb8")]
365pub const SCB8: self::Scb = self::Scb {
366    ptr: 0x40680000u32 as _,
367};
368#[cfg(feature = "scb9")]
369pub const SCB9: self::Scb = self::Scb {
370    ptr: 0x40690000u32 as _,
371};
372#[cfg(feature = "scb10")]
373pub const SCB10: self::Scb = self::Scb {
374    ptr: 0x406a0000u32 as _,
375};
376#[cfg(feature = "scb11")]
377pub const SCB11: self::Scb = self::Scb {
378    ptr: 0x406b0000u32 as _,
379};
380#[cfg(feature = "scb12")]
381pub const SCB12: self::Scb = self::Scb {
382    ptr: 0x406c0000u32 as _,
383};
384#[cfg(feature = "sar")]
385#[derive(Copy, Clone, Eq, PartialEq)]
386pub struct Sar {
387    ptr: *mut u8,
388}
389#[cfg(feature = "sar")]
390pub const SAR: self::Sar = self::Sar {
391    ptr: 0x409d0000u32 as _,
392};
393#[cfg(feature = "pass")]
394#[derive(Copy, Clone, Eq, PartialEq)]
395pub struct Pass {
396    ptr: *mut u8,
397}
398#[cfg(feature = "pass")]
399pub const PASS: self::Pass = self::Pass {
400    ptr: 0x409f0000u32 as _,
401};
402#[cfg(feature = "pdm0")]
403#[derive(Copy, Clone, Eq, PartialEq)]
404pub struct Pdm {
405    ptr: *mut u8,
406}
407#[cfg(feature = "pdm0")]
408pub const PDM0: self::Pdm = self::Pdm {
409    ptr: 0x40a00000u32 as _,
410};
411#[cfg(feature = "i2s0")]
412#[derive(Copy, Clone, Eq, PartialEq)]
413pub struct I2S {
414    ptr: *mut u8,
415}
416#[cfg(feature = "i2s0")]
417pub const I2S0: self::I2S = self::I2S {
418    ptr: 0x40a10000u32 as _,
419};
420#[cfg(feature = "i2s1")]
421pub const I2S1: self::I2S = self::I2S {
422    ptr: 0x40a11000u32 as _,
423};
424
425pub use cortex_m::peripheral::Peripherals as CorePeripherals;
426pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
427#[doc = "Number available in the NVIC for configuring priority"]
428pub const NVIC_PRIO_BITS: u8 = 3;
429#[doc(hidden)]
430pub union Vector {
431    _handler: unsafe extern "C" fn(),
432    _reserved: u32,
433}
434#[cfg(feature = "rt")]
435pub use self::Interrupt as interrupt;
436#[cfg(feature = "rt")]
437pub use cortex_m_rt::interrupt;
438#[cfg(feature = "rt")]
439pub mod interrupt_handlers {
440    extern "C" {
441        pub fn IOSS_INTERRUPTS_GPIO_0();
442        pub fn IOSS_INTERRUPTS_GPIO_1();
443        pub fn IOSS_INTERRUPTS_GPIO_2();
444        pub fn IOSS_INTERRUPTS_GPIO_3();
445        pub fn IOSS_INTERRUPTS_GPIO_4();
446        pub fn IOSS_INTERRUPTS_GPIO_5();
447        pub fn IOSS_INTERRUPTS_GPIO_6();
448        pub fn IOSS_INTERRUPTS_GPIO_7();
449        pub fn IOSS_INTERRUPTS_GPIO_8();
450        pub fn IOSS_INTERRUPTS_GPIO_9();
451        pub fn IOSS_INTERRUPTS_GPIO_10();
452        pub fn IOSS_INTERRUPTS_GPIO_11();
453        pub fn IOSS_INTERRUPTS_GPIO_12();
454        pub fn IOSS_INTERRUPTS_GPIO_13();
455        pub fn IOSS_INTERRUPTS_GPIO_14();
456        pub fn IOSS_INTERRUPT_GPIO();
457        pub fn IOSS_INTERRUPT_VDD();
458        pub fn LPCOMP_INTERRUPT();
459        pub fn SCB_8_INTERRUPT();
460        pub fn SRSS_INTERRUPT_MCWDT_0();
461        pub fn SRSS_INTERRUPT_MCWDT_1();
462        pub fn SRSS_INTERRUPT_BACKUP();
463        pub fn SRSS_INTERRUPT();
464        pub fn CPUSS_INTERRUPTS_IPC_0();
465        pub fn CPUSS_INTERRUPTS_IPC_1();
466        pub fn CPUSS_INTERRUPTS_IPC_2();
467        pub fn CPUSS_INTERRUPTS_IPC_3();
468        pub fn CPUSS_INTERRUPTS_IPC_4();
469        pub fn CPUSS_INTERRUPTS_IPC_5();
470        pub fn CPUSS_INTERRUPTS_IPC_6();
471        pub fn CPUSS_INTERRUPTS_IPC_7();
472        pub fn CPUSS_INTERRUPTS_IPC_8();
473        pub fn CPUSS_INTERRUPTS_IPC_9();
474        pub fn CPUSS_INTERRUPTS_IPC_10();
475        pub fn CPUSS_INTERRUPTS_IPC_11();
476        pub fn CPUSS_INTERRUPTS_IPC_12();
477        pub fn CPUSS_INTERRUPTS_IPC_13();
478        pub fn CPUSS_INTERRUPTS_IPC_14();
479        pub fn CPUSS_INTERRUPTS_IPC_15();
480        pub fn SCB_0_INTERRUPT();
481        pub fn SCB_1_INTERRUPT();
482        pub fn SCB_2_INTERRUPT();
483        pub fn SCB_3_INTERRUPT();
484        pub fn SCB_4_INTERRUPT();
485        pub fn SCB_5_INTERRUPT();
486        pub fn SCB_6_INTERRUPT();
487        pub fn SCB_7_INTERRUPT();
488        pub fn SCB_9_INTERRUPT();
489        pub fn SCB_10_INTERRUPT();
490        pub fn SCB_11_INTERRUPT();
491        pub fn SCB_12_INTERRUPT();
492        pub fn CSD_INTERRUPT();
493        pub fn CPUSS_INTERRUPTS_DMAC_0();
494        pub fn CPUSS_INTERRUPTS_DMAC_1();
495        pub fn CPUSS_INTERRUPTS_DMAC_2();
496        pub fn CPUSS_INTERRUPTS_DMAC_3();
497        pub fn CPUSS_INTERRUPTS_DW0_0();
498        pub fn CPUSS_INTERRUPTS_DW0_1();
499        pub fn CPUSS_INTERRUPTS_DW0_2();
500        pub fn CPUSS_INTERRUPTS_DW0_3();
501        pub fn CPUSS_INTERRUPTS_DW0_4();
502        pub fn CPUSS_INTERRUPTS_DW0_5();
503        pub fn CPUSS_INTERRUPTS_DW0_6();
504        pub fn CPUSS_INTERRUPTS_DW0_7();
505        pub fn CPUSS_INTERRUPTS_DW0_8();
506        pub fn CPUSS_INTERRUPTS_DW0_9();
507        pub fn CPUSS_INTERRUPTS_DW0_10();
508        pub fn CPUSS_INTERRUPTS_DW0_11();
509        pub fn CPUSS_INTERRUPTS_DW0_12();
510        pub fn CPUSS_INTERRUPTS_DW0_13();
511        pub fn CPUSS_INTERRUPTS_DW0_14();
512        pub fn CPUSS_INTERRUPTS_DW0_15();
513        pub fn CPUSS_INTERRUPTS_DW0_16();
514        pub fn CPUSS_INTERRUPTS_DW0_17();
515        pub fn CPUSS_INTERRUPTS_DW0_18();
516        pub fn CPUSS_INTERRUPTS_DW0_19();
517        pub fn CPUSS_INTERRUPTS_DW0_20();
518        pub fn CPUSS_INTERRUPTS_DW0_21();
519        pub fn CPUSS_INTERRUPTS_DW0_22();
520        pub fn CPUSS_INTERRUPTS_DW0_23();
521        pub fn CPUSS_INTERRUPTS_DW0_24();
522        pub fn CPUSS_INTERRUPTS_DW0_25();
523        pub fn CPUSS_INTERRUPTS_DW0_26();
524        pub fn CPUSS_INTERRUPTS_DW0_27();
525        pub fn CPUSS_INTERRUPTS_DW0_28();
526        pub fn CPUSS_INTERRUPTS_DW1_0();
527        pub fn CPUSS_INTERRUPTS_DW1_1();
528        pub fn CPUSS_INTERRUPTS_DW1_2();
529        pub fn CPUSS_INTERRUPTS_DW1_3();
530        pub fn CPUSS_INTERRUPTS_DW1_4();
531        pub fn CPUSS_INTERRUPTS_DW1_5();
532        pub fn CPUSS_INTERRUPTS_DW1_6();
533        pub fn CPUSS_INTERRUPTS_DW1_7();
534        pub fn CPUSS_INTERRUPTS_DW1_8();
535        pub fn CPUSS_INTERRUPTS_DW1_9();
536        pub fn CPUSS_INTERRUPTS_DW1_10();
537        pub fn CPUSS_INTERRUPTS_DW1_11();
538        pub fn CPUSS_INTERRUPTS_DW1_12();
539        pub fn CPUSS_INTERRUPTS_DW1_13();
540        pub fn CPUSS_INTERRUPTS_DW1_14();
541        pub fn CPUSS_INTERRUPTS_DW1_15();
542        pub fn CPUSS_INTERRUPTS_DW1_16();
543        pub fn CPUSS_INTERRUPTS_DW1_17();
544        pub fn CPUSS_INTERRUPTS_DW1_18();
545        pub fn CPUSS_INTERRUPTS_DW1_19();
546        pub fn CPUSS_INTERRUPTS_DW1_20();
547        pub fn CPUSS_INTERRUPTS_DW1_21();
548        pub fn CPUSS_INTERRUPTS_DW1_22();
549        pub fn CPUSS_INTERRUPTS_DW1_23();
550        pub fn CPUSS_INTERRUPTS_DW1_24();
551        pub fn CPUSS_INTERRUPTS_DW1_25();
552        pub fn CPUSS_INTERRUPTS_DW1_26();
553        pub fn CPUSS_INTERRUPTS_DW1_27();
554        pub fn CPUSS_INTERRUPTS_DW1_28();
555        pub fn CPUSS_INTERRUPTS_FAULT_0();
556        pub fn CPUSS_INTERRUPTS_FAULT_1();
557        pub fn CPUSS_INTERRUPT_CRYPTO();
558        pub fn CPUSS_INTERRUPT_FM();
559        pub fn CPUSS_INTERRUPTS_CM4_FP();
560        pub fn CPUSS_INTERRUPTS_CM0_CTI_0();
561        pub fn CPUSS_INTERRUPTS_CM0_CTI_1();
562        pub fn CPUSS_INTERRUPTS_CM4_CTI_0();
563        pub fn CPUSS_INTERRUPTS_CM4_CTI_1();
564        pub fn TCPWM_0_INTERRUPTS_0();
565        pub fn TCPWM_0_INTERRUPTS_1();
566        pub fn TCPWM_0_INTERRUPTS_2();
567        pub fn TCPWM_0_INTERRUPTS_3();
568        pub fn TCPWM_0_INTERRUPTS_4();
569        pub fn TCPWM_0_INTERRUPTS_5();
570        pub fn TCPWM_0_INTERRUPTS_6();
571        pub fn TCPWM_0_INTERRUPTS_7();
572        pub fn TCPWM_1_INTERRUPTS_0();
573        pub fn TCPWM_1_INTERRUPTS_1();
574        pub fn TCPWM_1_INTERRUPTS_2();
575        pub fn TCPWM_1_INTERRUPTS_3();
576        pub fn TCPWM_1_INTERRUPTS_4();
577        pub fn TCPWM_1_INTERRUPTS_5();
578        pub fn TCPWM_1_INTERRUPTS_6();
579        pub fn TCPWM_1_INTERRUPTS_7();
580        pub fn TCPWM_1_INTERRUPTS_8();
581        pub fn TCPWM_1_INTERRUPTS_9();
582        pub fn TCPWM_1_INTERRUPTS_10();
583        pub fn TCPWM_1_INTERRUPTS_11();
584        pub fn TCPWM_1_INTERRUPTS_12();
585        pub fn TCPWM_1_INTERRUPTS_13();
586        pub fn TCPWM_1_INTERRUPTS_14();
587        pub fn TCPWM_1_INTERRUPTS_15();
588        pub fn TCPWM_1_INTERRUPTS_16();
589        pub fn TCPWM_1_INTERRUPTS_17();
590        pub fn TCPWM_1_INTERRUPTS_18();
591        pub fn TCPWM_1_INTERRUPTS_19();
592        pub fn TCPWM_1_INTERRUPTS_20();
593        pub fn TCPWM_1_INTERRUPTS_21();
594        pub fn TCPWM_1_INTERRUPTS_22();
595        pub fn TCPWM_1_INTERRUPTS_23();
596        pub fn PASS_INTERRUPT_SAR();
597        pub fn AUDIOSS_0_INTERRUPT_I2S();
598        pub fn AUDIOSS_0_INTERRUPT_PDM();
599        pub fn AUDIOSS_1_INTERRUPT_I2S();
600        pub fn PROFILE_INTERRUPT();
601        pub fn SMIF_INTERRUPT();
602        pub fn USB_INTERRUPT_HI();
603        pub fn USB_INTERRUPT_MED();
604        pub fn USB_INTERRUPT_LO();
605        pub fn SDHC_0_INTERRUPT_WAKEUP();
606        pub fn SDHC_0_INTERRUPT_GENERAL();
607        pub fn SDHC_1_INTERRUPT_WAKEUP();
608        pub fn SDHC_1_INTERRUPT_GENERAL();
609    }
610}
611#[cfg(feature = "rt")]
612#[doc(hidden)]
613#[link_section = ".vector_table.interrupts"]
614#[no_mangle]
615pub static __INTERRUPTS: [Vector; 168] = [
616    Vector {
617        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_0,
618    },
619    Vector {
620        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_1,
621    },
622    Vector {
623        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_2,
624    },
625    Vector {
626        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_3,
627    },
628    Vector {
629        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_4,
630    },
631    Vector {
632        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_5,
633    },
634    Vector {
635        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_6,
636    },
637    Vector {
638        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_7,
639    },
640    Vector {
641        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_8,
642    },
643    Vector {
644        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_9,
645    },
646    Vector {
647        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_10,
648    },
649    Vector {
650        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_11,
651    },
652    Vector {
653        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_12,
654    },
655    Vector {
656        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_13,
657    },
658    Vector {
659        _handler: interrupt_handlers::IOSS_INTERRUPTS_GPIO_14,
660    },
661    Vector {
662        _handler: interrupt_handlers::IOSS_INTERRUPT_GPIO,
663    },
664    Vector {
665        _handler: interrupt_handlers::IOSS_INTERRUPT_VDD,
666    },
667    Vector {
668        _handler: interrupt_handlers::LPCOMP_INTERRUPT,
669    },
670    Vector {
671        _handler: interrupt_handlers::SCB_8_INTERRUPT,
672    },
673    Vector {
674        _handler: interrupt_handlers::SRSS_INTERRUPT_MCWDT_0,
675    },
676    Vector {
677        _handler: interrupt_handlers::SRSS_INTERRUPT_MCWDT_1,
678    },
679    Vector {
680        _handler: interrupt_handlers::SRSS_INTERRUPT_BACKUP,
681    },
682    Vector {
683        _handler: interrupt_handlers::SRSS_INTERRUPT,
684    },
685    Vector {
686        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_0,
687    },
688    Vector {
689        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_1,
690    },
691    Vector {
692        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_2,
693    },
694    Vector {
695        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_3,
696    },
697    Vector {
698        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_4,
699    },
700    Vector {
701        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_5,
702    },
703    Vector {
704        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_6,
705    },
706    Vector {
707        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_7,
708    },
709    Vector {
710        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_8,
711    },
712    Vector {
713        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_9,
714    },
715    Vector {
716        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_10,
717    },
718    Vector {
719        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_11,
720    },
721    Vector {
722        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_12,
723    },
724    Vector {
725        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_13,
726    },
727    Vector {
728        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_14,
729    },
730    Vector {
731        _handler: interrupt_handlers::CPUSS_INTERRUPTS_IPC_15,
732    },
733    Vector {
734        _handler: interrupt_handlers::SCB_0_INTERRUPT,
735    },
736    Vector {
737        _handler: interrupt_handlers::SCB_1_INTERRUPT,
738    },
739    Vector {
740        _handler: interrupt_handlers::SCB_2_INTERRUPT,
741    },
742    Vector {
743        _handler: interrupt_handlers::SCB_3_INTERRUPT,
744    },
745    Vector {
746        _handler: interrupt_handlers::SCB_4_INTERRUPT,
747    },
748    Vector {
749        _handler: interrupt_handlers::SCB_5_INTERRUPT,
750    },
751    Vector {
752        _handler: interrupt_handlers::SCB_6_INTERRUPT,
753    },
754    Vector {
755        _handler: interrupt_handlers::SCB_7_INTERRUPT,
756    },
757    Vector {
758        _handler: interrupt_handlers::SCB_9_INTERRUPT,
759    },
760    Vector {
761        _handler: interrupt_handlers::SCB_10_INTERRUPT,
762    },
763    Vector {
764        _handler: interrupt_handlers::SCB_11_INTERRUPT,
765    },
766    Vector {
767        _handler: interrupt_handlers::SCB_12_INTERRUPT,
768    },
769    Vector {
770        _handler: interrupt_handlers::CSD_INTERRUPT,
771    },
772    Vector {
773        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DMAC_0,
774    },
775    Vector {
776        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DMAC_1,
777    },
778    Vector {
779        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DMAC_2,
780    },
781    Vector {
782        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DMAC_3,
783    },
784    Vector {
785        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_0,
786    },
787    Vector {
788        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_1,
789    },
790    Vector {
791        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_2,
792    },
793    Vector {
794        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_3,
795    },
796    Vector {
797        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_4,
798    },
799    Vector {
800        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_5,
801    },
802    Vector {
803        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_6,
804    },
805    Vector {
806        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_7,
807    },
808    Vector {
809        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_8,
810    },
811    Vector {
812        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_9,
813    },
814    Vector {
815        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_10,
816    },
817    Vector {
818        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_11,
819    },
820    Vector {
821        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_12,
822    },
823    Vector {
824        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_13,
825    },
826    Vector {
827        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_14,
828    },
829    Vector {
830        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_15,
831    },
832    Vector {
833        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_16,
834    },
835    Vector {
836        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_17,
837    },
838    Vector {
839        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_18,
840    },
841    Vector {
842        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_19,
843    },
844    Vector {
845        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_20,
846    },
847    Vector {
848        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_21,
849    },
850    Vector {
851        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_22,
852    },
853    Vector {
854        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_23,
855    },
856    Vector {
857        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_24,
858    },
859    Vector {
860        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_25,
861    },
862    Vector {
863        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_26,
864    },
865    Vector {
866        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_27,
867    },
868    Vector {
869        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW0_28,
870    },
871    Vector {
872        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_0,
873    },
874    Vector {
875        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_1,
876    },
877    Vector {
878        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_2,
879    },
880    Vector {
881        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_3,
882    },
883    Vector {
884        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_4,
885    },
886    Vector {
887        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_5,
888    },
889    Vector {
890        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_6,
891    },
892    Vector {
893        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_7,
894    },
895    Vector {
896        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_8,
897    },
898    Vector {
899        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_9,
900    },
901    Vector {
902        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_10,
903    },
904    Vector {
905        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_11,
906    },
907    Vector {
908        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_12,
909    },
910    Vector {
911        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_13,
912    },
913    Vector {
914        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_14,
915    },
916    Vector {
917        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_15,
918    },
919    Vector {
920        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_16,
921    },
922    Vector {
923        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_17,
924    },
925    Vector {
926        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_18,
927    },
928    Vector {
929        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_19,
930    },
931    Vector {
932        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_20,
933    },
934    Vector {
935        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_21,
936    },
937    Vector {
938        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_22,
939    },
940    Vector {
941        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_23,
942    },
943    Vector {
944        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_24,
945    },
946    Vector {
947        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_25,
948    },
949    Vector {
950        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_26,
951    },
952    Vector {
953        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_27,
954    },
955    Vector {
956        _handler: interrupt_handlers::CPUSS_INTERRUPTS_DW1_28,
957    },
958    Vector {
959        _handler: interrupt_handlers::CPUSS_INTERRUPTS_FAULT_0,
960    },
961    Vector {
962        _handler: interrupt_handlers::CPUSS_INTERRUPTS_FAULT_1,
963    },
964    Vector {
965        _handler: interrupt_handlers::CPUSS_INTERRUPT_CRYPTO,
966    },
967    Vector {
968        _handler: interrupt_handlers::CPUSS_INTERRUPT_FM,
969    },
970    Vector {
971        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM4_FP,
972    },
973    Vector {
974        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM0_CTI_0,
975    },
976    Vector {
977        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM0_CTI_1,
978    },
979    Vector {
980        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM4_CTI_0,
981    },
982    Vector {
983        _handler: interrupt_handlers::CPUSS_INTERRUPTS_CM4_CTI_1,
984    },
985    Vector {
986        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_0,
987    },
988    Vector {
989        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_1,
990    },
991    Vector {
992        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_2,
993    },
994    Vector {
995        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_3,
996    },
997    Vector {
998        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_4,
999    },
1000    Vector {
1001        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_5,
1002    },
1003    Vector {
1004        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_6,
1005    },
1006    Vector {
1007        _handler: interrupt_handlers::TCPWM_0_INTERRUPTS_7,
1008    },
1009    Vector {
1010        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_0,
1011    },
1012    Vector {
1013        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_1,
1014    },
1015    Vector {
1016        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_2,
1017    },
1018    Vector {
1019        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_3,
1020    },
1021    Vector {
1022        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_4,
1023    },
1024    Vector {
1025        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_5,
1026    },
1027    Vector {
1028        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_6,
1029    },
1030    Vector {
1031        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_7,
1032    },
1033    Vector {
1034        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_8,
1035    },
1036    Vector {
1037        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_9,
1038    },
1039    Vector {
1040        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_10,
1041    },
1042    Vector {
1043        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_11,
1044    },
1045    Vector {
1046        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_12,
1047    },
1048    Vector {
1049        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_13,
1050    },
1051    Vector {
1052        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_14,
1053    },
1054    Vector {
1055        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_15,
1056    },
1057    Vector {
1058        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_16,
1059    },
1060    Vector {
1061        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_17,
1062    },
1063    Vector {
1064        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_18,
1065    },
1066    Vector {
1067        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_19,
1068    },
1069    Vector {
1070        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_20,
1071    },
1072    Vector {
1073        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_21,
1074    },
1075    Vector {
1076        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_22,
1077    },
1078    Vector {
1079        _handler: interrupt_handlers::TCPWM_1_INTERRUPTS_23,
1080    },
1081    Vector {
1082        _handler: interrupt_handlers::PASS_INTERRUPT_SAR,
1083    },
1084    Vector {
1085        _handler: interrupt_handlers::AUDIOSS_0_INTERRUPT_I2S,
1086    },
1087    Vector {
1088        _handler: interrupt_handlers::AUDIOSS_0_INTERRUPT_PDM,
1089    },
1090    Vector {
1091        _handler: interrupt_handlers::AUDIOSS_1_INTERRUPT_I2S,
1092    },
1093    Vector {
1094        _handler: interrupt_handlers::PROFILE_INTERRUPT,
1095    },
1096    Vector {
1097        _handler: interrupt_handlers::SMIF_INTERRUPT,
1098    },
1099    Vector {
1100        _handler: interrupt_handlers::USB_INTERRUPT_HI,
1101    },
1102    Vector {
1103        _handler: interrupt_handlers::USB_INTERRUPT_MED,
1104    },
1105    Vector {
1106        _handler: interrupt_handlers::USB_INTERRUPT_LO,
1107    },
1108    Vector {
1109        _handler: interrupt_handlers::SDHC_0_INTERRUPT_WAKEUP,
1110    },
1111    Vector {
1112        _handler: interrupt_handlers::SDHC_0_INTERRUPT_GENERAL,
1113    },
1114    Vector {
1115        _handler: interrupt_handlers::SDHC_1_INTERRUPT_WAKEUP,
1116    },
1117    Vector {
1118        _handler: interrupt_handlers::SDHC_1_INTERRUPT_GENERAL,
1119    },
1120];
1121#[doc = "Enumeration of all the interrupts."]
1122#[derive(Copy, Clone, Debug, PartialEq, Eq)]
1123#[repr(u16)]
1124pub enum Interrupt {
1125    #[doc = "GPIO Port Interrupt #0"]
1126    IOSS_INTERRUPTS_GPIO_0 = 0,
1127
1128    #[doc = "GPIO Port Interrupt #1"]
1129    IOSS_INTERRUPTS_GPIO_1 = 1,
1130
1131    #[doc = "GPIO Port Interrupt #2"]
1132    IOSS_INTERRUPTS_GPIO_2 = 2,
1133
1134    #[doc = "GPIO Port Interrupt #3"]
1135    IOSS_INTERRUPTS_GPIO_3 = 3,
1136
1137    #[doc = "GPIO Port Interrupt #4"]
1138    IOSS_INTERRUPTS_GPIO_4 = 4,
1139
1140    #[doc = "GPIO Port Interrupt #5"]
1141    IOSS_INTERRUPTS_GPIO_5 = 5,
1142
1143    #[doc = "GPIO Port Interrupt #6"]
1144    IOSS_INTERRUPTS_GPIO_6 = 6,
1145
1146    #[doc = "GPIO Port Interrupt #7"]
1147    IOSS_INTERRUPTS_GPIO_7 = 7,
1148
1149    #[doc = "GPIO Port Interrupt #8"]
1150    IOSS_INTERRUPTS_GPIO_8 = 8,
1151
1152    #[doc = "GPIO Port Interrupt #9"]
1153    IOSS_INTERRUPTS_GPIO_9 = 9,
1154
1155    #[doc = "GPIO Port Interrupt #10"]
1156    IOSS_INTERRUPTS_GPIO_10 = 10,
1157
1158    #[doc = "GPIO Port Interrupt #11"]
1159    IOSS_INTERRUPTS_GPIO_11 = 11,
1160
1161    #[doc = "GPIO Port Interrupt #12"]
1162    IOSS_INTERRUPTS_GPIO_12 = 12,
1163
1164    #[doc = "GPIO Port Interrupt #13"]
1165    IOSS_INTERRUPTS_GPIO_13 = 13,
1166
1167    #[doc = "GPIO Port Interrupt #14"]
1168    IOSS_INTERRUPTS_GPIO_14 = 14,
1169
1170    #[doc = "GPIO All Ports"]
1171    IOSS_INTERRUPT_GPIO = 15,
1172
1173    #[doc = "GPIO Supply Detect Interrupt"]
1174    IOSS_INTERRUPT_VDD = 16,
1175
1176    #[doc = "Low Power Comparator Interrupt"]
1177    LPCOMP_INTERRUPT = 17,
1178
1179    #[doc = "Serial Communication Block #8 (DeepSleep capable)"]
1180    SCB_8_INTERRUPT = 18,
1181
1182    #[doc = "Multi Counter Watchdog Timer interrupt"]
1183    SRSS_INTERRUPT_MCWDT_0 = 19,
1184
1185    #[doc = "Multi Counter Watchdog Timer interrupt"]
1186    SRSS_INTERRUPT_MCWDT_1 = 20,
1187
1188    #[doc = "Backup domain interrupt"]
1189    SRSS_INTERRUPT_BACKUP = 21,
1190
1191    #[doc = "Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)"]
1192    SRSS_INTERRUPT = 22,
1193
1194    #[doc = "CPUSS Inter Process Communication Interrupt #0"]
1195    CPUSS_INTERRUPTS_IPC_0 = 23,
1196
1197    #[doc = "CPUSS Inter Process Communication Interrupt #1"]
1198    CPUSS_INTERRUPTS_IPC_1 = 24,
1199
1200    #[doc = "CPUSS Inter Process Communication Interrupt #2"]
1201    CPUSS_INTERRUPTS_IPC_2 = 25,
1202
1203    #[doc = "CPUSS Inter Process Communication Interrupt #3"]
1204    CPUSS_INTERRUPTS_IPC_3 = 26,
1205
1206    #[doc = "CPUSS Inter Process Communication Interrupt #4"]
1207    CPUSS_INTERRUPTS_IPC_4 = 27,
1208
1209    #[doc = "CPUSS Inter Process Communication Interrupt #5"]
1210    CPUSS_INTERRUPTS_IPC_5 = 28,
1211
1212    #[doc = "CPUSS Inter Process Communication Interrupt #6"]
1213    CPUSS_INTERRUPTS_IPC_6 = 29,
1214
1215    #[doc = "CPUSS Inter Process Communication Interrupt #7"]
1216    CPUSS_INTERRUPTS_IPC_7 = 30,
1217
1218    #[doc = "CPUSS Inter Process Communication Interrupt #8"]
1219    CPUSS_INTERRUPTS_IPC_8 = 31,
1220
1221    #[doc = "CPUSS Inter Process Communication Interrupt #9"]
1222    CPUSS_INTERRUPTS_IPC_9 = 32,
1223
1224    #[doc = "CPUSS Inter Process Communication Interrupt #10"]
1225    CPUSS_INTERRUPTS_IPC_10 = 33,
1226
1227    #[doc = "CPUSS Inter Process Communication Interrupt #11"]
1228    CPUSS_INTERRUPTS_IPC_11 = 34,
1229
1230    #[doc = "CPUSS Inter Process Communication Interrupt #12"]
1231    CPUSS_INTERRUPTS_IPC_12 = 35,
1232
1233    #[doc = "CPUSS Inter Process Communication Interrupt #13"]
1234    CPUSS_INTERRUPTS_IPC_13 = 36,
1235
1236    #[doc = "CPUSS Inter Process Communication Interrupt #14"]
1237    CPUSS_INTERRUPTS_IPC_14 = 37,
1238
1239    #[doc = "CPUSS Inter Process Communication Interrupt #15"]
1240    CPUSS_INTERRUPTS_IPC_15 = 38,
1241
1242    #[doc = "Serial Communication Block #0"]
1243    SCB_0_INTERRUPT = 39,
1244
1245    #[doc = "Serial Communication Block #1"]
1246    SCB_1_INTERRUPT = 40,
1247
1248    #[doc = "Serial Communication Block #2"]
1249    SCB_2_INTERRUPT = 41,
1250
1251    #[doc = "Serial Communication Block #3"]
1252    SCB_3_INTERRUPT = 42,
1253
1254    #[doc = "Serial Communication Block #4"]
1255    SCB_4_INTERRUPT = 43,
1256
1257    #[doc = "Serial Communication Block #5"]
1258    SCB_5_INTERRUPT = 44,
1259
1260    #[doc = "Serial Communication Block #6"]
1261    SCB_6_INTERRUPT = 45,
1262
1263    #[doc = "Serial Communication Block #7"]
1264    SCB_7_INTERRUPT = 46,
1265
1266    #[doc = "Serial Communication Block #9"]
1267    SCB_9_INTERRUPT = 47,
1268
1269    #[doc = "Serial Communication Block #10"]
1270    SCB_10_INTERRUPT = 48,
1271
1272    #[doc = "Serial Communication Block #11"]
1273    SCB_11_INTERRUPT = 49,
1274
1275    #[doc = "Serial Communication Block #12"]
1276    SCB_12_INTERRUPT = 50,
1277
1278    #[doc = "CSD (Capsense) interrupt"]
1279    CSD_INTERRUPT = 51,
1280
1281    #[doc = "CPUSS DMAC, Channel #0"]
1282    CPUSS_INTERRUPTS_DMAC_0 = 52,
1283
1284    #[doc = "CPUSS DMAC, Channel #1"]
1285    CPUSS_INTERRUPTS_DMAC_1 = 53,
1286
1287    #[doc = "CPUSS DMAC, Channel #2"]
1288    CPUSS_INTERRUPTS_DMAC_2 = 54,
1289
1290    #[doc = "CPUSS DMAC, Channel #3"]
1291    CPUSS_INTERRUPTS_DMAC_3 = 55,
1292
1293    #[doc = "CPUSS DataWire #0, Channel #0"]
1294    CPUSS_INTERRUPTS_DW0_0 = 56,
1295
1296    #[doc = "CPUSS DataWire #0, Channel #1"]
1297    CPUSS_INTERRUPTS_DW0_1 = 57,
1298
1299    #[doc = "CPUSS DataWire #0, Channel #2"]
1300    CPUSS_INTERRUPTS_DW0_2 = 58,
1301
1302    #[doc = "CPUSS DataWire #0, Channel #3"]
1303    CPUSS_INTERRUPTS_DW0_3 = 59,
1304
1305    #[doc = "CPUSS DataWire #0, Channel #4"]
1306    CPUSS_INTERRUPTS_DW0_4 = 60,
1307
1308    #[doc = "CPUSS DataWire #0, Channel #5"]
1309    CPUSS_INTERRUPTS_DW0_5 = 61,
1310
1311    #[doc = "CPUSS DataWire #0, Channel #6"]
1312    CPUSS_INTERRUPTS_DW0_6 = 62,
1313
1314    #[doc = "CPUSS DataWire #0, Channel #7"]
1315    CPUSS_INTERRUPTS_DW0_7 = 63,
1316
1317    #[doc = "CPUSS DataWire #0, Channel #8"]
1318    CPUSS_INTERRUPTS_DW0_8 = 64,
1319
1320    #[doc = "CPUSS DataWire #0, Channel #9"]
1321    CPUSS_INTERRUPTS_DW0_9 = 65,
1322
1323    #[doc = "CPUSS DataWire #0, Channel #10"]
1324    CPUSS_INTERRUPTS_DW0_10 = 66,
1325
1326    #[doc = "CPUSS DataWire #0, Channel #11"]
1327    CPUSS_INTERRUPTS_DW0_11 = 67,
1328
1329    #[doc = "CPUSS DataWire #0, Channel #12"]
1330    CPUSS_INTERRUPTS_DW0_12 = 68,
1331
1332    #[doc = "CPUSS DataWire #0, Channel #13"]
1333    CPUSS_INTERRUPTS_DW0_13 = 69,
1334
1335    #[doc = "CPUSS DataWire #0, Channel #14"]
1336    CPUSS_INTERRUPTS_DW0_14 = 70,
1337
1338    #[doc = "CPUSS DataWire #0, Channel #15"]
1339    CPUSS_INTERRUPTS_DW0_15 = 71,
1340
1341    #[doc = "CPUSS DataWire #0, Channel #16"]
1342    CPUSS_INTERRUPTS_DW0_16 = 72,
1343
1344    #[doc = "CPUSS DataWire #0, Channel #17"]
1345    CPUSS_INTERRUPTS_DW0_17 = 73,
1346
1347    #[doc = "CPUSS DataWire #0, Channel #18"]
1348    CPUSS_INTERRUPTS_DW0_18 = 74,
1349
1350    #[doc = "CPUSS DataWire #0, Channel #19"]
1351    CPUSS_INTERRUPTS_DW0_19 = 75,
1352
1353    #[doc = "CPUSS DataWire #0, Channel #20"]
1354    CPUSS_INTERRUPTS_DW0_20 = 76,
1355
1356    #[doc = "CPUSS DataWire #0, Channel #21"]
1357    CPUSS_INTERRUPTS_DW0_21 = 77,
1358
1359    #[doc = "CPUSS DataWire #0, Channel #22"]
1360    CPUSS_INTERRUPTS_DW0_22 = 78,
1361
1362    #[doc = "CPUSS DataWire #0, Channel #23"]
1363    CPUSS_INTERRUPTS_DW0_23 = 79,
1364
1365    #[doc = "CPUSS DataWire #0, Channel #24"]
1366    CPUSS_INTERRUPTS_DW0_24 = 80,
1367
1368    #[doc = "CPUSS DataWire #0, Channel #25"]
1369    CPUSS_INTERRUPTS_DW0_25 = 81,
1370
1371    #[doc = "CPUSS DataWire #0, Channel #26"]
1372    CPUSS_INTERRUPTS_DW0_26 = 82,
1373
1374    #[doc = "CPUSS DataWire #0, Channel #27"]
1375    CPUSS_INTERRUPTS_DW0_27 = 83,
1376
1377    #[doc = "CPUSS DataWire #0, Channel #28"]
1378    CPUSS_INTERRUPTS_DW0_28 = 84,
1379
1380    #[doc = "CPUSS DataWire #1, Channel #0"]
1381    CPUSS_INTERRUPTS_DW1_0 = 85,
1382
1383    #[doc = "CPUSS DataWire #1, Channel #1"]
1384    CPUSS_INTERRUPTS_DW1_1 = 86,
1385
1386    #[doc = "CPUSS DataWire #1, Channel #2"]
1387    CPUSS_INTERRUPTS_DW1_2 = 87,
1388
1389    #[doc = "CPUSS DataWire #1, Channel #3"]
1390    CPUSS_INTERRUPTS_DW1_3 = 88,
1391
1392    #[doc = "CPUSS DataWire #1, Channel #4"]
1393    CPUSS_INTERRUPTS_DW1_4 = 89,
1394
1395    #[doc = "CPUSS DataWire #1, Channel #5"]
1396    CPUSS_INTERRUPTS_DW1_5 = 90,
1397
1398    #[doc = "CPUSS DataWire #1, Channel #6"]
1399    CPUSS_INTERRUPTS_DW1_6 = 91,
1400
1401    #[doc = "CPUSS DataWire #1, Channel #7"]
1402    CPUSS_INTERRUPTS_DW1_7 = 92,
1403
1404    #[doc = "CPUSS DataWire #1, Channel #8"]
1405    CPUSS_INTERRUPTS_DW1_8 = 93,
1406
1407    #[doc = "CPUSS DataWire #1, Channel #9"]
1408    CPUSS_INTERRUPTS_DW1_9 = 94,
1409
1410    #[doc = "CPUSS DataWire #1, Channel #10"]
1411    CPUSS_INTERRUPTS_DW1_10 = 95,
1412
1413    #[doc = "CPUSS DataWire #1, Channel #11"]
1414    CPUSS_INTERRUPTS_DW1_11 = 96,
1415
1416    #[doc = "CPUSS DataWire #1, Channel #12"]
1417    CPUSS_INTERRUPTS_DW1_12 = 97,
1418
1419    #[doc = "CPUSS DataWire #1, Channel #13"]
1420    CPUSS_INTERRUPTS_DW1_13 = 98,
1421
1422    #[doc = "CPUSS DataWire #1, Channel #14"]
1423    CPUSS_INTERRUPTS_DW1_14 = 99,
1424
1425    #[doc = "CPUSS DataWire #1, Channel #15"]
1426    CPUSS_INTERRUPTS_DW1_15 = 100,
1427
1428    #[doc = "CPUSS DataWire #1, Channel #16"]
1429    CPUSS_INTERRUPTS_DW1_16 = 101,
1430
1431    #[doc = "CPUSS DataWire #1, Channel #17"]
1432    CPUSS_INTERRUPTS_DW1_17 = 102,
1433
1434    #[doc = "CPUSS DataWire #1, Channel #18"]
1435    CPUSS_INTERRUPTS_DW1_18 = 103,
1436
1437    #[doc = "CPUSS DataWire #1, Channel #19"]
1438    CPUSS_INTERRUPTS_DW1_19 = 104,
1439
1440    #[doc = "CPUSS DataWire #1, Channel #20"]
1441    CPUSS_INTERRUPTS_DW1_20 = 105,
1442
1443    #[doc = "CPUSS DataWire #1, Channel #21"]
1444    CPUSS_INTERRUPTS_DW1_21 = 106,
1445
1446    #[doc = "CPUSS DataWire #1, Channel #22"]
1447    CPUSS_INTERRUPTS_DW1_22 = 107,
1448
1449    #[doc = "CPUSS DataWire #1, Channel #23"]
1450    CPUSS_INTERRUPTS_DW1_23 = 108,
1451
1452    #[doc = "CPUSS DataWire #1, Channel #24"]
1453    CPUSS_INTERRUPTS_DW1_24 = 109,
1454
1455    #[doc = "CPUSS DataWire #1, Channel #25"]
1456    CPUSS_INTERRUPTS_DW1_25 = 110,
1457
1458    #[doc = "CPUSS DataWire #1, Channel #26"]
1459    CPUSS_INTERRUPTS_DW1_26 = 111,
1460
1461    #[doc = "CPUSS DataWire #1, Channel #27"]
1462    CPUSS_INTERRUPTS_DW1_27 = 112,
1463
1464    #[doc = "CPUSS DataWire #1, Channel #28"]
1465    CPUSS_INTERRUPTS_DW1_28 = 113,
1466
1467    #[doc = "CPUSS Fault Structure Interrupt #0"]
1468    CPUSS_INTERRUPTS_FAULT_0 = 114,
1469
1470    #[doc = "CPUSS Fault Structure Interrupt #1"]
1471    CPUSS_INTERRUPTS_FAULT_1 = 115,
1472
1473    #[doc = "CRYPTO Accelerator Interrupt"]
1474    CPUSS_INTERRUPT_CRYPTO = 116,
1475
1476    #[doc = "FLASH Macro Interrupt"]
1477    CPUSS_INTERRUPT_FM = 117,
1478
1479    #[doc = "Floating Point operation fault"]
1480    CPUSS_INTERRUPTS_CM4_FP = 118,
1481
1482    #[doc = "CM0+ CTI #0"]
1483    CPUSS_INTERRUPTS_CM0_CTI_0 = 119,
1484
1485    #[doc = "CM0+ CTI #1"]
1486    CPUSS_INTERRUPTS_CM0_CTI_1 = 120,
1487
1488    #[doc = "CM4 CTI #0"]
1489    CPUSS_INTERRUPTS_CM4_CTI_0 = 121,
1490
1491    #[doc = "CM4 CTI #1"]
1492    CPUSS_INTERRUPTS_CM4_CTI_1 = 122,
1493
1494    #[doc = "TCPWM #0, Counter #0"]
1495    TCPWM_0_INTERRUPTS_0 = 123,
1496
1497    #[doc = "TCPWM #0, Counter #1"]
1498    TCPWM_0_INTERRUPTS_1 = 124,
1499
1500    #[doc = "TCPWM #0, Counter #2"]
1501    TCPWM_0_INTERRUPTS_2 = 125,
1502
1503    #[doc = "TCPWM #0, Counter #3"]
1504    TCPWM_0_INTERRUPTS_3 = 126,
1505
1506    #[doc = "TCPWM #0, Counter #4"]
1507    TCPWM_0_INTERRUPTS_4 = 127,
1508
1509    #[doc = "TCPWM #0, Counter #5"]
1510    TCPWM_0_INTERRUPTS_5 = 128,
1511
1512    #[doc = "TCPWM #0, Counter #6"]
1513    TCPWM_0_INTERRUPTS_6 = 129,
1514
1515    #[doc = "TCPWM #0, Counter #7"]
1516    TCPWM_0_INTERRUPTS_7 = 130,
1517
1518    #[doc = "TCPWM #1, Counter #0"]
1519    TCPWM_1_INTERRUPTS_0 = 131,
1520
1521    #[doc = "TCPWM #1, Counter #1"]
1522    TCPWM_1_INTERRUPTS_1 = 132,
1523
1524    #[doc = "TCPWM #1, Counter #2"]
1525    TCPWM_1_INTERRUPTS_2 = 133,
1526
1527    #[doc = "TCPWM #1, Counter #3"]
1528    TCPWM_1_INTERRUPTS_3 = 134,
1529
1530    #[doc = "TCPWM #1, Counter #4"]
1531    TCPWM_1_INTERRUPTS_4 = 135,
1532
1533    #[doc = "TCPWM #1, Counter #5"]
1534    TCPWM_1_INTERRUPTS_5 = 136,
1535
1536    #[doc = "TCPWM #1, Counter #6"]
1537    TCPWM_1_INTERRUPTS_6 = 137,
1538
1539    #[doc = "TCPWM #1, Counter #7"]
1540    TCPWM_1_INTERRUPTS_7 = 138,
1541
1542    #[doc = "TCPWM #1, Counter #8"]
1543    TCPWM_1_INTERRUPTS_8 = 139,
1544
1545    #[doc = "TCPWM #1, Counter #9"]
1546    TCPWM_1_INTERRUPTS_9 = 140,
1547
1548    #[doc = "TCPWM #1, Counter #10"]
1549    TCPWM_1_INTERRUPTS_10 = 141,
1550
1551    #[doc = "TCPWM #1, Counter #11"]
1552    TCPWM_1_INTERRUPTS_11 = 142,
1553
1554    #[doc = "TCPWM #1, Counter #12"]
1555    TCPWM_1_INTERRUPTS_12 = 143,
1556
1557    #[doc = "TCPWM #1, Counter #13"]
1558    TCPWM_1_INTERRUPTS_13 = 144,
1559
1560    #[doc = "TCPWM #1, Counter #14"]
1561    TCPWM_1_INTERRUPTS_14 = 145,
1562
1563    #[doc = "TCPWM #1, Counter #15"]
1564    TCPWM_1_INTERRUPTS_15 = 146,
1565
1566    #[doc = "TCPWM #1, Counter #16"]
1567    TCPWM_1_INTERRUPTS_16 = 147,
1568
1569    #[doc = "TCPWM #1, Counter #17"]
1570    TCPWM_1_INTERRUPTS_17 = 148,
1571
1572    #[doc = "TCPWM #1, Counter #18"]
1573    TCPWM_1_INTERRUPTS_18 = 149,
1574
1575    #[doc = "TCPWM #1, Counter #19"]
1576    TCPWM_1_INTERRUPTS_19 = 150,
1577
1578    #[doc = "TCPWM #1, Counter #20"]
1579    TCPWM_1_INTERRUPTS_20 = 151,
1580
1581    #[doc = "TCPWM #1, Counter #21"]
1582    TCPWM_1_INTERRUPTS_21 = 152,
1583
1584    #[doc = "TCPWM #1, Counter #22"]
1585    TCPWM_1_INTERRUPTS_22 = 153,
1586
1587    #[doc = "TCPWM #1, Counter #23"]
1588    TCPWM_1_INTERRUPTS_23 = 154,
1589
1590    #[doc = "SAR ADC interrupt"]
1591    PASS_INTERRUPT_SAR = 155,
1592
1593    #[doc = "I2S0 Audio interrupt"]
1594    AUDIOSS_0_INTERRUPT_I2S = 156,
1595
1596    #[doc = "PDM0/PCM0 Audio interrupt"]
1597    AUDIOSS_0_INTERRUPT_PDM = 157,
1598
1599    #[doc = "I2S1 Audio interrupt"]
1600    AUDIOSS_1_INTERRUPT_I2S = 158,
1601
1602    #[doc = "Energy Profiler interrupt"]
1603    PROFILE_INTERRUPT = 159,
1604
1605    #[doc = "Serial Memory Interface interrupt"]
1606    SMIF_INTERRUPT = 160,
1607
1608    #[doc = "USB Interrupt"]
1609    USB_INTERRUPT_HI = 161,
1610
1611    #[doc = "USB Interrupt"]
1612    USB_INTERRUPT_MED = 162,
1613
1614    #[doc = "USB Interrupt"]
1615    USB_INTERRUPT_LO = 163,
1616
1617    #[doc = "SDIO wakeup interrupt for mxsdhc"]
1618    SDHC_0_INTERRUPT_WAKEUP = 164,
1619
1620    #[doc = "Consolidated interrupt for mxsdhc for everything else"]
1621    SDHC_0_INTERRUPT_GENERAL = 165,
1622
1623    #[doc = "EEMC wakeup interrupt for mxsdhc, not used"]
1624    SDHC_1_INTERRUPT_WAKEUP = 166,
1625
1626    #[doc = "Consolidated interrupt for mxsdhc for everything else"]
1627    SDHC_1_INTERRUPT_GENERAL = 167,
1628}
1629unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
1630    #[inline(always)]
1631    fn number(self) -> u16 {
1632        self as u16
1633    }
1634}
1635#[allow(non_snake_case)]
1636/// Required for compatibility with RTIC and other frameworks
1637pub struct Peripherals {
1638    #[cfg(feature = "peri")]
1639    pub PERI: self::Peri,
1640    #[cfg(feature = "peri_ms")]
1641    pub PERI_MS: self::PeriMs,
1642    #[cfg(feature = "crypto")]
1643    pub CRYPTO: self::Crypto,
1644    #[cfg(feature = "cpuss")]
1645    pub CPUSS: self::Cpuss,
1646    #[cfg(feature = "fault")]
1647    pub FAULT: self::Fault,
1648    #[cfg(feature = "ipc")]
1649    pub IPC: self::Ipc,
1650    #[cfg(feature = "prot")]
1651    pub PROT: self::Prot,
1652    #[cfg(feature = "flashc")]
1653    pub FLASHC: self::Flashc,
1654    #[cfg(feature = "srss")]
1655    pub SRSS: self::Srss,
1656    #[cfg(feature = "backup")]
1657    pub BACKUP: self::Backup,
1658    #[cfg(feature = "dw0")]
1659    pub DW0: self::Dw,
1660    #[cfg(feature = "dw1")]
1661    pub DW1: self::Dw,
1662    #[cfg(feature = "dmac")]
1663    pub DMAC: self::Dmac,
1664    #[cfg(feature = "efuse")]
1665    pub EFUSE: self::Efuse,
1666    #[cfg(feature = "profile")]
1667    pub PROFILE: self::Profile,
1668    #[cfg(feature = "hsiom")]
1669    pub HSIOM: self::Hsiom,
1670    #[cfg(feature = "gpio")]
1671    pub GPIO: self::Gpio,
1672    #[cfg(feature = "smartio")]
1673    pub SMARTIO: self::Smartio,
1674    #[cfg(feature = "lpcomp")]
1675    pub LPCOMP: self::Lpcomp,
1676    #[cfg(feature = "csd0")]
1677    pub CSD0: self::Csd,
1678    #[cfg(feature = "tcpwm0")]
1679    pub TCPWM0: self::Tcpwm,
1680    #[cfg(feature = "tcpwm1")]
1681    pub TCPWM1: self::Tcpwm,
1682    #[cfg(feature = "lcd0")]
1683    pub LCD0: self::Lcd,
1684    #[cfg(feature = "usbfs0")]
1685    pub USBFS0: self::Usbfs,
1686    #[cfg(feature = "smif0")]
1687    pub SMIF0: self::Smif,
1688    #[cfg(feature = "sdhc0")]
1689    pub SDHC0: self::Sdhc,
1690    #[cfg(feature = "sdhc1")]
1691    pub SDHC1: self::Sdhc,
1692    #[cfg(feature = "scb0")]
1693    pub SCB0: self::Scb,
1694    #[cfg(feature = "scb1")]
1695    pub SCB1: self::Scb,
1696    #[cfg(feature = "scb2")]
1697    pub SCB2: self::Scb,
1698    #[cfg(feature = "scb3")]
1699    pub SCB3: self::Scb,
1700    #[cfg(feature = "scb4")]
1701    pub SCB4: self::Scb,
1702    #[cfg(feature = "scb5")]
1703    pub SCB5: self::Scb,
1704    #[cfg(feature = "scb6")]
1705    pub SCB6: self::Scb,
1706    #[cfg(feature = "scb7")]
1707    pub SCB7: self::Scb,
1708    #[cfg(feature = "scb8")]
1709    pub SCB8: self::Scb,
1710    #[cfg(feature = "scb9")]
1711    pub SCB9: self::Scb,
1712    #[cfg(feature = "scb10")]
1713    pub SCB10: self::Scb,
1714    #[cfg(feature = "scb11")]
1715    pub SCB11: self::Scb,
1716    #[cfg(feature = "scb12")]
1717    pub SCB12: self::Scb,
1718    #[cfg(feature = "sar")]
1719    pub SAR: self::Sar,
1720    #[cfg(feature = "pass")]
1721    pub PASS: self::Pass,
1722    #[cfg(feature = "pdm0")]
1723    pub PDM0: self::Pdm,
1724    #[cfg(feature = "i2s0")]
1725    pub I2S0: self::I2S,
1726    #[cfg(feature = "i2s1")]
1727    pub I2S1: self::I2S,
1728}
1729
1730impl Peripherals {
1731    /// Returns Peripheral struct multiple times
1732    /// Required for compatibility with RTIC and other frameworks
1733    #[inline]
1734    pub fn take() -> Option<Self> {
1735        Some(Self::steal())
1736    }
1737
1738    /// Returns Peripheral struct multiple times
1739    /// Required for compatibility with RTIC and other frameworks
1740    #[inline]
1741    pub fn steal() -> Self {
1742        Peripherals {
1743            #[cfg(feature = "peri")]
1744            PERI: crate::PERI,
1745            #[cfg(feature = "peri_ms")]
1746            PERI_MS: crate::PERI_MS,
1747            #[cfg(feature = "crypto")]
1748            CRYPTO: crate::CRYPTO,
1749            #[cfg(feature = "cpuss")]
1750            CPUSS: crate::CPUSS,
1751            #[cfg(feature = "fault")]
1752            FAULT: crate::FAULT,
1753            #[cfg(feature = "ipc")]
1754            IPC: crate::IPC,
1755            #[cfg(feature = "prot")]
1756            PROT: crate::PROT,
1757            #[cfg(feature = "flashc")]
1758            FLASHC: crate::FLASHC,
1759            #[cfg(feature = "srss")]
1760            SRSS: crate::SRSS,
1761            #[cfg(feature = "backup")]
1762            BACKUP: crate::BACKUP,
1763            #[cfg(feature = "dw0")]
1764            DW0: crate::DW0,
1765            #[cfg(feature = "dw1")]
1766            DW1: crate::DW1,
1767            #[cfg(feature = "dmac")]
1768            DMAC: crate::DMAC,
1769            #[cfg(feature = "efuse")]
1770            EFUSE: crate::EFUSE,
1771            #[cfg(feature = "profile")]
1772            PROFILE: crate::PROFILE,
1773            #[cfg(feature = "hsiom")]
1774            HSIOM: crate::HSIOM,
1775            #[cfg(feature = "gpio")]
1776            GPIO: crate::GPIO,
1777            #[cfg(feature = "smartio")]
1778            SMARTIO: crate::SMARTIO,
1779            #[cfg(feature = "lpcomp")]
1780            LPCOMP: crate::LPCOMP,
1781            #[cfg(feature = "csd0")]
1782            CSD0: crate::CSD0,
1783            #[cfg(feature = "tcpwm0")]
1784            TCPWM0: crate::TCPWM0,
1785            #[cfg(feature = "tcpwm1")]
1786            TCPWM1: crate::TCPWM1,
1787            #[cfg(feature = "lcd0")]
1788            LCD0: crate::LCD0,
1789            #[cfg(feature = "usbfs0")]
1790            USBFS0: crate::USBFS0,
1791            #[cfg(feature = "smif0")]
1792            SMIF0: crate::SMIF0,
1793            #[cfg(feature = "sdhc0")]
1794            SDHC0: crate::SDHC0,
1795            #[cfg(feature = "sdhc1")]
1796            SDHC1: crate::SDHC1,
1797            #[cfg(feature = "scb0")]
1798            SCB0: crate::SCB0,
1799            #[cfg(feature = "scb1")]
1800            SCB1: crate::SCB1,
1801            #[cfg(feature = "scb2")]
1802            SCB2: crate::SCB2,
1803            #[cfg(feature = "scb3")]
1804            SCB3: crate::SCB3,
1805            #[cfg(feature = "scb4")]
1806            SCB4: crate::SCB4,
1807            #[cfg(feature = "scb5")]
1808            SCB5: crate::SCB5,
1809            #[cfg(feature = "scb6")]
1810            SCB6: crate::SCB6,
1811            #[cfg(feature = "scb7")]
1812            SCB7: crate::SCB7,
1813            #[cfg(feature = "scb8")]
1814            SCB8: crate::SCB8,
1815            #[cfg(feature = "scb9")]
1816            SCB9: crate::SCB9,
1817            #[cfg(feature = "scb10")]
1818            SCB10: crate::SCB10,
1819            #[cfg(feature = "scb11")]
1820            SCB11: crate::SCB11,
1821            #[cfg(feature = "scb12")]
1822            SCB12: crate::SCB12,
1823            #[cfg(feature = "sar")]
1824            SAR: crate::SAR,
1825            #[cfg(feature = "pass")]
1826            PASS: crate::PASS,
1827            #[cfg(feature = "pdm0")]
1828            PDM0: crate::PDM0,
1829            #[cfg(feature = "i2s0")]
1830            I2S0: crate::I2S0,
1831            #[cfg(feature = "i2s1")]
1832            I2S1: crate::I2S1,
1833        }
1834    }
1835}
psoc_pac_psoc6_02/lib.rs

psoc_pac_psoc6_02/
lib.rs
