Struct probe_rs::architecture::riscv::Riscv32

pub struct Riscv32 { /* fields omitted */ }

Methods

impl Riscv32

pub fn new(interface: RiscvCommunicationInterface) -> Self

Trait Implementations

impl Clone for Riscv32

fn clone(&self) -> Riscv32

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl CoreInterface for Riscv32

fn wait_for_core_halted(&self) -> Result<(), Error>

Wait until the core is halted. If the core does not halt on its own, a [DebugProbeError::Timeout] error will be returned.

fn core_halted(&self) -> Result<bool, Error>

Check if the core is halted. If the core does not halt on its own, a [CoreError::Timeout] error will be returned.

fn halt(&self) -> Result<CoreInformation, Error>

Try to halt the core. This function ensures the core is actually halted, and returns a [CoreError::Timeout] otherwise.

fn run(&self) -> Result<(), Error>

fn reset(&self) -> Result<(), Error>

Reset the core, and then continue to execute instructions. If the core should be halted after reset, use the [reset_and_halt] function.

fn reset_and_halt(&self) -> Result<CoreInformation, Error>

Reset the core, and then immediately halt. To continue execution after reset, use the [reset] function.

fn step(&self) -> Result<CoreInformation, Error>

Steps one instruction and then enters halted state again.

fn read_core_reg(&self, address: CoreRegisterAddress) -> Result<u32, Error>

fn write_core_reg(
    &self,
    address: CoreRegisterAddress,
    value: u32
) -> Result<(), Error>

fn get_available_breakpoint_units(&self) -> Result<u32, Error>

fn enable_breakpoints(&mut self, _state: bool) -> Result<(), Error>

fn set_breakpoint(&self, bp_unit_index: usize, addr: u32) -> Result<(), Error>

fn clear_breakpoint(&self, unit_index: usize) -> Result<(), Error>

fn registers(&self) -> &'static RegisterFile

fn memory(&self) -> Memory

fn hw_breakpoints_enabled(&self) -> bool

fn architecture(&self) -> Architecture