probe_rs/
error.rs

1use crate::architecture::arm::ArmError;
2use crate::architecture::riscv::communication_interface::RiscvError;
3use crate::architecture::xtensa::communication_interface::XtensaError;
4use crate::config::RegistryError;
5use crate::core::memory_mapped_registers::RegisterAddressOutOfBounds;
6use crate::memory::{InvalidDataLengthError, MemoryNotAlignedError};
7use crate::probe::DebugProbeError;
8
9/// The overarching error type which contains all possible errors as variants.
10#[derive(thiserror::Error, Debug, docsplay::Display)]
11pub enum Error {
12    /// An error with the usage of the probe occurred
13    Probe(#[from] DebugProbeError),
14    /// An ARM specific error occurred.
15    Arm(#[source] ArmError),
16    /// A RISC-V specific error occurred.
17    Riscv(#[source] RiscvError),
18    /// An Xtensa specific error occurred.
19    Xtensa(#[source] XtensaError),
20    /// Core {0} is not enabled.
21    CoreDisabled(usize),
22    /// Core {0} does not exist.
23    CoreNotFound(usize),
24    /// Unable to load specification for chip
25    ChipNotFound(#[from] RegistryError),
26    /// An operation was not performed because the required permissions were not given: {0}.
27    ///
28    /// This can for example happen when the core is locked and needs to be erased to be unlocked.
29    /// Then the correct permission needs to be given to automatically unlock the core to prevent accidental erases.
30    #[ignore_extra_doc_attributes]
31    MissingPermissions(String),
32    /// An error that is not architecture specific occurred: {0}
33    GenericCoreError(String),
34    /// Errors accessing core register: {0}
35    Register(String),
36
37    /// Error calculating the address of a register
38    #[error(transparent)]
39    RegisterAddressOutOfBounds(#[from] RegisterAddressOutOfBounds),
40    /// The {0} capability has not yet been implemented for this architecture.
41    ///
42    /// Because of the large varieties of supported architectures, it is not always possible for
43    /// a contributor to implement functionality for all of them. This allows us to
44    /// implement new functionality on selected architectures first, and then add support for
45    /// the other architectures later.
46    NotImplemented(&'static str),
47    /// Some uncategorized error occurred.
48    #[display("{0}")]
49    Other(String),
50    /// A timeout occurred.
51    // TODO: Errors below should be core specific
52    Timeout,
53    /// Memory access to address {0.address:#X?} was not aligned to {0.alignment} bytes.
54    #[error(transparent)]
55    MemoryNotAligned(#[from] MemoryNotAlignedError),
56    /// The data buffer had an invalid length.
57    #[error(transparent)]
58    InvalidDataLength(#[from] InvalidDataLengthError),
59    /// Failed to write CPU register {register}.
60    WriteRegister {
61        /// The name of the register that was tried to be written.
62        register: String,
63        /// The source error of this error.
64        source: Box<dyn std::error::Error + 'static + Send + Sync>,
65    },
66    /// Failed to read CPU register {register}.
67    ReadRegister {
68        /// The name of the register that was tried to be read.
69        register: String,
70        /// The source error of this error.
71        source: Box<dyn std::error::Error + 'static + Send + Sync>,
72    },
73
74    /// Error during breakpoint configuration
75    BreakpointOperation(#[from] BreakpointError),
76}
77
78/// Errors that occur during breakpoint configuration
79#[derive(thiserror::Error, Debug, docsplay::Display)]
80pub enum BreakpointError {
81    /// No breakpoint found at address {0:#010x}
82    NotFound(u64),
83}
84
85impl From<ArmError> for Error {
86    fn from(value: ArmError) -> Self {
87        match value {
88            ArmError::Timeout => Error::Timeout,
89            ArmError::MemoryNotAligned(e) => Error::MemoryNotAligned(e),
90            ArmError::InvalidDataLength(e) => Error::InvalidDataLength(e),
91            other => Error::Arm(other),
92        }
93    }
94}
probe_rs/error.rs

probe_rs/
error.rs
