probe_rs/core/
core_status.rs

1use crate::semihosting::SemihostingCommand;
2
3/// The status of the core.
4#[derive(Debug, PartialEq, Eq, Copy, Clone)]
5pub enum CoreStatus {
6    /// The core is currently running.
7    Running,
8    /// The core is currently halted. This also specifies the reason as a payload.
9    Halted(HaltReason),
10    /// This is a Cortex-M specific status, and will not be set or handled by RISC-V code.
11    LockedUp,
12    /// The core is currently sleeping.
13    Sleeping,
14    /// The core state is currently unknown. This is always the case when the core is first created.
15    Unknown,
16}
17
18impl CoreStatus {
19    /// Returns `true` if the core is currently halted.
20    pub fn is_halted(&self) -> bool {
21        matches!(self, CoreStatus::Halted(_))
22    }
23
24    /// Returns `true` if the core is currently running.
25    pub fn is_running(&self) -> bool {
26        self == &Self::Running
27    }
28}
29
30/// When the core halts due to a breakpoint request, some architectures will allow us to distinguish between a software and hardware breakpoint.
31#[derive(Debug, PartialEq, Eq, Copy, Clone)]
32pub enum BreakpointCause {
33    /// We encountered a hardware breakpoint.
34    Hardware,
35    /// We encountered a software breakpoint instruction.
36    Software,
37    /// We were not able to distinguish if this was a hardware or software breakpoint.
38    Unknown,
39    /// The target requested the host perform a semihosting operation.
40    ///
41    /// The core set up some registers into a well-specified state and then hit
42    /// a breakpoint. This indicates the core would like the debug probe to do
43    /// some work.
44    Semihosting(SemihostingCommand),
45}
46
47/// The reason why a core was halted.
48#[derive(Debug, PartialEq, Eq, Copy, Clone)]
49pub enum HaltReason {
50    /// Multiple reasons for a halt.
51    ///
52    /// This can happen for example when a single instruction
53    /// step ends up on a breakpoint, after which both breakpoint and step / request
54    /// are set.
55    Multiple,
56    /// Core halted due to a breakpoint. The cause is `Unknown` if we cannot distinguish between a hardware and software breakpoint.
57    Breakpoint(BreakpointCause),
58    /// Core halted due to an exception, e.g. an
59    /// an interrupt.
60    Exception,
61    /// Core halted due to a data watchpoint
62    Watchpoint,
63    /// Core halted after single step
64    Step,
65    /// Core halted because of a debugger request
66    Request,
67    /// External halt request
68    External,
69    /// Unknown reason for halt.
70    ///
71    /// This can happen for example when the core is already halted when we connect.
72    Unknown,
73}
74
75/// When a core hits an exception, we halt the core.
76///
77/// `VectorCatchCondition` describes which event exactly should trigger a halt.
78#[derive(Debug, PartialEq, Eq, Copy, Clone)]
79pub enum VectorCatchCondition {
80    /// We encountered a hardfault.
81    HardFault,
82    /// We encountered a local reset.
83    CoreReset,
84    /// We encountered a SecureFault.
85    SecureFault,
86    /// We encountered any exception.
87    All,
88}
probe_rs/core/core_status.rs

probe_rs/core/
core_status.rs
