Struct probe_rs::architecture::arm::dp::Ctrl

impl Ctrl

pub fn csyspwrupack(&self) -> bool

System powerup acknowledge. Indicates the status of the CSYSPWRUPACK signal. See Power control requirements and operation on page B2-78.

pub fn csyspwrupreq(&self) -> bool

System powerup request. This bit controls the CSYSPWRUPREQ signal. See Power control requirements and operation on page B2-78.

pub fn cdbgpwrupack(&self) -> bool

Debug powerup acknowledge. Indicates the status of the CDBGPWRUPACK signal. See Power control requirements and operation on page B2-78.

pub fn cdbgpwrupreq(&self) -> bool

Debug powerup request. This bit controls the CDBGPWRUPREQ signal. See Power control requirements and operation on page B2-78.

pub fn cdbgrstack(&self) -> bool

Debug reset acknowledge. Indicates the status of the CDBGRSTACK signal. See Debug reset control behavior on page B2-81.

pub fn c_dbg_rst_req(&self) -> bool

Debug reset request. This bit controls the CDBGRSTREQ signal. See Debug reset control request on page B2-82.

After a powerup reset, this bit is 0b0.

pub fn trn_cnt(&self) -> u16

Transaction counter. See The transaction counter on page B1-43. After a powerup reset, the value of this field is UNKNOWN.

It is IMPLEMENTATION DEFINED whether this field is implemented.

TRNCNT is not supported in MINDP configuration. In MINDP configuration, the effect of writing a value other than zero to TRNCNT or TRNMODE is UNPREDICTABLE. See also MINDP, Minimal DP extension on page B1-40.

pub fn mask_lane(&self) -> u8

For pushed operations, the DP performs a byte-by-byte comparison of the word that is supplied in an AP write transaction with the current word at the target AP address. The MASKLANE field is used to select the bytes to be included in this comparison. For more information about pushed operations, see Pushed-compare and pushed-verify operations on page B1-44.

Each of the four bits of the MASKLANE field corresponds to one of the four bytes of the words to be compared. Therefore, each bit is said to control one byte lane of the compare operation.

Table B2-8 shows how the bits of MASKLANE control the comparison masking.

pub fn w_data_err(&self) -> bool

This bit is set to 0b1 if one of the following Write Data Error occurs:

A parity or framing error on the data phase of a write.
A write that has been accepted by the DP is then discarded without being submitted to the AP. For more information, see Sticky flags and DP error responses on page B1-41.

Access to and how to clear this field are DATA LINK DEFINED:

JTAG-DP, all implementations

Access is reserved, RES0.

SW-DP, all implementations, and JTAG-DP, DPv1 and higher

Access is RO/WI.
To clear WDATAERR to 0b0, write 0b1 to the ABORT.WDERRCLR field in the ABORT register. A single write of the ABORT register can be used to clear multiple flags if necessary.

After clearing the WDATAERR flag, you must typically resend the corrupted data. After a powerup reset, WDATAERR is 0b0.

pub fn read_ok(&self) -> bool

This bit is DATA LINK DEFINED

On JTAG-DP, the bit is reserved, RES0.
On SW-DP, access is RO/WI.

If the response to the previous AP read or RDBUFF read was OK, the bit is set to 0b1. If the response was not OK, it is cleared to 0b0.

This flag always indicates the response to the last AP read access. See Protocol error response on page B4-114.

After a powerup reset, this bit is 0b0.

Note

This field is defined for DPv1 and higher only.

pub fn sticky_err(&self) -> bool

This bit is set to 0b1 if an error is returned by an AP transaction. See Sticky flags and DP error responses on page B1-41.

Access to and how to clear this field are DATA LINK DEFINED:

JTAG-DP, all implementations

Access is R/W1C.
To clear STICKYERR to 0b0, write 0b1 to it, which signals the DP to clear the flag and set it to 0b0. A single write of the CTRL/STAT register can be used to clear multiple flags if necessary.

STICKYERR can also be cleared using the ABORT.STKERRCLR field.

SW-DP, all implementations, and JTAG-DP, DPv1 and higher

Access is RO/WI.
To clear STICKYERR to 0b0, write 0b1 to the ABORT.STKERRCLR field in the ABORT register. A single write of the ABORT register can be used to clear multiple flags if necessary.

After clearing CTRL/STAT.STICKYERR, you must find the location where the error that caused the flag to be set occurred.

After a powerup reset, this bit is 0b0.

pub fn stick_cmp(&self) -> bool

This bit is set to 0b1 when a mismatch occurs during a pushed-compare operation or a match occurs during a pushed-verify operation. See Pushed-compare and pushed-verify operations on page B1-44. It is IMPLEMENTATION DEFINED whether this field is implemented. See MINDP, Minimal DP extension on page B1-40. Access to and how to clear this field are DATA LINK DEFINED:

JTAG-DP, all implementations

Access is R/W1C.
To clear STICKYCMP to 0b0, write 0b1 to it, which signals the DP to clear the flag and set it to 0b0. A single write of the CTRL/STAT register can be used to clear multiple flags if necessary. STICKYCMP can also be cleared using the ABORT.STKERRCLR field.

SW-DP, all implementations, and JTAG-DP, DPv1 and higher

Access is RO/WI. B2 DP Reference Information B2.2 DP register descriptions
To clear STICKYCMP to 0b0, write 0b1 to the ABORT.STKCMPCLR field in the ABORT register. A single write of the ABORT register can be used to clear multiple flags if necessary. After clearing STICKYCMP, you must retrieve the value of the transaction counter to find the location where the error that caused the flag to be set occurred.

After a powerup reset, this bit is 0b0.

pub fn trn_mode(&self) -> u8

This field sets the transfer mode for AP operations. In normal operation, AP transactions are passed to the AP for processing, as described in Using the AP to access debug resources on page A1-31. In pushed-verify and pushed-compare operations, the DP compares the value that is supplied in an AP write transaction with the value held in the target AP address. The AP write transaction generates a read access to the debug memory system as described in Pushed-compare and pushed-verify operations on page B1-44.

TRNMODE can have one of the following values:

0b00: Normal operation.
0b01: Pushed-verify mode.
0b10: Pushed-compare mode.
0b11: Reserved.

After a powerup reset, the value of this field is UNKNOWN.

Note

It is IMPLEMENTATION DEFINED whether this field is implemented.

TRNMODE is not supported in MINDP configuration. In MINDP configuration, the effect of writing a value other than zero to TRNCNT or TRNMODE is UNPREDICTABLE. See also MINDP, Minimal DP extension on page B1-40.

pub fn sticky_orun(&self) -> bool

If overrun detection is enabled, this bit is set to 0b1 when an overrun occurs. See bit[0] of this register for details of enabling overrun detection. Access to and how to clear this field are DATA LINK DEFINED:

JTAG-DP, all implementations

Access is R/W1C.
To clear STICKYORUN to 0b0, write 0b1 to it, which signals the DP to clear the flag and set it to 0b0. A single write of the CTRL/STAT register can be used to clear multiple flags if necessary. STICKYORUN can also be cleared using the ABORT.STKERRCLR field. SW-DP, all implementations, and JTAG-DP, DPv1 and higher
Access is RO/WI.
To clear STICKYORUN to 0b0, write 0b1 to the ABORT.ORUNERRCLR field in the ABORT register.

A single write of the ABORT register can be used to clear multiple flags if necessary. After clearing STICKYORUN, you must find out which DP or AP transaction initiated the overrun that caused the flag to be set, and repeat the transactions for that DP or AP from the transaction pointed to by the transaction counter.

After a powerup reset, this bit is 0b0.

pub fn orun_detect(&self) -> bool

This bit can have one of the following values:

0b0: Overrun detection is disabled.
0b1: Overrun detection is enabled.

For more information about overrun detection, see Sticky flags and DP error responses on page B1-41.

After a powerup reset, this bit is 0b0.

pub fn set_csyspwrupreq(&mut self, value: bool)

System powerup request. This bit controls the CSYSPWRUPREQ signal. See Power control requirements and operation on page B2-78.

pub fn set_cdbgpwrupreq(&mut self, value: bool)

Debug powerup request. This bit controls the CDBGPWRUPREQ signal. See Power control requirements and operation on page B2-78.

pub fn set_c_dbg_rst_req(&mut self, value: bool)

Debug reset request. This bit controls the CDBGRSTREQ signal. See Debug reset control request on page B2-82.

After a powerup reset, this bit is 0b0.

pub fn set_trn_cnt(&mut self, value: u16)

Transaction counter. See The transaction counter on page B1-43. After a powerup reset, the value of this field is UNKNOWN.

It is IMPLEMENTATION DEFINED whether this field is implemented.

TRNCNT is not supported in MINDP configuration. In MINDP configuration, the effect of writing a value other than zero to TRNCNT or TRNMODE is UNPREDICTABLE. See also MINDP, Minimal DP extension on page B1-40.

pub fn set_mask_lane(&mut self, value: u8)

For pushed operations, the DP performs a byte-by-byte comparison of the word that is supplied in an AP write transaction with the current word at the target AP address. The MASKLANE field is used to select the bytes to be included in this comparison. For more information about pushed operations, see Pushed-compare and pushed-verify operations on page B1-44.

Each of the four bits of the MASKLANE field corresponds to one of the four bytes of the words to be compared. Therefore, each bit is said to control one byte lane of the compare operation.

Table B2-8 shows how the bits of MASKLANE control the comparison masking.

pub fn set_orun_detect(&mut self, value: bool)

This bit can have one of the following values:

0b0: Overrun detection is disabled.
0b1: Overrun detection is enabled.

For more information about overrun detection, see Sticky flags and DP error responses on page B1-41.

After a powerup reset, this bit is 0b0.

Trait Implementations§

impl<T> BitRange<T> for Ctrlwhere
u32: BitRange<T>,

fn bit_range(&self, msb: usize, lsb: usize) -> T

Get a range of bits.

impl<T> BitRangeMut<T> for Ctrlwhere
u32: BitRangeMut<T>,

fn set_bit_range(&mut self, msb: usize, lsb: usize, value: T)

Set a range of bits.

impl Clone for Ctrl

fn clone(&self) -> Ctrl

Returns a copy of the value. Read more

1.0.0 · source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more

impl Debug for Ctrl

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

impl Default for Ctrl

fn default() -> Ctrl

Returns the “default value” for a type. Read more

impl DpRegister for Ctrl

const VERSION: DebugPortVersion = DebugPortVersion::DPv1

The version of the debug port that is required to read this register.

impl From<Ctrl> for u32

fn from(raw: Ctrl) -> Self

Converts to this type from the input type.

impl Register for Ctrl

const ADDRESS: u8 = 4u8

The address of the register (in bytes).

const NAME: &'static str = "CTRL/STAT"

The name of the register as string.

impl TryFrom<u32> for Ctrl

type Error = RegisterParseError

The type returned in the event of a conversion error.

fn try_from(raw: u32) -> Result<Self, Self::Error>

Performs the conversion.

Auto Trait Implementations§

impl UnwindSafe for Ctrl

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fn bit(&self, bit: usize) -> bool

Get a single bit.

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fn set_bit(&mut self, bit: usize, value: bool)

Set a single bit.

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