pub struct Riscv32<'probe> { /* private fields */ }
Expand description
A interface to operate RISC-V cores.
Implementations
sourceimpl<'probe> Riscv32<'probe>
impl<'probe> Riscv32<'probe>
sourcepub fn new(
interface: &'probe mut RiscvCommunicationInterface,
state: &'probe mut RiscVState
) -> Self
pub fn new(
interface: &'probe mut RiscvCommunicationInterface,
state: &'probe mut RiscVState
) -> Self
Create a new RISC-V interface.
Trait Implementations
sourceimpl<'probe> CoreInterface for Riscv32<'probe>
impl<'probe> CoreInterface for Riscv32<'probe>
sourcefn hw_breakpoints(&mut self) -> Result<Vec<Option<u64>>, Error>
fn hw_breakpoints(&mut self) -> Result<Vec<Option<u64>>, Error>
See docs on the CoreInterface::hw_breakpoints
trait
NOTE: For riscv, this assumes that only execution breakpoints are used.
sourcefn wait_for_core_halted(&mut self, timeout: Duration) -> Result<(), Error>
fn wait_for_core_halted(&mut self, timeout: Duration) -> Result<(), Error>
Wait until the core is halted. If the core does not halt on its own,
a DebugProbeError::Timeout
error will be returned. Read more
sourcefn core_halted(&mut self) -> Result<bool, Error>
fn core_halted(&mut self) -> Result<bool, Error>
Check if the core is halted. If the core does not halt on its own,
a DebugProbeError::Timeout
error will be returned. Read more
sourcefn halt(&mut self, timeout: Duration) -> Result<CoreInformation, Error>
fn halt(&mut self, timeout: Duration) -> Result<CoreInformation, Error>
Try to halt the core. This function ensures the core is actually halted, and
returns a DebugProbeError::Timeout
otherwise. Read more
sourcefn reset(&mut self) -> Result<(), Error>
fn reset(&mut self) -> Result<(), Error>
Reset the core, and then continue to execute instructions. If the core
should be halted after reset, use the reset_and_halt
function. Read more
sourcefn reset_and_halt(
&mut self,
_timeout: Duration
) -> Result<CoreInformation, Error>
fn reset_and_halt(
&mut self,
_timeout: Duration
) -> Result<CoreInformation, Error>
sourcefn step(&mut self) -> Result<CoreInformation, Error>
fn step(&mut self) -> Result<CoreInformation, Error>
Steps one instruction and then enters halted state again.
sourcefn read_core_reg(&mut self, address: RegisterId) -> Result<RegisterValue, Error>
fn read_core_reg(&mut self, address: RegisterId) -> Result<RegisterValue, Error>
Read the value of a core register.
sourcefn write_core_reg(
&mut self,
address: RegisterId,
value: RegisterValue
) -> Result<()>
fn write_core_reg(
&mut self,
address: RegisterId,
value: RegisterValue
) -> Result<()>
Write the value of a core register.
sourcefn available_breakpoint_units(&mut self) -> Result<u32, Error>
fn available_breakpoint_units(&mut self) -> Result<u32, Error>
Returns all the available breakpoint units of the core.
sourcefn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>
fn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>
Enables breakpoints on this core. If a breakpoint is set, it will halt as soon as it is hit.
sourcefn set_hw_breakpoint(
&mut self,
bp_unit_index: usize,
addr: u64
) -> Result<(), Error>
fn set_hw_breakpoint(
&mut self,
bp_unit_index: usize,
addr: u64
) -> Result<(), Error>
Sets a breakpoint at addr
. It does so by using unit bp_unit_index
.
sourcefn clear_hw_breakpoint(&mut self, unit_index: usize) -> Result<(), Error>
fn clear_hw_breakpoint(&mut self, unit_index: usize) -> Result<(), Error>
Clears the breakpoint configured in unit unit_index
.
sourcefn registers(&self) -> &'static RegisterFile
fn registers(&self) -> &'static RegisterFile
Returns a list of all the registers of this core.
sourcefn hw_breakpoints_enabled(&self) -> bool
fn hw_breakpoints_enabled(&self) -> bool
Returns true
if hwardware breakpoints are enabled, false
otherwise.
sourcefn architecture(&self) -> Architecture
fn architecture(&self) -> Architecture
Get the Architecture
of the Core.
sourcefn instruction_set(&mut self) -> Result<InstructionSet, Error>
fn instruction_set(&mut self) -> Result<InstructionSet, Error>
Determine the instruction set the core is operating in This must be queried while halted as this is a runtime decision for some core types Read more
sourcefn status(&mut self) -> Result<CoreStatus, Error>
fn status(&mut self) -> Result<CoreStatus, Error>
Returns the current status of the core.
sourcefn fpu_support(&mut self) -> Result<bool, Error>
fn fpu_support(&mut self) -> Result<bool, Error>
Determine if an FPU is present. This must be queried while halted as this is a runtime decision for some core types. Read more
sourcefn on_session_stop(&mut self) -> Result<(), Error>
fn on_session_stop(&mut self) -> Result<(), Error>
Called during session stop to do any pending cleanup
sourceimpl<'probe> MemoryInterface for Riscv32<'probe>
impl<'probe> MemoryInterface for Riscv32<'probe>
sourcefn supports_native_64bit_access(&mut self) -> bool
fn supports_native_64bit_access(&mut self) -> bool
Does this interface support native 64-bit wide accesses Read more
sourcefn read_word_64(&mut self, address: u64) -> Result<u64, Error>
fn read_word_64(&mut self, address: u64) -> Result<u64, Error>
Read a 64bit word of at address
. Read more
sourcefn read_word_32(&mut self, address: u64) -> Result<u32, Error>
fn read_word_32(&mut self, address: u64) -> Result<u32, Error>
Read a 32bit word of at address
. Read more
sourcefn read_64(&mut self, address: u64, data: &mut [u64]) -> Result<(), Error>
fn read_64(&mut self, address: u64, data: &mut [u64]) -> Result<(), Error>
Read a block of 64bit words at address
. Read more
sourcefn read_32(&mut self, address: u64, data: &mut [u32]) -> Result<(), Error>
fn read_32(&mut self, address: u64, data: &mut [u32]) -> Result<(), Error>
Read a block of 32bit words at address
. Read more
sourcefn read_8(&mut self, address: u64, data: &mut [u8]) -> Result<(), Error>
fn read_8(&mut self, address: u64, data: &mut [u8]) -> Result<(), Error>
Read a block of 8bit words at address
.
sourcefn write_word_64(&mut self, address: u64, data: u64) -> Result<(), Error>
fn write_word_64(&mut self, address: u64, data: u64) -> Result<(), Error>
Write a 64bit word at address
. Read more
sourcefn write_word_32(&mut self, address: u64, data: u32) -> Result<(), Error>
fn write_word_32(&mut self, address: u64, data: u32) -> Result<(), Error>
Write a 32bit word at address
. Read more
sourcefn write_word_8(&mut self, address: u64, data: u8) -> Result<(), Error>
fn write_word_8(&mut self, address: u64, data: u8) -> Result<(), Error>
Write an 8bit word at address
.
sourcefn write_64(&mut self, address: u64, data: &[u64]) -> Result<(), Error>
fn write_64(&mut self, address: u64, data: &[u64]) -> Result<(), Error>
Write a block of 64bit words at address
. Read more
sourcefn write_32(&mut self, address: u64, data: &[u32]) -> Result<(), Error>
fn write_32(&mut self, address: u64, data: &[u32]) -> Result<(), Error>
Write a block of 32bit words at address
. Read more
sourcefn write_8(&mut self, address: u64, data: &[u8]) -> Result<(), Error>
fn write_8(&mut self, address: u64, data: &[u8]) -> Result<(), Error>
Write a block of 8bit words at address
.
sourcefn read_mem_64bit(&mut self, address: u64, data: &mut [u8]) -> Result<(), Error>
fn read_mem_64bit(&mut self, address: u64, data: &mut [u8]) -> Result<(), Error>
Reads bytes using 64 bit memory access. Address must be 64 bit aligned and data must be an exact multiple of 8. Read more
Auto Trait Implementations
impl<'probe> !RefUnwindSafe for Riscv32<'probe>
impl<'probe> Send for Riscv32<'probe>
impl<'probe> !Sync for Riscv32<'probe>
impl<'probe> Unpin for Riscv32<'probe>
impl<'probe> !UnwindSafe for Riscv32<'probe>
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more