Struct probe_rs::architecture::riscv::Riscv32

pub struct Riscv32<'probe> { /* fields omitted */ }

Implementations

impl<'probe> Riscv32<'probe>

pub fn new(interface: &'probe mut RiscvCommunicationInterface) -> Self

Trait Implementations

impl<'probe> CoreInterface for Riscv32<'probe>

pub fn wait_for_core_halted(&mut self, timeout: Duration) -> Result<(), Error>

Wait until the core is halted. If the core does not halt on its own, a DebugProbeError::Timeout error will be returned.

pub fn core_halted(&mut self) -> Result<bool, Error>

Check if the core is halted. If the core does not halt on its own, a CoreError::Timeout error will be returned.

pub fn halt(&mut self, timeout: Duration) -> Result<CoreInformation, Error>

Try to halt the core. This function ensures the core is actually halted, and returns a CoreError::Timeout otherwise.

pub fn run(&mut self) -> Result<(), Error>

pub fn reset(&mut self) -> Result<(), Error>

Reset the core, and then continue to execute instructions. If the core should be halted after reset, use the reset_and_halt function.

pub fn reset_and_halt(
    &mut self,
    _timeout: Duration
) -> Result<CoreInformation, Error>

Reset the core, and then immediately halt. To continue execution after reset, use the reset function.

pub fn step(&mut self) -> Result<CoreInformation, Error>

Steps one instruction and then enters halted state again.

pub fn read_core_reg(
    &mut self,
    address: CoreRegisterAddress
) -> Result<u32, Error>

pub fn write_core_reg(
    &mut self,
    address: CoreRegisterAddress,
    value: u32
) -> Result<()>

pub fn get_available_breakpoint_units(&mut self) -> Result<u32, Error>

pub fn enable_breakpoints(&mut self, _state: bool) -> Result<(), Error>

pub fn set_breakpoint(
    &mut self,
    bp_unit_index: usize,
    addr: u32
) -> Result<(), Error>

pub fn clear_breakpoint(&mut self, unit_index: usize) -> Result<(), Error>

pub fn registers(&self) -> &'static RegisterFile

pub fn hw_breakpoints_enabled(&self) -> bool

pub fn architecture(&self) -> Architecture

Get the Architecture of the Core.

pub fn status(&mut self) -> Result<CoreStatus, Error>

impl<'probe> MemoryInterface for Riscv32<'probe>

pub fn read_word_32(&mut self, address: u32) -> Result<u32, Error>

Read a 32bit word of at address.

pub fn read_word_8(&mut self, address: u32) -> Result<u8, Error>

Read an 8bit word of at address.

pub fn read_32(&mut self, address: u32, data: &mut [u32]) -> Result<(), Error>

Read a block of 32bit words at address.

pub fn read_8(&mut self, address: u32, data: &mut [u8]) -> Result<(), Error>

Read a block of 8bit words at address.

pub fn write_word_32(&mut self, address: u32, data: u32) -> Result<(), Error>

Write a 32bit word at address.

pub fn write_word_8(&mut self, address: u32, data: u8) -> Result<(), Error>

Write an 8bit word at address.

pub fn write_32(&mut self, address: u32, data: &[u32]) -> Result<(), Error>

Write a block of 32bit words at address.

pub fn write_8(&mut self, address: u32, data: &[u8]) -> Result<(), Error>

Write a block of 8bit words at address.

pub fn flush(&mut self) -> Result<(), Error>

Flush any outstanding operations.