[][src]Enum probe_rs::architecture::riscv::communication_interface::RiscvBusAccess

pub enum RiscvBusAccess {
    A8,
    A16,
    A32,
    A64,
    A128,
}

Access width for bus access. This is used both for system bus access (sbcs register), as well for abstract commands.

Variants

A8
A16
A32
A64
A128

Trait Implementations

impl Clone for RiscvBusAccess[src]

impl Copy for RiscvBusAccess[src]

impl Debug for RiscvBusAccess[src]

impl From<RiscvBusAccess> for u8[src]

impl PartialEq<RiscvBusAccess> for RiscvBusAccess[src]

impl PartialOrd<RiscvBusAccess> for RiscvBusAccess[src]

impl StructuralPartialEq for RiscvBusAccess[src]

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> ToOwned for T where
    T: Clone
[src]

type Owned = T

The resulting type after obtaining ownership.

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.