Module register 

Register-plane nodes — 128-bit SIMD words as values (type_system_alignment.md §8.4 layer 2).

A register word is a plain 16-byte value with a lane-typed or raw view (polydat::ast::RegLanes). Views are free bitcasts: the RegView adapter (auto-inserted by the assembler for any reg→reg wire) retags without touching bits, so a word can be [i64; 2] for one op, [u8-ish bytes] for a shuffle, and algorithm-defined raw state for a third — at zero cost.

Families here:

• Splats — float lanes from f64 (exact for f32 lanes in range), integer lanes from a u64 bit-level constructor (k as iN per lane; range semantics belong to the adapter system, constructors are bit tools).
• Gather / conversions — [f32; 4] ↔ vec_f32 and a bounds-checked window gather from a slice.
• Lane access — get/set for f32 lanes, reads for i16/i64.
• Element-wise arithmetic — add/sub/mul across every lane family; integer ops wrap (lane arithmetic is modular, the range-checked story lives in scalar adapters).
• reg_dot_f32 — horizontal dot with a FIXED reduction tree ((l0+l1) + (l2+l3)), part of the op contract so results are reproducible everywhere (determinism D2).
• reg_shuffle_bytes — arbitrary byte permutation of the raw word from a 16-entry const mask (the SWAR/state-word workhorse).

Structs

RegAddF32

The reg_add_f32 node.

RegAddF64

The reg_add_f64 node.

RegAddI8

The reg_add_i8 node.

RegAddI16

The reg_add_i16 node.

RegAddI32

The reg_add_i32 node.

RegAddI64

The reg_add_i64 node.

RegDotF32

reg_dot_f32(a, b) — horizontal dot product with the FIXED reduction tree (l0*r0 + l1*r1) + (l2*r2 + l3*r3). The tree shape is part of the contract (determinism D2): every host and every execution tier produces bit-identical results.

RegGatherF32

reg_gather_f32(v, offset) — load lanes [offset, offset+4) of an f32 slice into a register word. Panics when the window runs past the end (silent zero-fill would corrupt distance math downstream).

RegLaneF32

reg_lane_f32(r, i) — read lane i (0..4), widened to f64.

RegLaneI16

reg_lane_i16(r, i) — read lane i (0..8).

RegLaneI64

reg_lane_i64(r, i) — read lane i (0..2).

RegMulF32

The reg_mul_f32 node.

RegMulF64

The reg_mul_f64 node.

RegMulI8

reg_mul_i8(a, b) — the wrapping product per lane. x86 has no byte-lane multiply short of AVX-512 and Cranelift lowers none, so native code runs this body through a helper.

RegMulI16

The reg_mul_i16 node.

RegMulI32

The reg_mul_i32 node.

RegMulI64

The reg_mul_i64 node.

RegShuffleBytes

reg_shuffle_bytes(x, mask) — arbitrary byte permutation of the raw word: output byte i is input byte mask[i]. The mask is a 16-entry const list, each entry < 16 (panic otherwise, at build time). Duplicate indices broadcast; this is the SWAR / state-word workhorse for lane rearrangement under any view. Native code bakes the mask into one shuffle instruction, so the node exposes it as its constants.

RegSplatF32

reg_splat_f32(k) — broadcast k (applied at f32 precision) into all four f32 lanes.

RegSplatF64

reg_splat_f64(k) — broadcast k into both f64 lanes.

RegSplatI8

reg_splat_i8(k) — bit-level broadcast: each lane is k as i8.

RegSplatI16

reg_splat_i16(k) — bit-level broadcast: each lane is k as i16.

RegSplatI32

reg_splat_i32(k) — bit-level broadcast: each lane is k as i32.

RegSplatI64

reg_splat_i64(k) — bit-level broadcast: each lane is k as i64.

RegSubF32

The reg_sub_f32 node.

RegSubF64

The reg_sub_f64 node.

RegSubI8

The reg_sub_i8 node.

RegSubI16

The reg_sub_i16 node.

RegSubI32

The reg_sub_i32 node.

RegSubI64

The reg_sub_i64 node.

RegToVecF32

reg_to_vec_f32(r) — the inverse projection.

RegView

Pass-through guard that retags a register word’s view. The bits are untouched — this is the materialized form of “views are free bitcasts” for intra-graph wires whose producer and consumer declare different lane typings. Auto-inserted by compile::assembly::auto_adapter for every reg→reg pair; rarely instantiated by hand.

RegWithLaneF32

reg_with_lane_f32(r, i, v) — copy of r with lane i replaced by v (at f32 precision).

VecToRegF32

vec_to_reg_f32(v) — a length-4 vec_f32 IS a reg_f32x4; panics on any other length.

Functions

gather_f32

The word of lanes [offset, offset+4) of v; panics past the end.

is_reg_port

true when t is any register-plane PortType.

lane_f32

Lane i of r as f32 lanes, widened.

lane_i16

Lane i of r as i16 lanes.

lane_i64

Lane i of r as i64 lanes.

mul_i8

The wrapping product of a and b as i8 lanes.

to_reg_f32

The word of a four-element v.

with_lane_f32

r with f32 lane i replaced by v.