[−][src]Struct pl011_qemu::PL011_Regs

#[repr(C)]pub struct PL011_Regs {
    pub uartdr: RW<u32>,
    pub uartrsr: RW<u32>,
    pub uartfr: RO<u32>,
    pub uartilpr: RW<u32>,
    pub uartibrd: RW<u32>,
    pub uartfbrd: RW<u32>,
    pub uartlcr_h: RW<u32>,
    pub uartcr: RW<u32>,
    pub uartifls: RW<u32>,
    pub uartimsc: RW<u32>,
    pub uartris: RO<u32>,
    pub uartmis: RO<u32>,
    pub uarticr: WO<u32>,
    pub uartdmacr: RW<u32>,
    pub uartperiphid0: RO<u32>,
    pub uartperiphid1: RO<u32>,
    pub uartperiphid2: RO<u32>,
    pub uartperiphid3: RO<u32>,
    pub uartpcellid0: RO<u32>,
    pub uartpcellid1: RO<u32>,
    pub uartpcellid2: RO<u32>,
    pub uartpcellid3: RO<u32>,
    // some fields omitted
}

Struct representing PL011 registers. Not intended to be directly used

Fields

uartdr: RW<u32>

Data Register

uartrsr: RW<u32>

receive status / error clear

uartfr: RO<u32>

flag register

uartilpr: RW<u32>

IrDA Low power counter register

uartibrd: RW<u32>

integer baud rate

uartfbrd: RW<u32>

fractional baud rate

uartlcr_h: RW<u32>

line control

uartcr: RW<u32>

control

uartifls: RW<u32>

interrupt fifo level select

uartimsc: RW<u32>

interrupt mask set/clear

uartris: RO<u32>

raw interrupt status

uartmis: RO<u32>

masked interrupt status

uarticr: WO<u32>

interrupt clear

uartdmacr: RW<u32>

dma control

uartperiphid0: RO<u32>

UART Periph ID0

uartperiphid1: RO<u32>

UART Periph ID1

uartperiphid2: RO<u32>

UART Periph ID2

uartperiphid3: RO<u32>

UART Periph ID3

uartpcellid0: RO<u32>

UART PCell ID0

uartpcellid1: RO<u32>

UART PCell ID1

uartpcellid2: RO<u32>

UART PCell ID2

uartpcellid3: RO<u32>

UART PCell ID3

Auto Trait Implementations

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impl<T> Any for T where
    T: 'static + ?Sized, [src]

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    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

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type Output = T

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    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

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