pico_xs/registers/
sio.rs

1/// SIO_BASE ADDRESS
2use crate::xs::Bits;
3pub const BASE: u32 = 0xd000_0000;
4
5/// # Raw addresses and methods to interact with SIO gpio registers.
6///
7/// ## Adresses:
8/// GPIO OUTPUT VALUE
9pub const GPIO_OUT: *mut u32 = (BASE + 0x10) as *mut u32;
10/// GPIO OUTPUT VALUE SET
11pub const GPIO_OUT_SET: *mut u32 = (BASE + 0x14) as *mut u32;
12/// GPIO OUTPUT VALUE CLEAR
13pub const GPIO_OUT_CLR: *mut u32 = (BASE + 0x18) as *mut u32;
14/// GPIO OUTPUT VALUE XOR
15pub const GPIO_OUT_XOR: *mut u32 = (BASE + 0x1C) as *mut u32;
16/// GPIO OUTPUT ENABLE
17pub const GPIO_OE: *mut u32 = (BASE + 0x20) as *mut u32;
18/// GPIO OUTPUT ENABLE SET
19pub const GPIO_OE_SET: *mut u32 = (BASE + 0x24) as *mut u32;
20/// GPIO OUTPUT ENABLE CLEAR
21pub const GPIO_OE_CLR: *mut u32 = (BASE + 0x28) as *mut u32;
22/// GPIO OUTPUT ENABLE XOR
23pub const GPIO_OE_XOR: *mut u32 = (BASE + 0x2C) as *mut u32;
24/// Methods
25///
26pub fn gpio_oe_set(gpio: u32) {
27    GPIO_OE_SET.set(1 << gpio);
28}
29pub fn gpio_oe_clr(gpio: u32) {
30    GPIO_OE_CLR.clear(1 << gpio);
31}
32pub fn gpio_oe_xor(gpio: u32) {
33    GPIO_OE_XOR.xor(1 << gpio);
34}
35pub fn gpio_out_set(gpio: u32) {
36    GPIO_OUT_SET.set(1 << gpio);
37}
38pub fn gpio_out_clr(gpio: u32) {
39    GPIO_OUT_CLR.set(1 << gpio);
40}
41pub fn gpio_out_xor(gpio: u32) {
42    GPIO_OUT_XOR.xor(1 << gpio);
43}
44
45/// Struct for GPIO_OUT and GPIO_OE, because they share register-memory structure and methods.
46pub struct OutputSet {
47    gpio: u32,
48    base_address: *mut u32,
49    set: *mut u32,
50    clear: *mut u32,
51    xor: *mut u32,
52}
53
54impl OutputSet {
55    pub fn new(base_address: u32, gpio_pin: u32) -> Self {
56        Self {
57            gpio: gpio_pin,
58            base_address: base_address as *mut u32,
59            set: (base_address + 0x04) as *mut u32,
60            clear: (base_address + 0x08) as *mut u32,
61            xor: (base_address + 0x0c) as *mut u32,
62        }
63    }
64
65    pub fn set(&mut self) {
66        self.set.set(1 << self.gpio);
67    }
68
69    pub fn clr(&mut self) {
70        self.clear.set(1 << self.gpio);
71    }
72
73    pub fn xor(&mut self) {
74        self.xor.xor(1 << self.gpio);
75    }
76}
77
78pub fn gpio_input_value() -> u32 {
79    // GPIO_IN Register 29:0 where each bit represents the input value of the corresponding GPIO pin
80    //
81    const GPIO_IN: *mut u32 = (BASE + 0x004) as *mut u32;
82    let value: u32;
83    unsafe {
84        value = GPIO_IN.read_volatile();
85    }
86    value
87}
pico_xs/registers/sio.rs

pico_xs/registers/
sio.rs
