Struct Spi 

pub struct Spi<S, D, P, const DS: u8 = 8>
where
    S: State,
    D: SpiDevice,
    P: ValidSpiPinout<D>,
{ /* private fields */ }

Configured Spi bus.

This struct implements the embedded-hal Spi-related traits. It represents unique ownership of the entire Spi bus of a single configured rp235x Spi peripheral.

Spi has four generic parameters:

• S: a typestate for whether the bus is Enabled or Disabled. Upon initial creation, the bus is Disabled. You will then need to initialize it as either a main (master) or sub (slave) device, providing the necessary configuration, at which point it will become Enabled.

• D: Which of the concrete Spi peripherals is being used, pac::SPI0 or pac::SPI1

• P: Which pins are being used to configure the Spi peripheral D. A table of valid pinouts for each Spi peripheral can be found in section X.X.X of the rp235x datasheet.

  The ValidSpiPinout trait is implemented for tuples of pin types that follow the layout:

  • (Tx, Sck) (i.e. first the “Tx”/“MOSI” pin, then the “Sck”/“Clock” pin)
  • (Tx, Rx, Sck) (i.e. first “Tx”/“MOSI”, then “Rx”/“MISO”, then “Sck”/“Clock” pin)

  If you select an invalid layout, you will get a compile error that P does not implement ValidSpiPinout for your specified SpiDevice peripheral D

• DS: The “data size”, i.e. the number of bits transferred per data frame. Defaults to 8.

In most cases you won’t have to specify these types manually and can let the compiler infer them for you based on the values you pass in to new. If you want to select a different data frame size, you’ll need to do that by specifying the DS parameter manually.

See the module level docs for an example.

Implementations

impl<S, D, P, const DS: u8> Spi<S, D, P, DS>

where S: State, D: SpiDevice, P: ValidSpiPinout<D>,

pub fn free(self) -> (D, P)

Releases the underlying device and pins.

pub fn set_baudrate<F, B>( &mut self, peri_frequency: F, baudrate: B, ) -> Rate<u32, 1, 1>

where F: Into<Rate<u32, 1, 1>>, B: Into<Rate<u32, 1, 1>>,

Set device pre-scale and post-div properties to match the given baudrate as closely as possible based on the given peripheral clock frequency.

Typically the peripheral clock is set to 125_000_000 Hz.

Returns the frequency that we were able to achieve, which may not be exactly the requested baudrate.

pub fn set_format(&mut self, frame_format: FrameFormat)

Set format

impl<D, P, const DS: u8> Spi<Disabled, D, P, DS>

where D: SpiDevice, P: ValidSpiPinout<D>,

pub fn new(device: D, pins: P) -> Spi<Disabled, D, P, DS>

Create new not initialized Spi bus. Initialize it with .init or .init_slave.

Valid pin sets are in the form of (Tx, Sck) or (Tx, Rx, Sck)

If your pins are dynamically identified (Pin<DynPinId, _, _>) they will first need to pass validation using their corresponding ValidatedPinXX.

pub fn init<F, B, M>( self, resets: &mut RESETS, peri_frequency: F, baudrate: B, frame_format: M, ) -> Spi<Enabled, D, P, DS>

where F: Into<Rate<u32, 1, 1>>, B: Into<Rate<u32, 1, 1>>, M: Into<FrameFormat>,

Initialize the SPI in master mode

pub fn init_slave<M>( self, resets: &mut RESETS, frame_format: M, ) -> Spi<Enabled, D, P, DS>

where M: Into<FrameFormat>,

Initialize the SPI in slave mode

impl<D, P, const DS: u8> Spi<Enabled, D, P, DS>

where D: SpiDevice, P: ValidSpiPinout<D>,

pub fn is_busy(&self) -> bool

Check if spi is busy transmitting and/or receiving

pub fn disable(self) -> Spi<Disabled, D, P, DS>

Disable the spi to reset its configuration. You’ll then need to initialize it again to use it.

Trait Implementations

impl<D, P> ErrorType for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> ErrorType for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

Error type.

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u16) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u16) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u16) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u16) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u16) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u16) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u16) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u16) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u16) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u16) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u16) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u16) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u16) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u16) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u16) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u16> for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u16, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u16) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex<u8> for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u8, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u8) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u8> for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u8, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u8) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u8> for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u8, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u8) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u8> for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u8, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u8) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex<u8> for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

type Error = Infallible

An enumeration of SPI errors

fn read(&mut self) -> Result<u8, Error<Infallible>>

Reads the word stored in the shift register

fn send(&mut self, word: u8) -> Result<(), Error<Infallible>>

Sends a word to the slave

impl<D, P> FullDuplex for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u8, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u8) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u8, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u8) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u8, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u8) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u8, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u8) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> FullDuplex for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read(&mut self) -> Result<u8, Error<Infallible>>

Reads the word stored in the shift register

fn write(&mut self, word: u8) -> Result<(), Error<Infallible>>

Writes a word to the slave

impl<D, P> ReadTarget for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u8

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u8

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u8

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u8

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u8

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> ReadTarget for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

type ReceivedWord = u16

Type which is transferred in a single DMA transfer.

fn rx_treq() -> Option<u8>

Returns the DREQ number for this data source (None for memory buffers).

fn rx_address_count(&self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn rx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> SpiBus<u16> for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 10> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 10> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u16], write: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 10> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 10> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 10> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus<u16> for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 11> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 11> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u16], write: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 11> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 11> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 11> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus<u16> for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 12> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 12> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u16], write: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 12> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 12> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 12> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus<u16> for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 13> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 13> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u16], write: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 13> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 13> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 13> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus<u16> for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 14> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 14> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u16], write: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 14> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 14> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 14> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus<u16> for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 15> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 15> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u16], write: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 15> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 15> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 15> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus<u16> for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 16> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 16> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u16], write: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 16> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 16> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 16> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus<u16> for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 9> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 9> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u16], write: &[u16], ) -> Result<(), <Spi<Enabled, D, P, 9> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u16], ) -> Result<(), <Spi<Enabled, D, P, 9> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 9> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u8], ) -> Result<(), <Spi<Enabled, D, P> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u8], ) -> Result<(), <Spi<Enabled, D, P> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u8], write: &[u8], ) -> Result<(), <Spi<Enabled, D, P> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u8], ) -> Result<(), <Spi<Enabled, D, P> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u8], ) -> Result<(), <Spi<Enabled, D, P, 4> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u8], ) -> Result<(), <Spi<Enabled, D, P, 4> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u8], write: &[u8], ) -> Result<(), <Spi<Enabled, D, P, 4> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u8], ) -> Result<(), <Spi<Enabled, D, P, 4> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 4> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u8], ) -> Result<(), <Spi<Enabled, D, P, 5> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u8], ) -> Result<(), <Spi<Enabled, D, P, 5> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u8], write: &[u8], ) -> Result<(), <Spi<Enabled, D, P, 5> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u8], ) -> Result<(), <Spi<Enabled, D, P, 5> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 5> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u8], ) -> Result<(), <Spi<Enabled, D, P, 6> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u8], ) -> Result<(), <Spi<Enabled, D, P, 6> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u8], write: &[u8], ) -> Result<(), <Spi<Enabled, D, P, 6> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u8], ) -> Result<(), <Spi<Enabled, D, P, 6> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 6> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> SpiBus for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

fn read( &mut self, words: &mut [u8], ) -> Result<(), <Spi<Enabled, D, P, 7> as ErrorType>::Error>

Read words from the slave.

fn write( &mut self, words: &[u8], ) -> Result<(), <Spi<Enabled, D, P, 7> as ErrorType>::Error>

Write words to the slave, ignoring all the incoming words.

fn transfer( &mut self, read: &mut [u8], write: &[u8], ) -> Result<(), <Spi<Enabled, D, P, 7> as ErrorType>::Error>

Write and read simultaneously. write is written to the slave on MOSI and words received on MISO are stored in read.

fn transfer_in_place( &mut self, words: &mut [u8], ) -> Result<(), <Spi<Enabled, D, P, 7> as ErrorType>::Error>

Write and read simultaneously. The contents of words are written to the slave, and the received words are stored into the same words buffer, overwriting it.

fn flush(&mut self) -> Result<(), <Spi<Enabled, D, P, 7> as ErrorType>::Error>

Wait until all operations have completed and the bus is idle.

impl<D, P> WriteTarget for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u8

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u8

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u8

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u8

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u8

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> WriteTarget for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

type TransmittedWord = u16

Type which is transferred in a single DMA transfer.

fn tx_treq() -> Option<u8>

Returns the DREQ number for this data sink (None for memory buffers).

fn tx_address_count(&mut self) -> (u32, u32)

Returns the address and the maximum number of words that can be transferred from this data source in a single DMA operation.

fn tx_increment(&self) -> bool

Returns whether the address shall be incremented after each transfer.

impl<D, P> Default<u16> for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u16> for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> Default<u8> for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessReadTarget for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 10>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 11>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 12>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 13>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 14>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 15>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 16>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 4>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 5>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 6>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 7>

where D: SpiDevice, P: ValidSpiPinout<D>,

impl<D, P> EndlessWriteTarget for Spi<Enabled, D, P, 9>

where D: SpiDevice, P: ValidSpiPinout<D>,