Module lock 

Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to.

Structs

LOCK_SPEC

Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to.

Type Aliases

CORE0_R

Field CORE0 reader -

CORE0_W

Field CORE0 writer -

CORE1_R

Field CORE1 reader -

CORE1_W

Field CORE1 writer -

DEBUG_R

Field DEBUG reader -

DEBUG_W

Field DEBUG writer -

DMA_R

Field DMA reader -

R

Register LOCK reader

W

Register LOCK writer