pub type SRAM5 = Reg<SRAM5_SPEC>;Expand description
SRAM5 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
You can read this register and get sram5::R. You can reset, write, write_with_zero this register using sram5::W. You can also modify this register. See API.
For information about available fields see sram5
module
Aliased Typeยง
pub struct SRAM5 { /* private fields */ }