[][src]Enum perf_event::events::CacheResult

#[repr(u32)]
pub enum CacheResult {
    ACCESS,
    MISS,
}

What sort of cache result we're interested in observing.

ACCESS counts the total number of operations performed on the cache, whereas MISS counts only those requests that the cache could not satisfy. Treating MISS as a fraction of ACCESS gives you the cache's miss rate.

This is used used in the Cache type as part of the identification of a cache event. Each variant here corresponds to a particular PERF_COUNT_HW_CACHE_RESULT_... constant supported by the perf_event_open system call.

Variants

ACCESS

to measure accesses

MISS

to measure misses

Trait Implementations

impl Clone for CacheResult[src]

impl Copy for CacheResult[src]

impl Debug for CacheResult[src]

impl Eq for CacheResult[src]

impl PartialEq<CacheResult> for CacheResult[src]

impl StructuralEq for CacheResult[src]

impl StructuralPartialEq for CacheResult[src]

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> ToOwned for T where
    T: Clone
[src]

type Owned = T

The resulting type after obtaining ownership.

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.