perf_count/
event.rs

1#[derive(Debug, Clone)]
2pub enum Event {
3    /// Total cycles.
4    CPUCycles,
5    /// Retired instructions.  Be careful, these can be affected by various issues, most notably
6    /// hardware interrupt counts.
7    Instructions,
8    /// Cache accesses. Usually this indicates Last Level Cache accesses but this may vary depending
9    /// on your CPU. This may include prefetches and coherency messages; again this depends on the
10    /// design of your CPU.
11    CacheReferences,
12
13    /// Cache misses. Usually this indicates Last Level Cache misses; this is intended to be used in
14    /// conjunction with the [CacheReferences] event to calculate cache miss rates.
15    CacheMisses,
16
17    /// Retired branch instructions.  Prior to Linux 2.6.34, this used the wrong event on AMD
18    /// processors.
19    BranchInstructions,
20
21    /// Mispredicted branch instructions.
22    BranchMisses,
23
24    /// This counts context switches.
25    ContextSwitches,
26}
perf_count/event.rs

perf_count/
event.rs
