Crate patina_paging 

Paging

Implementation for identity mapped page table management for x64 and aarch64. This library provides structures that allow building, installing, and editing page tables in a no_std environment and without the use of Alloc.

The PageTable trait provides the interface for managing page tables. The caller must provide an implementation of the page_allocator::PageAllocator trait which the page table implementation will use to allocate pages of physical memory for use in the page tables.

This crate currently contains two concrete implementations of the PageTable trait: x64::X64PageTable and aarch64::AArch64PageTable.

Safety Assumptions

This crate is intended for low-level firmware and kernel environments. Using it assumes table-stakes execution conditions:

• The caller is running at a privilege level that can safely read/write paging control registers.
• Interrupts are disabled while performing page-table mutations that temporarily relax protections.

Callers are responsible for upholding these conditions when invoking APIs that touch hardware paging state.

Features

• supervisor: Accepts the MemoryAttributes::Supervisor attribute and enforces it on X64 by clearing the User/Supervisor bit of the affected page table entries, restricting those pages to supervisor-mode access. This feature also disables CPU write protection (clears CR0.WP) before mutating a page table entry and re-enables it immediately afterward, so the entry can be updated if the page tables are mapped read-only. This feature is only supported on X64. Enabling it for a non-X64 target (e.g. aarch64) has no effect.

Examples

use patina_paging::{aarch64, x64, MemoryAttributes, PageTable, PagingType, PtError};
use patina_paging::page_allocator::PageAllocator;

struct MyPageAllocator;
impl PageAllocator for MyPageAllocator {
   fn allocate_page(&mut self, align: u64, size: u64, is_root: bool) -> Result<u64, PtError> {
      // Return page aligned address of the allocated page, or an error.
      Ok(0)
   }
}

fn main_x64() -> Result<(), PtError> {
    // Create a X64 page table.
    let mut allocator = MyPageAllocator;
    let mut page_table = x64::X64PageTable::new(allocator, PagingType::Paging4Level)?;

    // Map a memory region with read-only and write-back attributes.
    page_table.map_memory_region(0x1000, 0x2000, MemoryAttributes::ReadOnly | MemoryAttributes::Writeback)?;

    // Install the page table.
    page_table.install_page_table()?;
    Ok(())
}

fn main_aarch64() -> Result<(), PtError> {
    // Create a AArch64 page table.
    let mut allocator = MyPageAllocator;
    let mut page_table = aarch64::AArch64PageTable::new(allocator, PagingType::Paging4Level)?;

    // Map a memory region with read-only and write-back attributes.
    page_table.map_memory_region(0x1000, 0x2000, MemoryAttributes::ReadOnly | MemoryAttributes::Writeback).unwrap();

    // Install the page table.
    page_table.install_page_table()?;
    Ok(())
}

License

Copyright (c) Microsoft Corporation.

SPDX-License-Identifier: Apache-2.0

Modules

aarch64

AArch64-specific implementation of page table management, including address translation and memory attribute handling.

page_allocator

x64

x64-specific implementation of page table management, including paging structures and address translation.

Structs

MappedRegion

A struct representing a mapped memory region, self-mapped or zero-VA are excluded.

MemoryAttributes

Enums

PagingType

PtError

Paging error codes. These are used to indicate errors that occur during paging operations. The errors are returned as a Result type, where Ok(T) indicates success and Err(PtError) indicates an error.

Traits

PageTable

PageTable trait is implemented by all concrete page table implementations and provides the interface for managing page tables.