Crate page_table_entry

page_table_entry

This crate provides the definition of page table entry for various hardware architectures.

Currently supported architectures and page table entry types:

• x86: x86_64::X64PTE
• ARM: aarch64::A64PTE
• RISC-V: riscv::Rv64PTE
• LoongArch: loongarch64::LA64PTE

All these types implement the GenericPTE trait, which provides unified methods for manipulating various page table entries.

Examples (x86_64)

use memory_addr::PhysAddr;
use x86_64::structures::paging::page_table::PageTableFlags;
use page_table_entry::{GenericPTE, MappingFlags, x86_64::X64PTE};

let paddr = PhysAddr::from(0x233000);
let pte = X64PTE::new_page(
    paddr,
    /* flags: */ MappingFlags::READ | MappingFlags::WRITE,
    /* is_huge: */ false,
);
assert!(!pte.is_unused());
assert!(pte.is_present());
assert_eq!(pte.paddr(), paddr);
assert_eq!(
    pte.bits(),
    0x800_0000000233_003, // PRESENT | WRITE | NO_EXECUTE | paddr(0x233000)
);

Modules

aarch64AArch64

AArch64 VMSAv8-64 translation table format descriptors.

loongarch64LoongArch LA64

loongarch64 page table entries.

riscvRISC-V RV32 or RISC-V RV64

RISC-V page table entries.

x86_64x86-64

x86 page table entries on 64-bit paging.

Structs

MappingFlags

Generic page table entry flags that indicate the corresponding mapped memory region permissions and attributes.

Traits

GenericPTE

A generic page table entry.