Module csr5 

CSR5 sparse matrix format.

CSR5 is a tile-based variant of CSR designed for load-balanced SpMV on GPUs. It divides the non-zero elements into fixed-size tiles (typically 32 elements wide, matching the warp size), with each tile assigned to one warp.

The key insight is that tiles may straddle row boundaries. The tile_desc array encodes where rows start and end within each tile, enabling each warp to know exactly which rows its elements contribute to.

Structure

A Csr5Matrix<T> contains:

• The original CSR arrays (row_ptr, col_idx, values)
• tile_ptr[num_tiles+1]: maps tile index to starting element index
• tile_desc[num_tiles]: bit-packed descriptor encoding row boundaries within each tile (which rows start/end in this tile)
• calibrator[rows]: workspace for cross-tile row contribution merging

Reference

W. Liu and B. Vinter, “CSR5: An Efficient Storage Format for Cross-Platform Sparse Matrix-Vector Multiplication”, ICS 2015.

Structs

Csr5Matrix

A sparse matrix in CSR5 format, stored on GPU.

TileDescriptor

Tile descriptor: bit-packed row boundary information for one tile.

Constants

CSR5_SIGMA

Number of rows encoded per tile descriptor segment. Each tile can contain contributions to multiple rows; this is the maximum tracked per tile.

CSR5_TILE_WIDTH

Number of non-zero elements per tile (warp width).