opencl_dynamic_sys/constants/
cl_ext.rs

1#![allow(non_upper_case_globals)]
2
3use crate::types::{
4    cl_bitfield, cl_channel_type, cl_command_queue_properties, cl_command_type, cl_device_info,
5    cl_event_info,
6    cl_ext::{
7        cl_accelerator_info_intel, cl_accelerator_type_intel, cl_amd_device_attribute_query,
8        cl_command_buffer_flags_khr, cl_command_buffer_info_khr, cl_command_buffer_properties_khr,
9        cl_command_buffer_state_khr, cl_command_buffer_structure_type_khr,
10        cl_command_queue_capabilities_intel, cl_command_termination_reason_arm,
11        cl_context_memory_initialize_khr, cl_device_command_buffer_capabilities_khr,
12        cl_device_controlled_termination_capabilities_arm, cl_device_feature_capabilities_intel,
13        cl_device_integer_dot_product_capabilities_khr, cl_device_partition_property_ext,
14        cl_device_scheduling_controls_capabilities_arm, cl_device_svm_capabilities_arm,
15        cl_device_unified_shared_memory_capabilities_intel, cl_diagnostics_verbose_level,
16        cl_external_memory_handle_type_khr, cl_external_semaphore_handle_type_khr,
17        cl_image_requirements_info_ext, cl_import_properties_arm, cl_intel_avc_motion_estimation,
18        cl_kernel_exec_info_arm, cl_mem_alloc_flags_img, cl_mem_alloc_flags_intel,
19        cl_mem_info_intel, cl_mem_migration_flags_ext, cl_mem_properties_intel,
20        cl_mipmap_filter_mode_img, cl_motion_detect_desc_intel, cl_mutable_command_info_khr,
21        cl_mutable_dispatch_asserts_khr, cl_mutable_dispatch_fields_khr,
22        cl_ndrange_kernel_command_properties_khr, cl_nv_device_attribute_query,
23        cl_platform_command_buffer_capabilities_khr, cl_qcom_ext_host_ptr, cl_queue_priority_khr,
24        cl_queue_throttle_khr, cl_semaphore_info_khr, cl_semaphore_properties_khr,
25        cl_semaphore_type_khr, cl_svm_mem_flags_arm, cl_unified_shared_memory_type_intel,
26        cl_version_khr,
27    },
28    cl_kernel_exec_info, cl_kernel_info, cl_kernel_sub_group_info, cl_mem_flags, cl_mem_info,
29    cl_platform::{cl_int, cl_uint, cl_ulong},
30    cl_platform_info, cl_program_info, cl_properties, cl_queue_properties, cl_sampler_properties,
31    size_t,
32};
33
34// cl_device_info
35pub const CL_DEVICE_COMMAND_BUFFER_CAPABILITIES_KHR: cl_device_info = 0x12A9;
36pub const CL_DEVICE_COMMAND_BUFFER_REQUIRED_QUEUE_PROPERTIES_KHR: cl_device_info = 0x12AA;
37
38// cl_device_command_buffer_capabilities_khr - bitfield
39pub const CL_COMMAND_BUFFER_CAPABILITY_KERNEL_PRINTF_KHR:
40    cl_device_command_buffer_capabilities_khr = 1 << 0;
41pub const CL_COMMAND_BUFFER_CAPABILITY_DEVICE_SIDE_ENQUEUE_KHR:
42    cl_device_command_buffer_capabilities_khr = 1 << 1;
43pub const CL_COMMAND_BUFFER_CAPABILITY_SIMULTANEOUS_USE_KHR:
44    cl_device_command_buffer_capabilities_khr = 1 << 2;
45pub const CL_COMMAND_BUFFER_CAPABILITY_OUT_OF_ORDER_KHR: cl_device_command_buffer_capabilities_khr =
46    1 << 3;
47
48// cl_command_buffer_properties_khr
49pub const CL_COMMAND_BUFFER_FLAGS_KHR: cl_command_buffer_properties_khr = 0x1293;
50
51// cl_command_buffer_flags_khr
52pub const CL_COMMAND_BUFFER_SIMULTANEOUS_USE_KHR: cl_command_buffer_flags_khr = 1 << 0;
53
54// Error codes
55pub const CL_INVALID_COMMAND_BUFFER_KHR: cl_int = -1138;
56pub const CL_INVALID_SYNC_POINT_WAIT_LIST_KHR: cl_int = -1139;
57pub const CL_INCOMPATIBLE_COMMAND_QUEUE_KHR: cl_int = -1140;
58
59// cl_command_buffer_info_khr
60pub const CL_COMMAND_BUFFER_QUEUES_KHR: cl_command_buffer_info_khr = 0x1294;
61pub const CL_COMMAND_BUFFER_NUM_QUEUES_KHR: cl_command_buffer_info_khr = 0x1295;
62pub const CL_COMMAND_BUFFER_REFERENCE_COUNT_KHR: cl_command_buffer_info_khr = 0x1296;
63pub const CL_COMMAND_BUFFER_STATE_KHR: cl_command_buffer_info_khr = 0x1297;
64pub const CL_COMMAND_BUFFER_PROPERTIES_ARRAY_KHR: cl_command_buffer_info_khr = 0x1298;
65pub const CL_COMMAND_BUFFER_CONTEXT_KHR: cl_command_buffer_info_khr = 0x1299;
66
67// cl_command_buffer_state_khr
68pub const CL_COMMAND_BUFFER_STATE_RECORDING_KHR: cl_command_buffer_state_khr = 0;
69pub const CL_COMMAND_BUFFER_STATE_EXECUTABLE_KHR: cl_command_buffer_state_khr = 1;
70pub const CL_COMMAND_BUFFER_STATE_PENDING_KHR: cl_command_buffer_state_khr = 2;
71
72// cl_command_type
73pub const CL_COMMAND_COMMAND_BUFFER_KHR: cl_command_type = 0x12A8;
74
75// cl_platform_info
76pub const CL_PLATFORM_COMMAND_BUFFER_CAPABILITIES_KHR: cl_platform_info = 0x0908;
77
78// cl_platform_command_buffer_capabilities_khr
79pub const CL_COMMAND_BUFFER_PLATFORM_UNIVERSAL_SYNC_KHR:
80    cl_platform_command_buffer_capabilities_khr = 1 << 0;
81pub const CL_COMMAND_BUFFER_PLATFORM_REMAP_QUEUES_KHR: cl_platform_command_buffer_capabilities_khr =
82    1 << 1;
83pub const CL_COMMAND_BUFFER_PLATFORM_AUTOMATIC_REMAP_KHR:
84    cl_platform_command_buffer_capabilities_khr = 1 << 2;
85
86// cl_device_info
87pub const CL_DEVICE_COMMAND_BUFFER_NUM_SYNC_DEVICES_KHR: cl_device_info = 0x12AB;
88pub const CL_DEVICE_COMMAND_BUFFER_SYNC_DEVICES_KHR: cl_device_info = 0x12AC;
89
90// cl_device_command_buffer_capabilities_khr
91pub const CL_COMMAND_BUFFER_CAPABILITY_MULTIPLE_QUEUE_KHR:
92    cl_device_command_buffer_capabilities_khr = 1 << 4;
93
94// cl_command_buffer_flags_khr
95pub const CL_COMMAND_BUFFER_DEVICE_SIDE_SYNC_KHR: cl_command_buffer_flags_khr = 1 << 2;
96
97pub const CL_COMMAND_BUFFER_MUTABLE_KHR: cl_command_buffer_flags_khr = 1 << 1;
98
99pub const CL_INVALID_MUTABLE_COMMAND_KHR: cl_int = -1141;
100
101pub const CL_DEVICE_MUTABLE_DISPATCH_CAPABILITIES_KHR: cl_device_info = 0x12B0;
102
103pub const CL_MUTABLE_DISPATCH_UPDATABLE_FIELDS_KHR: cl_ndrange_kernel_command_properties_khr =
104    0x12B1;
105
106pub const CL_MUTABLE_DISPATCH_GLOBAL_OFFSET_KHR: cl_mutable_dispatch_fields_khr = 1 << 0;
107pub const CL_MUTABLE_DISPATCH_GLOBAL_SIZE_KHR: cl_mutable_dispatch_fields_khr = 1 << 1;
108pub const CL_MUTABLE_DISPATCH_LOCAL_SIZE_KHR: cl_mutable_dispatch_fields_khr = 1 << 2;
109pub const CL_MUTABLE_DISPATCH_ARGUMENTS_KHR: cl_mutable_dispatch_fields_khr = 1 << 3;
110pub const CL_MUTABLE_DISPATCH_EXEC_INFO_KHR: cl_mutable_dispatch_fields_khr = 1 << 4;
111
112pub const CL_MUTABLE_COMMAND_COMMAND_QUEUE_KHR: cl_mutable_command_info_khr = 0x12A0;
113pub const CL_MUTABLE_COMMAND_COMMAND_BUFFER_KHR: cl_mutable_command_info_khr = 0x12A1;
114pub const CL_MUTABLE_COMMAND_COMMAND_TYPE_KHR: cl_mutable_command_info_khr = 0x12AD;
115pub const CL_MUTABLE_DISPATCH_PROPERTIES_ARRAY_KHR: cl_mutable_command_info_khr = 0x12A2;
116pub const CL_MUTABLE_DISPATCH_KERNEL_KHR: cl_mutable_command_info_khr = 0x12A3;
117pub const CL_MUTABLE_DISPATCH_DIMENSIONS_KHR: cl_mutable_command_info_khr = 0x12A4;
118pub const CL_MUTABLE_DISPATCH_GLOBAL_WORK_OFFSET_KHR: cl_mutable_command_info_khr = 0x12A5;
119pub const CL_MUTABLE_DISPATCH_GLOBAL_WORK_SIZE_KHR: cl_mutable_command_info_khr = 0x12A6;
120pub const CL_MUTABLE_DISPATCH_LOCAL_WORK_SIZE_KHR: cl_mutable_command_info_khr = 0x12A7;
121
122pub const CL_STRUCTURE_TYPE_MUTABLE_BASE_CONFIG_KHR: cl_command_buffer_structure_type_khr = 0;
123pub const CL_STRUCTURE_TYPE_MUTABLE_DISPATCH_CONFIG_KHR: cl_command_buffer_structure_type_khr = 1;
124
125pub const CL_COMMAND_BUFFER_MUTABLE_DISPATCH_ASSERTS_KHR: cl_command_buffer_properties_khr = 0x1287;
126
127pub const CL_MUTABLE_DISPATCH_ASSERTS_KHR: cl_ndrange_kernel_command_properties_khr = 0x12B8;
128
129pub const CL_MUTABLE_DISPATCH_ASSERT_NO_ADDITIONAL_WORK_GROUPS_KHR:
130    cl_mutable_dispatch_asserts_khr = 1 << 0;
131
132// cl_khr_fp64 extension
133pub const CL_DEVICE_DOUBLE_FP_CONFIG: cl_device_info = 0x1032;
134
135// cl_khr_fp16 extension
136pub const CL_DEVICE_HALF_FP_CONFIG: cl_device_info = 0x1033;
137
138// cl_khr_icd extension
139pub const CL_PLATFORM_ICD_SUFFIX_KHR: cl_platform_info = 0x0920;
140
141// Additional Error Codes
142pub const CL_PLATFORM_NOT_FOUND_KHR: cl_int = -1001;
143
144// cl_khr_il_program extension
145
146/// New property to clGetDeviceInfo for retrieving supported intermediate languages.
147pub const CL_DEVICE_IL_VERSION_KHR: cl_device_info = 0x105B;
148
149/// New property to clGetProgramInfo for retrieving for retrieving the IL of a program.
150pub const CL_PROGRAM_IL_KHR: cl_program_info = 0x1169;
151
152pub const CL_DEVICE_IMAGE_PITCH_ALIGNMENT_KHR: cl_device_info = 0x104A;
153pub const CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT_KHR: cl_device_info = 0x104B;
154
155// cl_khr_initialize_memory extension
156pub const CL_CONTEXT_MEMORY_INITIALIZE_KHR: cl_uint = 0x2030;
157
158// cl_context_memory_initialize_khr
159pub const CL_CONTEXT_MEMORY_INITIALIZE_LOCAL_KHR: cl_context_memory_initialize_khr = 1 << 0;
160pub const CL_CONTEXT_MEMORY_INITIALIZE_PRIVATE_KHR: cl_context_memory_initialize_khr = 1 << 1;
161
162// cl_khr_terminate_context extension
163pub const CL_CONTEXT_TERMINATED_KHR: cl_int = -1121;
164
165pub const CL_DEVICE_TERMINATE_CAPABILITY_KHR: cl_uint = 0x2031;
166pub const CL_CONTEXT_TERMINATE_KHR: cl_uint = 0x2032;
167
168// cl_khr_spir extension
169pub const CL_DEVICE_SPIR_VERSIONS: cl_uint = 0x40E0;
170pub const CL_PROGRAM_BINARY_TYPE_INTERMEDIATE: cl_uint = 0x40E1;
171
172// cl_nv_device_attribute_query extension
173pub const CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV: cl_nv_device_attribute_query = 0x4000;
174pub const CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV: cl_nv_device_attribute_query = 0x4001;
175pub const CL_DEVICE_REGISTERS_PER_BLOCK_NV: cl_nv_device_attribute_query = 0x4002;
176pub const CL_DEVICE_WARP_SIZE_NV: cl_nv_device_attribute_query = 0x4003;
177pub const CL_DEVICE_GPU_OVERLAP_NV: cl_nv_device_attribute_query = 0x4004;
178pub const CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV: cl_nv_device_attribute_query = 0x4005;
179pub const CL_DEVICE_INTEGRATED_MEMORY_NV: cl_nv_device_attribute_query = 0x4006;
180
181// undocumented tokens for clGetDeviceInfo, see: https://anteru.net/blog/2014/associating-opencl-device-ids-with-gpus/
182pub const CL_DEVICE_PCI_BUS_ID_NV: cl_nv_device_attribute_query = 0x4008;
183pub const CL_DEVICE_PCI_SLOT_ID_NV: cl_nv_device_attribute_query = 0x4009;
184
185// cl_amd_device_attribute_query
186pub const CL_DEVICE_PROFILING_TIMER_OFFSET_AMD: cl_amd_device_attribute_query = 0x4036;
187pub const CL_DEVICE_TOPOLOGY_AMD: cl_amd_device_attribute_query = 0x4037;
188pub const CL_DEVICE_BOARD_NAME_AMD: cl_amd_device_attribute_query = 0x4038;
189pub const CL_DEVICE_GLOBAL_FREE_MEMORY_AMD: cl_amd_device_attribute_query = 0x4039;
190pub const CL_DEVICE_SIMD_PER_COMPUTE_UNIT_AMD: cl_amd_device_attribute_query = 0x4040;
191pub const CL_DEVICE_SIMD_WIDTH_AMD: cl_amd_device_attribute_query = 0x4041;
192pub const CL_DEVICE_SIMD_INSTRUCTION_WIDTH_AMD: cl_amd_device_attribute_query = 0x4042;
193pub const CL_DEVICE_WAVEFRONT_WIDTH_AMD: cl_amd_device_attribute_query = 0x4043;
194pub const CL_DEVICE_GLOBAL_MEM_CHANNELS_AMD: cl_amd_device_attribute_query = 0x4044;
195pub const CL_DEVICE_GLOBAL_MEM_CHANNEL_BANKS_AMD: cl_amd_device_attribute_query = 0x4045;
196pub const CL_DEVICE_GLOBAL_MEM_CHANNEL_BANK_WIDTH_AMD: cl_amd_device_attribute_query = 0x4046;
197pub const CL_DEVICE_LOCAL_MEM_SIZE_PER_COMPUTE_UNIT_AMD: cl_amd_device_attribute_query = 0x4047;
198pub const CL_DEVICE_LOCAL_MEM_BANKS_AMD: cl_amd_device_attribute_query = 0x4048;
199pub const CL_DEVICE_THREAD_TRACE_SUPPORTED_AMD: cl_amd_device_attribute_query = 0x4049;
200pub const CL_DEVICE_GFXIP_MAJOR_AMD: cl_amd_device_attribute_query = 0x404A;
201pub const CL_DEVICE_GFXIP_MINOR_AMD: cl_amd_device_attribute_query = 0x404B;
202pub const CL_DEVICE_AVAILABLE_ASYNC_QUEUES_AMD: cl_amd_device_attribute_query = 0x404C;
203pub const CL_DEVICE_PREFERRED_WORK_GROUP_SIZE_AMD: cl_amd_device_attribute_query = 0x4030;
204pub const CL_DEVICE_MAX_WORK_GROUP_SIZE_AMD: cl_amd_device_attribute_query = 0x4031;
205pub const CL_DEVICE_PREFERRED_CONSTANT_BUFFER_SIZE_AMD: cl_amd_device_attribute_query = 0x4033;
206pub const CL_DEVICE_PCIE_ID_AMD: cl_amd_device_attribute_query = 0x4034;
207
208// cl_arm_printf extension
209pub const CL_PRINTF_CALLBACK_ARM: cl_uint = 0x40B0;
210pub const CL_PRINTF_BUFFERSIZE_ARM: cl_uint = 0x40B1;
211
212// cl_device_partition_property_ext
213pub const CL_DEVICE_PARTITION_EQUALLY_EXT: cl_device_partition_property_ext = 0x4050;
214pub const CL_DEVICE_PARTITION_BY_COUNTS_EXT: cl_device_partition_property_ext = 0x4051;
215pub const CL_DEVICE_PARTITION_BY_NAMES_EXT: cl_device_partition_property_ext = 0x4052;
216pub const CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN_EXT: cl_device_partition_property_ext = 0x4053;
217
218// clDeviceGetInfo selectors
219pub const CL_DEVICE_PARENT_DEVICE_EXT: cl_device_info = 0x4054;
220pub const CL_DEVICE_PARTITION_TYPES_EXT: cl_device_info = 0x4055;
221pub const CL_DEVICE_AFFINITY_DOMAINS_EXT: cl_device_info = 0x4056;
222pub const CL_DEVICE_REFERENCE_COUNT_EXT: cl_device_info = 0x4057;
223pub const CL_DEVICE_PARTITION_STYLE_EXT: cl_device_info = 0x4058;
224
225// error codes
226pub const CL_DEVICE_PARTITION_FAILED_EXT: cl_int = -1057;
227pub const CL_INVALID_PARTITION_COUNT_EXT: cl_int = -1058;
228pub const CL_INVALID_PARTITION_NAME_EXT: cl_int = -1059;
229
230// CL_AFFINITY_DOMAINs
231pub const CL_AFFINITY_DOMAIN_L1_CACHE_EXT: cl_uint = 0x1;
232pub const CL_AFFINITY_DOMAIN_L2_CACHE_EXT: cl_uint = 0x2;
233pub const CL_AFFINITY_DOMAIN_L3_CACHE_EXT: cl_uint = 0x3;
234pub const CL_AFFINITY_DOMAIN_L4_CACHE_EXT: cl_uint = 0x4;
235pub const CL_AFFINITY_DOMAIN_NUMA_EXT: cl_uint = 0x10;
236pub const CL_AFFINITY_DOMAIN_NEXT_FISSIONABLE_EXT: cl_uint = 0x100;
237
238// cl_device_partition_property_ext list terminators
239pub const CL_PROPERTIES_LIST_END_EXT: cl_device_partition_property_ext = 0;
240pub const CL_PARTITION_BY_COUNTS_LIST_END_EXT: cl_device_partition_property_ext = 0;
241pub const CL_PARTITION_BY_NAMES_LIST_END_EXT: cl_device_partition_property_ext = 0xFFFF_FFFF;
242
243// cl_ext_migrate_memobject extension definitions
244pub const CL_MIGRATE_MEM_OBJECT_HOST_EXT: cl_mem_migration_flags_ext = 0x1;
245pub const CL_COMMAND_MIGRATE_MEM_OBJECT_EXT: cl_mem_migration_flags_ext = 0x4040;
246
247// cl_ext_cxx_for_opencl extension
248pub const CL_DEVICE_CXX_FOR_OPENCL_NUMERIC_VERSION_EXT: cl_uint = 0x4230;
249
250// cl_qcom_ext_host_ptr extension
251pub const CL_MEM_EXT_HOST_PTR_QCOM: cl_qcom_ext_host_ptr = 1 << 29;
252
253pub const CL_DEVICE_EXT_MEM_PADDING_IN_BYTES_QCOM: cl_qcom_ext_host_ptr = 0x40A0;
254pub const CL_DEVICE_PAGE_SIZE_QCOM: cl_qcom_ext_host_ptr = 0x40A1;
255pub const CL_IMAGE_ROW_ALIGNMENT_QCOM: cl_qcom_ext_host_ptr = 0x40A2;
256pub const CL_IMAGE_SLICE_ALIGNMENT_QCOM: cl_qcom_ext_host_ptr = 0x40A3;
257pub const CL_MEM_HOST_UNCACHED_QCOM: cl_qcom_ext_host_ptr = 0x40A4;
258pub const CL_MEM_HOST_WRITEBACK_QCOM: cl_qcom_ext_host_ptr = 0x40A5;
259pub const CL_MEM_HOST_WRITETHROUGH_QCOM: cl_qcom_ext_host_ptr = 0x40A6;
260pub const CL_MEM_HOST_WRITE_COMBINING_QCOM: cl_qcom_ext_host_ptr = 0x40A7;
261
262// cl_qcom_ext_host_ptr_iocoherent extension
263// Cache policy specifying io-coherence
264pub const CL_MEM_HOST_IOCOHERENT_QCOM: cl_qcom_ext_host_ptr = 0x40A9;
265
266// cl_qcom_ion_host_ptr extension
267pub const CL_MEM_ION_HOST_PTR_QCOM: cl_qcom_ext_host_ptr = 0x40A8;
268
269//cl_qcom_android_native_buffer_host_ptr extension
270pub const CL_MEM_ANDROID_NATIVE_BUFFER_HOST_PTR_QCOM: cl_qcom_ext_host_ptr = 0x40C6;
271
272// cl_img_yuv_image extension
273pub const CL_NV21_IMG: cl_channel_type = 0x40D0;
274pub const CL_YV12_IMG: cl_channel_type = 0x40D1;
275
276// cl_img_cached_allocations extension
277pub const CL_MEM_USE_UNCACHED_CPU_MEMORY_IMG: cl_mem_flags = 1 << 26;
278pub const CL_MEM_USE_CACHED_CPU_MEMORY_IMG: cl_mem_flags = 1 << 27;
279
280// cl_img_use_gralloc_ptr extension
281pub const CL_MEM_USE_GRALLOC_PTR_IMG: cl_mem_flags = 1 << 28;
282
283// To be used by clGetEventInfo:
284pub const CL_COMMAND_ACQUIRE_GRALLOC_OBJECTS_IMG: cl_event_info = 0x40D2;
285pub const CL_COMMAND_RELEASE_GRALLOC_OBJECTS_IMG: cl_event_info = 0x40D3;
286
287// Error codes from clEnqueueAcquireGrallocObjectsIMG and clEnqueueReleaseGrallocObjectsIMG
288pub const CL_GRALLOC_RESOURCE_NOT_ACQUIRED_IMG: cl_int = 0x40D4;
289pub const CL_INVALID_GRALLOC_OBJECT_IMG: cl_int = 0x40D5;
290
291// cl_img_generate_mipmap extension
292
293// To be used by clEnqueueGenerateMipmapIMG
294pub const CL_MIPMAP_FILTER_ANY_IMG: cl_mipmap_filter_mode_img = 0x0;
295pub const CL_MIPMAP_FILTER_BOX_IMG: cl_mipmap_filter_mode_img = 0x1;
296
297// To be used by clGetEventInfo
298pub const CL_COMMAND_GENERATE_MIPMAP_IMG: cl_event_info = 0x40D6;
299
300// cl_img_mem_properties extension
301
302// To be used by clCreateBufferWithProperties
303pub const CL_MEM_ALLOC_FLAGS_IMG: cl_properties = 0x40D7;
304
305// To be used with cl_mem_alloc_flags_img
306pub const CL_MEM_ALLOC_RELAX_REQUIREMENTS_IMG: cl_mem_alloc_flags_img = 1 << 0;
307
308// cl_khr_subgroups extension
309pub const CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE_KHR: cl_kernel_sub_group_info = 0x2033;
310pub const CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE_KHR: cl_kernel_sub_group_info = 0x2034;
311
312// cl_khr_mipmap_image extension
313
314// cl_sampler_properties
315pub const CL_SAMPLER_MIP_FILTER_MODE_KHR: cl_sampler_properties = 0x1155;
316pub const CL_SAMPLER_LOD_MIN_KHR: cl_sampler_properties = 0x1156;
317pub const CL_SAMPLER_LOD_MAX_KHR: cl_sampler_properties = 0x1157;
318
319// cl_command_queue_properties
320pub const CL_QUEUE_PRIORITY_KHR: cl_command_queue_properties = 0x1096;
321
322// cl_queue_priority_khr
323pub const CL_QUEUE_PRIORITY_HIGH_KHR: cl_queue_priority_khr = 1 << 0;
324pub const CL_QUEUE_PRIORITY_MED_KHR: cl_queue_priority_khr = 1 << 1;
325pub const CL_QUEUE_PRIORITY_LOW_KHR: cl_queue_priority_khr = 1 << 2;
326
327// cl_command_queue_properties
328pub const CL_QUEUE_THROTTLE_KHR: cl_command_queue_properties = 0x1097;
329
330// cl_queue_throttle_khr
331pub const CL_QUEUE_THROTTLE_HIGH_KHR: cl_queue_throttle_khr = 1 << 0;
332pub const CL_QUEUE_THROTTLE_MED_KHR: cl_queue_throttle_khr = 1 << 1;
333pub const CL_QUEUE_THROTTLE_LOW_KHR: cl_queue_throttle_khr = 1 << 2;
334
335// cl_khr_subgroup_named_barrier
336
337// cl_device_info
338pub const CL_DEVICE_MAX_NAMED_BARRIER_COUNT_KHR: cl_device_info = 0x2035;
339
340pub const CL_VERSION_MAJOR_BITS_KHR: cl_version_khr = 10;
341pub const CL_VERSION_MINOR_BITS_KHR: cl_version_khr = 10;
342pub const CL_VERSION_PATCH_BITS_KHR: cl_version_khr = 12;
343
344pub const CL_VERSION_MAJOR_MASK_KHR: cl_version_khr = (1 << CL_VERSION_MAJOR_BITS_KHR) - 1;
345pub const CL_VERSION_MINOR_MASK_KHR: cl_version_khr = (1 << CL_VERSION_MINOR_BITS_KHR) - 1;
346pub const CL_VERSION_PATCH_MASK_KHR: cl_version_khr = (1 << CL_VERSION_PATCH_BITS_KHR) - 1;
347
348pub const CL_NAME_VERSION_MAX_NAME_SIZE_KHR: size_t = 64;
349
350// cl_platform_info
351pub const CL_PLATFORM_NUMERIC_VERSION_KHR: cl_platform_info = 0x0906;
352pub const CL_PLATFORM_EXTENSIONS_WITH_VERSION_KHR: cl_platform_info = 0x0907;
353
354// cl_device_info
355pub const CL_DEVICE_NUMERIC_VERSION_KHR: cl_device_info = 0x105E;
356pub const CL_DEVICE_OPENCL_C_NUMERIC_VERSION_KHR: cl_device_info = 0x105F;
357pub const CL_DEVICE_EXTENSIONS_WITH_VERSION_KHR: cl_device_info = 0x1060;
358pub const CL_DEVICE_ILS_WITH_VERSION_KHR: cl_device_info = 0x1061;
359pub const CL_DEVICE_BUILT_IN_KERNELS_WITH_VERSION_KHR: cl_device_info = 0x1062;
360
361// cl_khr_device_uuid extension
362
363pub const CL_UUID_SIZE_KHR: size_t = 16;
364pub const CL_LUID_SIZE_KHR: size_t = 8;
365
366pub const CL_DEVICE_UUID_KHR: cl_device_info = 0x106A;
367pub const CL_DRIVER_UUID_KHR: cl_device_info = 0x106B;
368pub const CL_DEVICE_LUID_VALID_KHR: cl_device_info = 0x106C;
369pub const CL_DEVICE_LUID_KHR: cl_device_info = 0x106D;
370pub const CL_DEVICE_NODE_MASK_KHR: cl_device_info = 0x106E;
371
372// cl_device_info
373pub const CL_DEVICE_PCI_BUS_INFO_KHR: cl_device_info = 0x410F;
374
375// cl_device_integer_dot_product_capabilities_khr
376pub const CL_DEVICE_INTEGER_DOT_PRODUCT_INPUT_4x8BIT_PACKED_KHR:
377    cl_device_integer_dot_product_capabilities_khr = 1 << 0;
378pub const CL_DEVICE_INTEGER_DOT_PRODUCT_INPUT_4x8BIT_KHR:
379    cl_device_integer_dot_product_capabilities_khr = 1 << 1;
380
381// cl_device_info
382pub const CL_DEVICE_INTEGER_DOT_PRODUCT_CAPABILITIES_KHR: cl_device_info = 0x1073;
383pub const CL_DEVICE_INTEGER_DOT_PRODUCT_ACCELERATION_PROPERTIES_8BIT_KHR: cl_device_info = 0x1074;
384pub const CL_DEVICE_INTEGER_DOT_PRODUCT_ACCELERATION_PROPERTIES_4x8BIT_PACKED_KHR: cl_device_info =
385    0x1075;
386
387// cl_khr_external_memory
388
389// cl_platform_info
390pub const CL_PLATFORM_EXTERNAL_MEMORY_IMPORT_HANDLE_TYPES_KHR: cl_platform_info = 0x2044;
391
392// cl_device_info
393pub const CL_DEVICE_EXTERNAL_MEMORY_IMPORT_HANDLE_TYPES_KHR: cl_device_info = 0x204F;
394pub const CL_DEVICE_EXTERNAL_MEMORY_IMPORT_ASSUME_LINEAR_IMAGES_HANDLE_TYPES_KHR: cl_device_info =
395    0x2052;
396
397// cl_mem_properties
398pub const CL_MEM_DEVICE_HANDLE_LIST_KHR: cl_ulong = 0x2051;
399pub const CL_MEM_DEVICE_HANDLE_LIST_END_KHR: cl_ulong = 0;
400
401// cl_command_type
402pub const CL_COMMAND_ACQUIRE_EXTERNAL_MEM_OBJECTS_KHR: cl_command_type = 0x2047;
403pub const CL_COMMAND_RELEASE_EXTERNAL_MEM_OBJECTS_KHR: cl_command_type = 0x2048;
404
405// cl_khr_external_memory_dma_buf
406
407// cl_external_memory_handle_type_khr
408pub const CL_EXTERNAL_MEMORY_HANDLE_DMA_BUF_KHR: cl_external_memory_handle_type_khr = 0x2067;
409
410// cl_khr_external_memory_dx
411
412// cl_external_memory_handle_type_khr
413pub const CL_EXTERNAL_MEMORY_HANDLE_D3D11_TEXTURE_KHR: cl_external_memory_handle_type_khr = 0x2063;
414pub const CL_EXTERNAL_MEMORY_HANDLE_D3D11_TEXTURE_KMT_KHR: cl_external_memory_handle_type_khr =
415    0x2064;
416pub const CL_EXTERNAL_MEMORY_HANDLE_D3D12_HEAP_KHR: cl_external_memory_handle_type_khr = 0x2065;
417pub const CL_EXTERNAL_MEMORY_HANDLE_D3D12_RESOURCE_KHR: cl_external_memory_handle_type_khr = 0x2066;
418
419// cl_khr_external_memory_opaque_fd
420
421// cl_external_memory_handle_type_khr
422pub const CL_EXTERNAL_MEMORY_HANDLE_OPAQUE_FD_KHR: cl_external_memory_handle_type_khr = 0x2060;
423
424// cl_khr_external_memory_win32
425
426// cl_external_memory_handle_type_khr
427pub const CL_EXTERNAL_MEMORY_HANDLE_OPAQUE_WIN32_KHR: cl_external_memory_handle_type_khr = 0x2061;
428pub const CL_EXTERNAL_MEMORY_HANDLE_OPAQUE_WIN32_KMT_KHR: cl_external_memory_handle_type_khr =
429    0x2062;
430
431// cl_khr_external_semaphore
432
433// cl_platform_info
434pub const CL_PLATFORM_SEMAPHORE_IMPORT_HANDLE_TYPES_KHR: cl_platform_info = 0x2037;
435pub const CL_PLATFORM_SEMAPHORE_EXPORT_HANDLE_TYPES_KHR: cl_platform_info = 0x2038;
436
437// cl_device_info
438pub const CL_DEVICE_SEMAPHORE_IMPORT_HANDLE_TYPES_KHR: cl_device_info = 0x204D;
439pub const CL_DEVICE_SEMAPHORE_EXPORT_HANDLE_TYPES_KHR: cl_device_info = 0x204E;
440
441// cl_semaphore_properties_khr
442pub const CL_SEMAPHORE_EXPORT_HANDLE_TYPES_KHR: cl_semaphore_properties_khr = 0x203F;
443pub const CL_SEMAPHORE_EXPORT_HANDLE_TYPES_LIST_END_KHR: cl_semaphore_properties_khr = 0;
444
445// cl_semaphore_info_khr
446pub const CL_SEMAPHORE_EXPORTABLE_KHR: u32 = 0x2054;
447
448// cl_khr_external_semaphore_dx_fence
449
450// cl_external_semaphore_handle_type_khr
451pub const CL_SEMAPHORE_HANDLE_D3D12_FENCE_KHR: cl_external_semaphore_handle_type_khr = 0x2059;
452
453// cl_khr_external_semaphore_opaque_fd
454pub const CL_SEMAPHORE_HANDLE_OPAQUE_FD_KHR: cl_external_semaphore_handle_type_khr = 0x2055;
455
456// cl_khr_external_semaphore_sync_fd
457pub const CL_SEMAPHORE_HANDLE_SYNC_FD_KHR: cl_external_semaphore_handle_type_khr = 0x2058;
458
459// cl_khr_external_semaphore_win32
460pub const CL_SEMAPHORE_HANDLE_OPAQUE_WIN32_KHR: cl_external_semaphore_handle_type_khr = 0x2056;
461pub const CL_SEMAPHORE_HANDLE_OPAQUE_WIN32_KMT_KHR: cl_external_semaphore_handle_type_khr = 0x2057;
462
463// cl_khr_semaphore
464// cl_semaphore_type
465pub const CL_SEMAPHORE_TYPE_BINARY_KHR: cl_semaphore_type_khr = 1;
466
467// cl_platform_info
468pub const CL_PLATFORM_SEMAPHORE_TYPES_KHR: cl_platform_info = 0x2036;
469
470// cl_device_info
471pub const CL_DEVICE_SEMAPHORE_TYPES_KHR: cl_device_info = 0x204C;
472
473// cl_semaphore_info_khr
474pub const CL_SEMAPHORE_CONTEXT_KHR: cl_semaphore_info_khr = 0x2039;
475pub const CL_SEMAPHORE_REFERENCE_COUNT_KHR: cl_semaphore_info_khr = 0x203A;
476pub const CL_SEMAPHORE_PROPERTIES_KHR: cl_semaphore_info_khr = 0x203B;
477pub const CL_SEMAPHORE_PAYLOAD_KHR: cl_semaphore_info_khr = 0x203C;
478
479// cl_semaphore_info_khr or cl_semaphore_properties_khr
480pub const CL_SEMAPHORE_TYPE_KHR: cl_semaphore_info_khr = 0x203D;
481pub const CL_SEMAPHORE_DEVICE_HANDLE_LIST_KHR: cl_semaphore_info_khr = 0x2053;
482pub const CL_SEMAPHORE_DEVICE_HANDLE_LIST_END_KHR: cl_semaphore_info_khr = 0;
483
484// cl_command_type
485pub const CL_COMMAND_SEMAPHORE_WAIT_KHR: cl_command_type = 0x2042;
486pub const CL_COMMAND_SEMAPHORE_SIGNAL_KHR: cl_command_type = 0x2043;
487
488// Error codes
489pub const CL_INVALID_SEMAPHORE_KHR: cl_int = -1142;
490
491// cl_arm_import_memory extension
492
493/// Default and valid properties name for `cl_arm_import_memory`
494pub const CL_IMPORT_TYPE_ARM: cl_import_properties_arm = 0x40B2;
495
496/// Host process memory type default value for `CL_IMPORT_TYPE_ARM` property
497pub const CL_IMPORT_TYPE_HOST_ARM: cl_import_properties_arm = 0x40B3;
498
499/// DMA BUF memory type value for `CL_IMPORT_TYPE_ARM` property
500pub const CL_IMPORT_TYPE_DMA_BUF_ARM: cl_import_properties_arm = 0x40B4;
501
502/// Protected memory property
503pub const CL_IMPORT_TYPE_PROTECTED_ARM: cl_import_properties_arm = 0x40B5;
504
505/// Android hardware buffer type value for `CL_IMPORT_TYPE_ARM` property
506pub const CL_IMPORT_TYPE_ANDROID_HARDWARE_BUFFER_ARM: cl_import_properties_arm = 0x41E2;
507
508/// Data consistency with host property
509pub const CL_IMPORT_DMA_BUF_DATA_CONSISTENCY_WITH_HOST_ARM: cl_import_properties_arm = 0x41E3;
510
511/// Index of plane in a multiplanar hardware buffer
512pub const CL_IMPORT_ANDROID_HARDWARE_BUFFER_PLANE_INDEX_ARM: cl_import_properties_arm = 0x41EF;
513
514/// Index of layer in a multilayer hardware buffer
515pub const CL_IMPORT_ANDROID_HARDWARE_BUFFER_LAYER_INDEX_ARM: cl_import_properties_arm = 0x41F0;
516
517/// Import memory size value to indicate a size for the whole buffer.
518pub const CL_IMPORT_MEMORY_WHOLE_ALLOCATION_ARM: cl_import_properties_arm =
519    cl_import_properties_arm::MAX;
520
521// cl_arm_shared_virtual_memory extension
522
523// Used by clGetDeviceInfo
524pub const CL_DEVICE_SVM_CAPABILITIES_ARM: cl_device_info = 0x40B6;
525
526// Used by clGetMemObjectInfo
527pub const CL_MEM_USES_SVM_POINTER_ARM: cl_mem_info = 0x40B7;
528
529// Used by clSetKernelExecInfoARM:
530pub const CL_KERNEL_EXEC_INFO_SVM_PTRS_ARM: cl_kernel_exec_info_arm = 0x40B8;
531pub const CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM_ARM: cl_kernel_exec_info_arm = 0x40B9;
532
533// To be used by clGetEventInfo:
534pub const CL_COMMAND_SVM_FREE_ARM: cl_event_info = 0x40BA;
535pub const CL_COMMAND_SVM_MEMCPY_ARM: cl_event_info = 0x40BB;
536pub const CL_COMMAND_SVM_MEMFILL_ARM: cl_event_info = 0x40BC;
537pub const CL_COMMAND_SVM_MAP_ARM: cl_event_info = 0x40BD;
538pub const CL_COMMAND_SVM_UNMAP_ARM: cl_event_info = 0x40BF;
539
540// Flag values returned by clGetDeviceInfo with CL_DEVICE_SVM_CAPABILITIES_ARM as the param_name.
541pub const CL_DEVICE_SVM_COARSE_GRAIN_BUFFER_ARM: cl_device_svm_capabilities_arm = 1 << 0;
542pub const CL_DEVICE_SVM_FINE_GRAIN_BUFFER_ARM: cl_device_svm_capabilities_arm = 1 << 1;
543pub const CL_DEVICE_SVM_FINE_GRAIN_SYSTEM_ARM: cl_device_svm_capabilities_arm = 1 << 2;
544pub const CL_DEVICE_SVM_ATOMICS_ARM: cl_device_svm_capabilities_arm = 1 << 3;
545
546// Flag values used by clSVMAllocARM:
547pub const CL_MEM_SVM_FINE_GRAIN_BUFFER_ARM: cl_svm_mem_flags_arm = 1 << 10;
548pub const CL_MEM_SVM_ATOMICS_ARM: cl_svm_mem_flags_arm = 1 << 11;
549
550// cl_arm_get_core_id extension
551pub const CL_DEVICE_COMPUTE_UNITS_BITFIELD_ARM: cl_device_info = 0x40BF;
552
553// cl_arm_job_slot_selection
554// cl_device_info
555pub const CL_DEVICE_JOB_SLOTS_ARM: cl_device_info = 0x41E0;
556// cl_command_queue_properties
557pub const CL_QUEUE_JOB_SLOT_ARM: cl_command_queue_properties = 0x41E1;
558
559// cl_arm_scheduling_controls
560
561// cl_device_info
562pub const CL_DEVICE_SCHEDULING_CONTROLS_CAPABILITIES_ARM: cl_device_info = 0x41E4;
563
564pub const CL_DEVICE_SCHEDULING_KERNEL_BATCHING_ARM: cl_device_scheduling_controls_capabilities_arm =
565    1 << 0;
566pub const CL_DEVICE_SCHEDULING_WORKGROUP_BATCH_SIZE_ARM:
567    cl_device_scheduling_controls_capabilities_arm = 1 << 1;
568pub const CL_DEVICE_SCHEDULING_WORKGROUP_BATCH_SIZE_MODIFIER_ARM:
569    cl_device_scheduling_controls_capabilities_arm = 1 << 2;
570pub const CL_DEVICE_SCHEDULING_DEFERRED_FLUSH_ARM: cl_device_scheduling_controls_capabilities_arm =
571    1 << 3;
572pub const CL_DEVICE_SCHEDULING_REGISTER_ALLOCATION_ARM:
573    cl_device_scheduling_controls_capabilities_arm = 1 << 4;
574pub const CL_DEVICE_SCHEDULING_WARP_THROTTLING_ARM: cl_device_scheduling_controls_capabilities_arm =
575    1 << 5;
576pub const CL_DEVICE_SCHEDULING_COMPUTE_UNIT_BATCH_QUEUE_SIZE_ARM:
577    cl_device_scheduling_controls_capabilities_arm = 1 << 6;
578pub const CL_DEVICE_SCHEDULING_COMPUTE_UNIT_LIMIT_ARM:
579    cl_device_scheduling_controls_capabilities_arm = 1 << 7;
580
581pub const CL_DEVICE_SUPPORTED_REGISTER_ALLOCATIONS_ARM: cl_device_info = 0x41EB;
582pub const CL_DEVICE_MAX_WARP_COUNT_ARM: cl_device_info = 0x41EA;
583
584pub const CL_KERNEL_MAX_WARP_COUNT_ARM: cl_kernel_info = 0x41E9;
585
586pub const CL_KERNEL_EXEC_INFO_WORKGROUP_BATCH_SIZE_ARM: cl_kernel_exec_info = 0x41E5;
587pub const CL_KERNEL_EXEC_INFO_WORKGROUP_BATCH_SIZE_MODIFIER_ARM: cl_kernel_exec_info = 0x41E6;
588pub const CL_KERNEL_EXEC_INFO_WARP_COUNT_LIMIT_ARM: cl_kernel_exec_info = 0x41E8;
589pub const CL_KERNEL_EXEC_INFO_COMPUTE_UNIT_MAX_QUEUED_BATCHES_ARM: cl_kernel_exec_info = 0x41F1;
590
591pub const CL_QUEUE_KERNEL_BATCHING_ARM: cl_queue_properties = 0x41E7;
592pub const CL_QUEUE_DEFERRED_FLUSH_ARM: cl_queue_properties = 0x41EC;
593pub const CL_QUEUE_COMPUTE_UNIT_LIMIT_ARM: cl_queue_properties = 0x41F3;
594
595// cl_arm_controlled_kernel_termination
596
597// Error code to indicate kernel terminated with failure
598pub const CL_COMMAND_TERMINATED_ITSELF_WITH_FAILURE_ARM: cl_int = -1108;
599
600// cl_device_info
601pub const CL_DEVICE_CONTROLLED_TERMINATION_CAPABILITIES_ARM: cl_device_info = 0x41EE;
602
603// Bit fields for controlled termination feature query
604pub const CL_DEVICE_CONTROLLED_TERMINATION_SUCCESS_ARM:
605    cl_device_controlled_termination_capabilities_arm = 1 << 0;
606pub const CL_DEVICE_CONTROLLED_TERMINATION_FAILURE_ARM:
607    cl_device_controlled_termination_capabilities_arm = 1 << 1;
608pub const CL_DEVICE_CONTROLLED_TERMINATION_QUERY_ARM:
609    cl_device_controlled_termination_capabilities_arm = 1 << 2;
610
611// cl_event_info
612pub const CL_EVENT_COMMAND_TERMINATION_REASON_ARM: cl_event_info = 0x41ED;
613
614// Values returned for event termination reason query
615pub const CL_COMMAND_TERMINATION_COMPLETION_ARM: cl_command_termination_reason_arm = 0;
616pub const CL_COMMAND_TERMINATION_CONTROLLED_SUCCESS_ARM: cl_command_termination_reason_arm = 1;
617pub const CL_COMMAND_TERMINATION_CONTROLLED_FAILURE_ARM: cl_command_termination_reason_arm = 2;
618pub const CL_COMMAND_TERMINATION_ERROR_ARM: cl_command_termination_reason_arm = 3;
619
620// cl_arm_protected_memory_allocation
621pub const CL_MEM_PROTECTED_ALLOC_ARM: cl_bitfield = 1 << 36;
622
623// cl_intel_exec_by_local_thread extension
624pub const CL_QUEUE_THREAD_LOCAL_EXEC_ENABLE_INTEL: cl_bitfield = 1 << 31;
625
626// cl_intel_device_attribute_query
627pub const CL_DEVICE_FEATURE_FLAG_DP4A_INTEL: cl_device_feature_capabilities_intel = 1 << 0;
628pub const CL_DEVICE_FEATURE_FLAG_DPAS_INTEL: cl_device_feature_capabilities_intel = 1 << 1;
629
630// cl_device_info
631pub const CL_DEVICE_IP_VERSION_INTEL: cl_device_info = 0x4250;
632pub const CL_DEVICE_ID_INTEL: cl_device_info = 0x4251;
633pub const CL_DEVICE_NUM_SLICES_INTEL: cl_device_info = 0x4252;
634pub const CL_DEVICE_NUM_SUB_SLICES_PER_SLICE_INTEL: cl_device_info = 0x4253;
635pub const CL_DEVICE_NUM_EUS_PER_SUB_SLICE_INTEL: cl_device_info = 0x4254;
636pub const CL_DEVICE_NUM_THREADS_PER_EU_INTEL: cl_device_info = 0x4255;
637pub const CL_DEVICE_FEATURE_CAPABILITIES_INTEL: cl_device_info = 0x4256;
638
639// cl_intel_device_partition_by_names extension
640
641pub const CL_DEVICE_PARTITION_BY_NAMES_INTEL: cl_device_info = 0x4052;
642pub const CL_PARTITION_BY_NAMES_LIST_END_INTEL: cl_int = -1;
643
644// cl_intel_accelerator extension
645// cl_intel_motion_estimation extension
646// cl_intel_advanced_motion_estimation extension
647
648// error codes
649pub const CL_INVALID_ACCELERATOR_INTEL: cl_int = -1094;
650pub const CL_INVALID_ACCELERATOR_TYPE_INTEL: cl_int = -1095;
651pub const CL_INVALID_ACCELERATOR_DESCRIPTOR_INTEL: cl_int = -1096;
652pub const CL_ACCELERATOR_TYPE_NOT_SUPPORTED_INTEL: cl_int = -1097;
653
654// cl_accelerator_type_intel
655pub const CL_ACCELERATOR_TYPE_MOTION_ESTIMATION_INTEL: cl_accelerator_type_intel = 0x0;
656
657// cl_accelerator_info_intel
658pub const CL_ACCELERATOR_DESCRIPTOR_INTEL: cl_accelerator_info_intel = 0x4090;
659pub const CL_ACCELERATOR_REFERENCE_COUNT_INTEL: cl_accelerator_info_intel = 0x4091;
660pub const CL_ACCELERATOR_CONTEXT_INTEL: cl_accelerator_info_intel = 0x4092;
661pub const CL_ACCELERATOR_TYPE_INTEL: cl_accelerator_info_intel = 0x4093;
662
663// cl_motion_detect_desc_intel flags
664pub const CL_ME_MB_TYPE_16x16_INTEL: cl_motion_detect_desc_intel = 0x0;
665pub const CL_ME_MB_TYPE_8x8_INTEL: cl_motion_detect_desc_intel = 0x1;
666pub const CL_ME_MB_TYPE_4x4_INTEL: cl_motion_detect_desc_intel = 0x2;
667
668pub const CL_ME_SUBPIXEL_MODE_INTEGER_INTEL: cl_motion_detect_desc_intel = 0x0;
669pub const CL_ME_SUBPIXEL_MODE_HPEL_INTEL: cl_motion_detect_desc_intel = 0x1;
670pub const CL_ME_SUBPIXEL_MODE_QPEL_INTEL: cl_motion_detect_desc_intel = 0x2;
671
672pub const CL_ME_SAD_ADJUST_MODE_NONE_INTEL: cl_motion_detect_desc_intel = 0x0;
673pub const CL_ME_SAD_ADJUST_MODE_HAAR_INTEL: cl_motion_detect_desc_intel = 0x1;
674
675pub const CL_ME_SEARCH_PATH_RADIUS_2_2_INTEL: cl_motion_detect_desc_intel = 0x0;
676pub const CL_ME_SEARCH_PATH_RADIUS_4_4_INTEL: cl_motion_detect_desc_intel = 0x1;
677pub const CL_ME_SEARCH_PATH_RADIUS_16_12_INTEL: cl_motion_detect_desc_intel = 0x5;
678
679pub const CL_ME_SKIP_BLOCK_TYPE_16x16_INTEL: cl_motion_detect_desc_intel = 0x0;
680pub const CL_ME_CHROMA_INTRA_PREDICT_ENABLED_INTEL: cl_motion_detect_desc_intel = 0x1;
681pub const CL_ME_LUMA_INTRA_PREDICT_ENABLED_INTEL: cl_motion_detect_desc_intel = 0x2;
682pub const CL_ME_SKIP_BLOCK_TYPE_8x8_INTEL: cl_motion_detect_desc_intel = 0x4;
683
684pub const CL_ME_FORWARD_INPUT_MODE_INTEL: cl_motion_detect_desc_intel = 0x1;
685pub const CL_ME_BACKWARD_INPUT_MODE_INTEL: cl_motion_detect_desc_intel = 0x2;
686pub const CL_ME_BIDIRECTION_INPUT_MODE_INTEL: cl_motion_detect_desc_intel = 0x3;
687
688pub const CL_ME_BIDIR_WEIGHT_QUARTER_INTEL: cl_motion_detect_desc_intel = 16;
689pub const CL_ME_BIDIR_WEIGHT_THIRD_INTEL: cl_motion_detect_desc_intel = 21;
690pub const CL_ME_BIDIR_WEIGHT_HALF_INTEL: cl_motion_detect_desc_intel = 32;
691pub const CL_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL: cl_motion_detect_desc_intel = 43;
692pub const CL_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL: cl_motion_detect_desc_intel = 48;
693
694pub const CL_ME_COST_PENALTY_NONE_INTEL: cl_motion_detect_desc_intel = 0x0;
695pub const CL_ME_COST_PENALTY_LOW_INTEL: cl_motion_detect_desc_intel = 0x1;
696pub const CL_ME_COST_PENALTY_NORMAL_INTEL: cl_motion_detect_desc_intel = 0x2;
697pub const CL_ME_COST_PENALTY_HIGH_INTEL: cl_motion_detect_desc_intel = 0x3;
698
699pub const CL_ME_COST_PRECISION_QPEL_INTEL: cl_motion_detect_desc_intel = 0x0;
700pub const CL_ME_COST_PRECISION_HPEL_INTEL: cl_motion_detect_desc_intel = 0x1;
701pub const CL_ME_COST_PRECISION_PEL_INTEL: cl_motion_detect_desc_intel = 0x2;
702pub const CL_ME_COST_PRECISION_DPEL_INTEL: cl_motion_detect_desc_intel = 0x3;
703
704pub const CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL: cl_motion_detect_desc_intel = 0x0;
705pub const CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL: cl_motion_detect_desc_intel = 0x1;
706pub const CL_ME_LUMA_PREDICTOR_MODE_DC_INTEL: cl_motion_detect_desc_intel = 0x2;
707pub const CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL: cl_motion_detect_desc_intel = 0x3;
708
709pub const CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL: cl_motion_detect_desc_intel = 0x4;
710pub const CL_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL: cl_motion_detect_desc_intel = 0x4;
711pub const CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL: cl_motion_detect_desc_intel = 0x5;
712pub const CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL: cl_motion_detect_desc_intel = 0x6;
713pub const CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL: cl_motion_detect_desc_intel = 0x7;
714pub const CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL: cl_motion_detect_desc_intel = 0x8;
715
716pub const CL_ME_CHROMA_PREDICTOR_MODE_DC_INTEL: cl_motion_detect_desc_intel = 0x0;
717pub const CL_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL: cl_motion_detect_desc_intel = 0x1;
718pub const CL_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL: cl_motion_detect_desc_intel = 0x2;
719pub const CL_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL: cl_motion_detect_desc_intel = 0x3;
720
721// cl_device_info
722pub const CL_DEVICE_ME_VERSION_INTEL: cl_device_info = 0x407E;
723
724pub const CL_ME_VERSION_LEGACY_INTEL: cl_uint = 0x0;
725pub const CL_ME_VERSION_ADVANCED_VER_1_INTEL: cl_uint = 0x1;
726pub const CL_ME_VERSION_ADVANCED_VER_2_INTEL: cl_uint = 0x2;
727
728// cl_intel_simultaneous_sharing extension
729pub const CL_DEVICE_SIMULTANEOUS_INTEROPS_INTEL: cl_uint = 0x4104;
730pub const CL_DEVICE_NUM_SIMULTANEOUS_INTEROPS_INTEL: cl_uint = 0x4105;
731
732// cl_intel_egl_image_yuv extension
733pub const CL_EGL_YUV_PLANE_INTEL: cl_uint = 0x4107;
734
735// cl_intel_packed_yuv extension
736pub const CL_YUYV_INTEL: cl_uint = 0x4076;
737pub const CL_UYVY_INTEL: cl_uint = 0x4077;
738pub const CL_YVYU_INTEL: cl_uint = 0x4078;
739pub const CL_VYUY_INTEL: cl_uint = 0x4079;
740
741// cl_intel_required_subgroup_size extension
742pub const CL_DEVICE_SUB_GROUP_SIZES_INTEL: cl_uint = 0x4108;
743pub const CL_KERNEL_SPILL_MEM_SIZE_INTEL: cl_uint = 0x4109;
744pub const CL_KERNEL_COMPILE_SUB_GROUP_SIZE_INTEL: cl_uint = 0x410A;
745
746// cl_intel_driver_diagnostics extension
747pub const CL_CONTEXT_SHOW_DIAGNOSTICS_INTEL: cl_uint = 0x4106;
748
749pub const CL_CONTEXT_DIAGNOSTICS_LEVEL_ALL_INTEL: cl_diagnostics_verbose_level = 0xff;
750pub const CL_CONTEXT_DIAGNOSTICS_LEVEL_GOOD_INTEL: cl_diagnostics_verbose_level = 1;
751pub const CL_CONTEXT_DIAGNOSTICS_LEVEL_BAD_INTEL: cl_diagnostics_verbose_level = 1 << 1;
752pub const CL_CONTEXT_DIAGNOSTICS_LEVEL_NEUTRAL_INTEL: cl_diagnostics_verbose_level = 1 << 2;
753
754// cl_intel_planar_yuv extension
755pub const CL_NV12_INTEL: cl_uint = 0x410E;
756
757pub const CL_MEM_NO_ACCESS_INTEL: cl_uint = 1 << 24;
758pub const CL_MEM_ACCESS_FLAGS_UNRESTRICTED_INTEL: cl_uint = 1 << 25;
759
760pub const CL_DEVICE_PLANAR_YUV_MAX_WIDTH_INTEL: cl_uint = 0x417E;
761pub const CL_DEVICE_PLANAR_YUV_MAX_HEIGHT_INTEL: cl_uint = 0x417F;
762
763// cl_intel_device_side_avc_motion_estimation extension
764
765pub const CL_DEVICE_AVC_ME_VERSION_INTEL: cl_uint = 0x410B;
766pub const CL_DEVICE_AVC_ME_SUPPORTS_TEXTURE_SAMPLER_USE_INTEL: cl_uint = 0x410C;
767pub const CL_DEVICE_AVC_ME_SUPPORTS_PREEMPTION_INTEL: cl_uint = 0x410D;
768
769pub const CL_AVC_ME_VERSION_0_INTEL: cl_intel_avc_motion_estimation = 0x0; // No support.
770pub const CL_AVC_ME_VERSION_1_INTEL: cl_intel_avc_motion_estimation = 0x1; // First supported version.
771
772pub const CL_AVC_ME_MAJOR_16x16_INTEL: cl_intel_avc_motion_estimation = 0x0;
773pub const CL_AVC_ME_MAJOR_16x8_INTEL: cl_intel_avc_motion_estimation = 0x1;
774pub const CL_AVC_ME_MAJOR_8x16_INTEL: cl_intel_avc_motion_estimation = 0x2;
775pub const CL_AVC_ME_MAJOR_8x8_INTEL: cl_intel_avc_motion_estimation = 0x3;
776
777pub const CL_AVC_ME_MINOR_8x8_INTEL: cl_intel_avc_motion_estimation = 0x0;
778pub const CL_AVC_ME_MINOR_8x4_INTEL: cl_intel_avc_motion_estimation = 0x1;
779pub const CL_AVC_ME_MINOR_4x8_INTEL: cl_intel_avc_motion_estimation = 0x2;
780pub const CL_AVC_ME_MINOR_4x4_INTEL: cl_intel_avc_motion_estimation = 0x3;
781
782pub const CL_AVC_ME_MAJOR_FORWARD_INTEL: cl_intel_avc_motion_estimation = 0x0;
783pub const CL_AVC_ME_MAJOR_BACKWARD_INTEL: cl_intel_avc_motion_estimation = 0x1;
784pub const CL_AVC_ME_MAJOR_BIDIRECTIONAL_INTEL: cl_intel_avc_motion_estimation = 0x2;
785
786pub const CL_AVC_ME_PARTITION_MASK_ALL_INTEL: cl_intel_avc_motion_estimation = 0x0;
787pub const CL_AVC_ME_PARTITION_MASK_16x16_INTEL: cl_intel_avc_motion_estimation = 0x7E;
788pub const CL_AVC_ME_PARTITION_MASK_16x8_INTEL: cl_intel_avc_motion_estimation = 0x7D;
789pub const CL_AVC_ME_PARTITION_MASK_8x16_INTEL: cl_intel_avc_motion_estimation = 0x7B;
790pub const CL_AVC_ME_PARTITION_MASK_8x8_INTEL: cl_intel_avc_motion_estimation = 0x77;
791pub const CL_AVC_ME_PARTITION_MASK_8x4_INTEL: cl_intel_avc_motion_estimation = 0x6F;
792pub const CL_AVC_ME_PARTITION_MASK_4x8_INTEL: cl_intel_avc_motion_estimation = 0x5F;
793pub const CL_AVC_ME_PARTITION_MASK_4x4_INTEL: cl_intel_avc_motion_estimation = 0x3F;
794
795pub const CL_AVC_ME_SEARCH_WINDOW_EXHAUSTIVE_INTEL: cl_intel_avc_motion_estimation = 0x0;
796pub const CL_AVC_ME_SEARCH_WINDOW_SMALL_INTEL: cl_intel_avc_motion_estimation = 0x1;
797pub const CL_AVC_ME_SEARCH_WINDOW_TINY_INTEL: cl_intel_avc_motion_estimation = 0x2;
798pub const CL_AVC_ME_SEARCH_WINDOW_EXTRA_TINY_INTEL: cl_intel_avc_motion_estimation = 0x3;
799pub const CL_AVC_ME_SEARCH_WINDOW_DIAMOND_INTEL: cl_intel_avc_motion_estimation = 0x4;
800pub const CL_AVC_ME_SEARCH_WINDOW_LARGE_DIAMOND_INTEL: cl_intel_avc_motion_estimation = 0x5;
801pub const CL_AVC_ME_SEARCH_WINDOW_RESERVED0_INTEL: cl_intel_avc_motion_estimation = 0x6;
802pub const CL_AVC_ME_SEARCH_WINDOW_RESERVED1_INTEL: cl_intel_avc_motion_estimation = 0x7;
803pub const CL_AVC_ME_SEARCH_WINDOW_CUSTOM_INTEL: cl_intel_avc_motion_estimation = 0x8;
804pub const CL_AVC_ME_SEARCH_WINDOW_16x12_RADIUS_INTEL: cl_intel_avc_motion_estimation = 0x9;
805pub const CL_AVC_ME_SEARCH_WINDOW_4x4_RADIUS_INTEL: cl_intel_avc_motion_estimation = 0x2;
806pub const CL_AVC_ME_SEARCH_WINDOW_2x2_RADIUS_INTEL: cl_intel_avc_motion_estimation = 0xa;
807
808pub const CL_AVC_ME_SAD_ADJUST_MODE_NONE_INTEL: cl_intel_avc_motion_estimation = 0x0;
809pub const CL_AVC_ME_SAD_ADJUST_MODE_HAAR_INTEL: cl_intel_avc_motion_estimation = 0x2;
810
811pub const CL_AVC_ME_SUBPIXEL_MODE_INTEGER_INTEL: cl_intel_avc_motion_estimation = 0x0;
812pub const CL_AVC_ME_SUBPIXEL_MODE_HPEL_INTEL: cl_intel_avc_motion_estimation = 0x1;
813pub const CL_AVC_ME_SUBPIXEL_MODE_QPEL_INTEL: cl_intel_avc_motion_estimation = 0x3;
814
815pub const CL_AVC_ME_COST_PRECISION_QPEL_INTEL: cl_intel_avc_motion_estimation = 0x0;
816pub const CL_AVC_ME_COST_PRECISION_HPEL_INTEL: cl_intel_avc_motion_estimation = 0x1;
817pub const CL_AVC_ME_COST_PRECISION_PEL_INTEL: cl_intel_avc_motion_estimation = 0x2;
818pub const CL_AVC_ME_COST_PRECISION_DPEL_INTEL: cl_intel_avc_motion_estimation = 0x3;
819
820pub const CL_AVC_ME_BIDIR_WEIGHT_QUARTER_INTEL: cl_intel_avc_motion_estimation = 0x10;
821pub const CL_AVC_ME_BIDIR_WEIGHT_THIRD_INTEL: cl_intel_avc_motion_estimation = 0x15;
822pub const CL_AVC_ME_BIDIR_WEIGHT_HALF_INTEL: cl_intel_avc_motion_estimation = 0x20;
823pub const CL_AVC_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL: cl_intel_avc_motion_estimation = 0x2B;
824pub const CL_AVC_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL: cl_intel_avc_motion_estimation = 0x30;
825
826pub const CL_AVC_ME_BORDER_REACHED_LEFT_INTEL: cl_intel_avc_motion_estimation = 0x0;
827pub const CL_AVC_ME_BORDER_REACHED_RIGHT_INTEL: cl_intel_avc_motion_estimation = 0x2;
828pub const CL_AVC_ME_BORDER_REACHED_TOP_INTEL: cl_intel_avc_motion_estimation = 0x4;
829pub const CL_AVC_ME_BORDER_REACHED_BOTTOM_INTEL: cl_intel_avc_motion_estimation = 0x8;
830
831pub const CL_AVC_ME_SKIP_BLOCK_PARTITION_16x16_INTEL: cl_intel_avc_motion_estimation = 0x0;
832pub const CL_AVC_ME_SKIP_BLOCK_PARTITION_8x8_INTEL: cl_intel_avc_motion_estimation = 0x4000;
833
834pub const CL_AVC_ME_SKIP_BLOCK_16x16_FORWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
835    0x1 << 24;
836pub const CL_AVC_ME_SKIP_BLOCK_16x16_BACKWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
837    0x2 << 24;
838pub const CL_AVC_ME_SKIP_BLOCK_16x16_DUAL_ENABLE_INTEL: cl_intel_avc_motion_estimation = 0x3 << 24;
839pub const CL_AVC_ME_SKIP_BLOCK_8x8_FORWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
840    0x55 << 24;
841pub const CL_AVC_ME_SKIP_BLOCK_8x8_BACKWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
842    0xAA << 24;
843pub const CL_AVC_ME_SKIP_BLOCK_8x8_DUAL_ENABLE_INTEL: cl_intel_avc_motion_estimation = 0xFF << 24;
844pub const CL_AVC_ME_SKIP_BLOCK_8x8_0_FORWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
845    0x1 << 24;
846pub const CL_AVC_ME_SKIP_BLOCK_8x8_0_BACKWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
847    0x2 << 24;
848pub const CL_AVC_ME_SKIP_BLOCK_8x8_1_FORWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
849    0x1 << 26;
850pub const CL_AVC_ME_SKIP_BLOCK_8x8_1_BACKWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
851    0x2 << 26;
852pub const CL_AVC_ME_SKIP_BLOCK_8x8_2_FORWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
853    0x1 << 28;
854pub const CL_AVC_ME_SKIP_BLOCK_8x8_2_BACKWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
855    0x2 << 28;
856pub const CL_AVC_ME_SKIP_BLOCK_8x8_3_FORWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
857    0x1 << 30;
858pub const CL_AVC_ME_SKIP_BLOCK_8x8_3_BACKWARD_ENABLE_INTEL: cl_intel_avc_motion_estimation =
859    0x2 << 30;
860
861pub const CL_AVC_ME_BLOCK_BASED_SKIP_4x4_INTEL: cl_intel_avc_motion_estimation = 0x00;
862pub const CL_AVC_ME_BLOCK_BASED_SKIP_8x8_INTEL: cl_intel_avc_motion_estimation = 0x80;
863
864pub const CL_AVC_ME_INTRA_16x16_INTEL: cl_intel_avc_motion_estimation = 0x0;
865pub const CL_AVC_ME_INTRA_8x8_INTEL: cl_intel_avc_motion_estimation = 0x1;
866pub const CL_AVC_ME_INTRA_4x4_INTEL: cl_intel_avc_motion_estimation = 0x2;
867
868pub const CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_16x16_INTEL: cl_intel_avc_motion_estimation = 0x6;
869pub const CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_8x8_INTEL: cl_intel_avc_motion_estimation = 0x5;
870pub const CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_4x4_INTEL: cl_intel_avc_motion_estimation = 0x3;
871
872pub const CL_AVC_ME_INTRA_NEIGHBOR_LEFT_MASK_ENABLE_INTEL: cl_intel_avc_motion_estimation = 0x60;
873pub const CL_AVC_ME_INTRA_NEIGHBOR_UPPER_MASK_ENABLE_INTEL: cl_intel_avc_motion_estimation = 0x10;
874pub const CL_AVC_ME_INTRA_NEIGHBOR_UPPER_RIGHT_MASK_ENABLE_INTEL: cl_intel_avc_motion_estimation =
875    0x8;
876pub const CL_AVC_ME_INTRA_NEIGHBOR_UPPER_LEFT_MASK_ENABLE_INTEL: cl_intel_avc_motion_estimation =
877    0x4;
878
879pub const CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL: cl_intel_avc_motion_estimation = 0x0;
880pub const CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL: cl_intel_avc_motion_estimation = 0x1;
881pub const CL_AVC_ME_LUMA_PREDICTOR_MODE_DC_INTEL: cl_intel_avc_motion_estimation = 0x2;
882pub const CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL: cl_intel_avc_motion_estimation =
883    0x3;
884pub const CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL: cl_intel_avc_motion_estimation =
885    0x4;
886pub const CL_AVC_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL: cl_intel_avc_motion_estimation = 0x4;
887pub const CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL: cl_intel_avc_motion_estimation = 0x5;
888pub const CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL: cl_intel_avc_motion_estimation = 0x6;
889pub const CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL: cl_intel_avc_motion_estimation = 0x7;
890pub const CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL: cl_intel_avc_motion_estimation = 0x8;
891pub const CL_AVC_ME_CHROMA_PREDICTOR_MODE_DC_INTEL: cl_intel_avc_motion_estimation = 0x0;
892pub const CL_AVC_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL: cl_intel_avc_motion_estimation = 0x1;
893pub const CL_AVC_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL: cl_intel_avc_motion_estimation = 0x2;
894pub const CL_AVC_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL: cl_intel_avc_motion_estimation = 0x3;
895
896pub const CL_AVC_ME_FRAME_FORWARD_INTEL: cl_intel_avc_motion_estimation = 0x1;
897pub const CL_AVC_ME_FRAME_BACKWARD_INTEL: cl_intel_avc_motion_estimation = 0x2;
898pub const CL_AVC_ME_FRAME_DUAL_INTEL: cl_intel_avc_motion_estimation = 0x3;
899
900pub const CL_AVC_ME_SLICE_TYPE_PRED_INTEL: cl_intel_avc_motion_estimation = 0x0;
901pub const CL_AVC_ME_SLICE_TYPE_BPRED_INTEL: cl_intel_avc_motion_estimation = 0x1;
902pub const CL_AVC_ME_SLICE_TYPE_INTRA_INTEL: cl_intel_avc_motion_estimation = 0x2;
903
904pub const CL_AVC_ME_INTERLACED_SCAN_TOP_FIELD_INTEL: cl_intel_avc_motion_estimation = 0x0;
905pub const CL_AVC_ME_INTERLACED_SCAN_BOTTOM_FIELD_INTEL: cl_intel_avc_motion_estimation = 0x1;
906
907// cl_intel_unified_shared_memory extension
908
909// cl_device_info
910pub const CL_DEVICE_HOST_MEM_CAPABILITIES_INTEL: cl_device_info = 0x4190;
911pub const CL_DEVICE_DEVICE_MEM_CAPABILITIES_INTEL: cl_device_info = 0x4191;
912pub const CL_DEVICE_SINGLE_DEVICE_SHARED_MEM_CAPABILITIES_INTEL: cl_device_info = 0x4192;
913pub const CL_DEVICE_CROSS_DEVICE_SHARED_MEM_CAPABILITIES_INTEL: cl_device_info = 0x4193;
914pub const CL_DEVICE_SHARED_SYSTEM_MEM_CAPABILITIES_INTEL: cl_device_info = 0x4194;
915
916// cl_device_unified_shared_memory_capabilities_intel - bitfield
917pub const CL_UNIFIED_SHARED_MEMORY_ACCESS_INTEL:
918    cl_device_unified_shared_memory_capabilities_intel = 1 << 0;
919pub const CL_UNIFIED_SHARED_MEMORY_ATOMIC_ACCESS_INTEL:
920    cl_device_unified_shared_memory_capabilities_intel = 1 << 1;
921pub const CL_UNIFIED_SHARED_MEMORY_CONCURRENT_ACCESS_INTEL:
922    cl_device_unified_shared_memory_capabilities_intel = 1 << 2;
923pub const CL_UNIFIED_SHARED_MEMORY_CONCURRENT_ATOMIC_ACCESS_INTEL:
924    cl_device_unified_shared_memory_capabilities_intel = 1 << 3;
925
926pub const CL_MEM_ALLOC_FLAGS_INTEL: cl_mem_properties_intel = 0x4195;
927
928// cl_mem_alloc_flags_intel - bitfield
929pub const CL_MEM_ALLOC_WRITE_COMBINED_INTEL: cl_mem_alloc_flags_intel = 1 << 0;
930pub const CL_MEM_ALLOC_INITIAL_PLACEMENT_DEVICE_INTEL: cl_mem_alloc_flags_intel = 1 << 1;
931pub const CL_MEM_ALLOC_INITIAL_PLACEMENT_HOST_INTEL: cl_mem_alloc_flags_intel = 1 << 2;
932
933// cl_mem_alloc_info_intel
934pub const CL_MEM_ALLOC_TYPE_INTEL: cl_mem_info_intel = 0x419A;
935pub const CL_MEM_ALLOC_BASE_PTR_INTEL: cl_mem_info_intel = 0x419B;
936pub const CL_MEM_ALLOC_SIZE_INTEL: cl_mem_info_intel = 0x419C;
937pub const CL_MEM_ALLOC_DEVICE_INTEL: cl_mem_info_intel = 0x419D;
938
939// cl_unified_shared_memory_type_intel
940pub const CL_MEM_TYPE_UNKNOWN_INTEL: cl_unified_shared_memory_type_intel = 0x4196;
941pub const CL_MEM_TYPE_HOST_INTEL: cl_unified_shared_memory_type_intel = 0x4197;
942pub const CL_MEM_TYPE_DEVICE_INTEL: cl_unified_shared_memory_type_intel = 0x4198;
943pub const CL_MEM_TYPE_SHARED_INTEL: cl_unified_shared_memory_type_intel = 0x4199;
944
945// cl_kernel_exec_info
946pub const CL_KERNEL_EXEC_INFO_INDIRECT_HOST_ACCESS_INTEL: cl_kernel_exec_info = 0x4200;
947pub const CL_KERNEL_EXEC_INFO_INDIRECT_DEVICE_ACCESS_INTEL: cl_kernel_exec_info = 0x4201;
948pub const CL_KERNEL_EXEC_INFO_INDIRECT_SHARED_ACCESS_INTEL: cl_kernel_exec_info = 0x4202;
949pub const CL_KERNEL_EXEC_INFO_USM_PTRS_INTEL: cl_kernel_exec_info = 0x4203;
950
951// cl_command_type
952pub const CL_COMMAND_MEMFILL_INTEL: cl_command_type = 0x4204;
953pub const CL_COMMAND_MEMCPY_INTEL: cl_command_type = 0x4205;
954pub const CL_COMMAND_MIGRATEMEM_INTEL: cl_command_type = 0x4206;
955pub const CL_COMMAND_MEMADVISE_INTEL: cl_command_type = 0x4207;
956
957// cl_intel_mem_alloc_buffer_location
958
959// cl_mem_properties_intel
960pub const CL_MEM_ALLOC_BUFFER_LOCATION_INTEL: cl_mem_properties_intel = 0x419E;
961
962// cl_intel_program_scope_host_pipe
963
964// clGetEventInfo response when param_name is CL_EVENT_COMMAND_TYPE
965pub const CL_COMMAND_READ_HOST_PIPE_INTEL: cl_uint = 0x4214;
966pub const CL_COMMAND_WRITE_HOST_PIPE_INTEL: cl_uint = 0x4215;
967
968// clGetProgramInfo param_name
969pub const CL_PROGRAM_NUM_HOST_PIPES_INTEL: cl_program_info = 0x4216;
970pub const CL_PROGRAM_HOST_PIPE_NAMES_INTEL: cl_program_info = 0x4217;
971
972// cl_intel_mem_channel_property extension
973pub const CL_MEM_CHANNEL_INTEL: cl_uint = 0x4213;
974
975// cl_intel_mem_force_host_memory
976
977// cl_mem_flags
978pub const CL_MEM_FORCE_HOST_MEMORY_INTEL: cl_mem_flags = 1 << 20;
979
980// cl_intel_command_queue_families
981
982pub const CL_QUEUE_FAMILY_MAX_NAME_SIZE_INTEL: size_t = 64;
983
984// cl_device_info
985pub const CL_DEVICE_QUEUE_FAMILY_PROPERTIES_INTEL: cl_device_info = 0x418B;
986
987// cl_queue_properties
988pub const CL_QUEUE_FAMILY_INTEL: cl_queue_properties = 0x418C;
989pub const CL_QUEUE_INDEX_INTEL: cl_queue_properties = 0x418D;
990
991// cl_command_queue_capabilities_intel
992pub const CL_QUEUE_DEFAULT_CAPABILITIES_INTEL: cl_command_queue_capabilities_intel = 0;
993pub const CL_QUEUE_CAPABILITY_CREATE_SINGLE_QUEUE_EVENTS_INTEL:
994    cl_command_queue_capabilities_intel = 1 << 0;
995pub const CL_QUEUE_CAPABILITY_CREATE_CROSS_QUEUE_EVENTS_INTEL: cl_command_queue_capabilities_intel =
996    1 << 1;
997pub const CL_QUEUE_CAPABILITY_SINGLE_QUEUE_EVENT_WAIT_LIST_INTEL:
998    cl_command_queue_capabilities_intel = 1 << 2;
999pub const CL_QUEUE_CAPABILITY_CROSS_QUEUE_EVENT_WAIT_LIST_INTEL:
1000    cl_command_queue_capabilities_intel = 1 << 3;
1001pub const CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_INTEL: cl_command_queue_capabilities_intel = 1 << 8;
1002pub const CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_RECT_INTEL: cl_command_queue_capabilities_intel =
1003    1 << 9;
1004pub const CL_QUEUE_CAPABILITY_MAP_BUFFER_INTEL: cl_command_queue_capabilities_intel = 1 << 10;
1005pub const CL_QUEUE_CAPABILITY_FILL_BUFFER_INTEL: cl_command_queue_capabilities_intel = 1 << 11;
1006pub const CL_QUEUE_CAPABILITY_TRANSFER_IMAGE_INTEL: cl_command_queue_capabilities_intel = 1 << 12;
1007pub const CL_QUEUE_CAPABILITY_MAP_IMAGE_INTEL: cl_command_queue_capabilities_intel = 1 << 13;
1008pub const CL_QUEUE_CAPABILITY_FILL_IMAGE_INTEL: cl_command_queue_capabilities_intel = 1 << 14;
1009pub const CL_QUEUE_CAPABILITY_TRANSFER_BUFFER_IMAGE_INTEL: cl_command_queue_capabilities_intel =
1010    1 << 15;
1011pub const CL_QUEUE_CAPABILITY_TRANSFER_IMAGE_BUFFER_INTEL: cl_command_queue_capabilities_intel =
1012    1 << 16;
1013pub const CL_QUEUE_CAPABILITY_MARKER_INTEL: cl_command_queue_capabilities_intel = 1 << 24;
1014pub const CL_QUEUE_CAPABILITY_BARRIER_INTEL: cl_command_queue_capabilities_intel = 1 << 25;
1015pub const CL_QUEUE_CAPABILITY_KERNEL_INTEL: cl_command_queue_capabilities_intel = 1 << 26;
1016
1017// cl_intel_queue_no_sync_operations
1018pub const CL_QUEUE_NO_SYNC_OPERATIONS_INTEL: cl_command_queue_properties = 1 << 29;
1019
1020// cl_ext_image_requirements_info
1021pub const CL_IMAGE_REQUIREMENTS_ROW_PITCH_ALIGNMENT_EXT: cl_image_requirements_info_ext = 0x1290;
1022pub const CL_IMAGE_REQUIREMENTS_BASE_ADDRESS_ALIGNMENT_EXT: cl_image_requirements_info_ext = 0x1292;
1023pub const CL_IMAGE_REQUIREMENTS_SIZE_EXT: cl_image_requirements_info_ext = 0x12B2;
1024pub const CL_IMAGE_REQUIREMENTS_MAX_WIDTH_EXT: cl_image_requirements_info_ext = 0x12B3;
1025pub const CL_IMAGE_REQUIREMENTS_MAX_HEIGHT_EXT: cl_image_requirements_info_ext = 0x12B4;
1026pub const CL_IMAGE_REQUIREMENTS_MAX_DEPTH_EXT: cl_image_requirements_info_ext = 0x12B5;
1027pub const CL_IMAGE_REQUIREMENTS_MAX_ARRAY_SIZE_EXT: cl_image_requirements_info_ext = 0x12B6;
1028
1029// cl_ext_image_from_buffer
1030pub const CL_IMAGE_REQUIREMENTS_SLICE_PITCH_ALIGNMENT_EXT: cl_image_requirements_info_ext = 0x1291;
1031
1032// cl_ext_image_raw10_raw12
1033pub const CL_UNSIGNED_INT_RAW10_EXT: cl_uint = 0x10E3;
1034pub const CL_UNSIGNED_INT_RAW12_EXT: cl_uint = 0x10E4;
opencl_dynamic_sys/constants/cl_ext.rs

opencl_dynamic_sys/constants/
cl_ext.rs
