Crate open_vaf

A frontend for Verilog AMS that returns an Tree based IR as its end result

let source_map_allocator = Bump::new();
 let source_map = ast
    .parse_from_and_print_errors(Path::new("<File>"), &source_map_allocator, true)?;
 let hir = ast
    .lower_and_print_errors(source_map, true)?;
 let mir = hir
    .lower_and_print_errors(source_map, true)?;

Re-exports

pub use bumpalo;

pub use ahash;

pub use rustc_hash;

Modules

analysis

ast

ast_lowering

This module is responsible for lowering an Ast to an Hir

cfg

data_structures

hir

ir

mir

parser

symbol

symbol_table

util

Macros

impl_id_type

Provides the implementation which allows the data of an IR to be accessed using an ID type generated using the id_type! macro.

resolve

A macro that hides the boiler plate required for name resolution using the resolver struct It is defined in the name_resolution module but due to limitations of rustdoc can’t be shown there in the documentation If $name wasn’t found or doesn’t math any SymbolDeclaration::$declaration the appropriate errors are added to $self.errors and execution continuous after the macro

resolve_hierarchical

A macro that hides the boiler plate required for name resolution of hieraichal Identifiers using the resolver struct It is defined in the name_resolution module but due to limitations of rustdoc can’t be shown there in the documentation
If $name wasn’t found or doesn’t math any SymbolDeclaration::$declaration the appropriate errors are added to $self.errors and execution continuous after the macro

Structs

SourceMap

Span

StringLiteral