Crate oak_verilog 

🛠️ Developer Guide

Verilog support for the Oak language framework.

This directory contains the core logic implementation of the project. Below are instructions for a quick start.

🚦 Quick Start

Core API Usage

// Example: Basic calling workflow
fn main() {
    // 1. Initialization
    // 2. Execute core logic
    // 3. Handle returned results
}

🔍 Module Description

• lib.rs: Exports public interfaces and core traits.
• parser/ (if exists): Implements specific syntax parsing logic.
• ast/ (if exists): Defines the syntax tree structure.

🏗️ Architecture Design

The project follows the general architectural specifications of the Oak ecosystem, emphasizing:

1. Immutability: Uses the Green/Red Tree structure to ensure efficient sharing of syntax trees.
2. Fault Tolerance: Core logic is highly inclusive of erroneous input.
3. Scalability: Convenient for downstream tools to perform secondary development.

Re-exports

pub use crate::language::VerilogLanguage;

pub use crate::lexer::VerilogLexer;

pub use crate::parser::VerilogParser;

pub use crate::lexer::token_type::VerilogKind as TokenType;

pub use crate::parser::element_type::VerilogElementType as ElementType;

Modules

ast

AST module. AST module.

builder

Builder module.

language

Language module.

lexer

Lexer module.

parser

Parser module.