nvml_wrapper/bitmasks/
event.rs

1use crate::ffi::bindings::*;
2use bitflags::bitflags;
3#[cfg(feature = "serde")]
4use serde_derive::{Deserialize, Serialize};
5
6bitflags! {
7    /**
8    Event types that you can request to be notified about.
9
10    Types can be combined with the Bitwise Or operator `|` when passed to
11    `Device.register_events()`.
12    */
13    // Checked against local
14    #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
15    #[derive(Debug, Copy, Clone, Eq, PartialEq, Hash)]
16    pub struct EventTypes: u64 {
17        /// A corrected texture memory error is not an ECC error, so it does not
18        /// generate a single bit event.
19        const SINGLE_BIT_ECC_ERROR  = nvmlEventTypeSingleBitEccError as u64;
20        /// An uncorrected texture memory error is not an ECC error, so it does not
21        /// generate a double bit event.
22        const DOUBLE_BIT_ECC_ERROR  = nvmlEventTypeDoubleBitEccError as u64;
23        /**
24        Power state change event.
25
26        On the Fermi architecture, a PState change is an indicator that the GPU
27        is throttling down due to no work being executed on the GPU, power
28        capping, or thermal capping. In a typical situation, Fermi-based
29        GPUs should stay in performance state zero for the duration of the
30        execution of a compute process.
31        */
32        const PSTATE_CHANGE         = nvmlEventTypePState as u64;
33        const CRITICAL_XID_ERROR    = nvmlEventTypeXidCriticalError as u64;
34        /// Only supports the Kepler architecture.
35        const CLOCK_CHANGE          = nvmlEventTypeClock as u64;
36        /// Power source change event (battery vs. AC power).
37        const POWER_SOURCE_CHANGE   = nvmlEventTypePowerSourceChange as u64;
38        /// MIG configuration changes.
39        const MIG_CONFIG_CHANGE     = nvmlEventMigConfigChange as u64;
40    }
41}
nvml_wrapper/bitmasks/event.rs

nvml_wrapper/bitmasks/
event.rs
