nvml_wrapper/enum_wrappers/
device.rs

1use crate::error::NvmlError;
2use crate::ffi::bindings::*;
3#[cfg(feature = "serde")]
4use serde_derive::{Deserialize, Serialize};
5use wrapcenum_derive::EnumWrapper;
6
7/// API types that allow changes to default permission restrictions.
8// Checked against local
9#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
10#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
11#[wrap(c_enum = "nvmlRestrictedAPI_enum")]
12pub enum Api {
13    /**
14    APIs that change application clocks.
15
16    Applicable methods on `Device`: `.set_applications_clocks()`,
17    `.reset_applications_clocks()`
18    */
19    #[wrap(c_variant = "NVML_RESTRICTED_API_SET_APPLICATION_CLOCKS")]
20    ApplicationClocks,
21    /// APIs that enable/disable auto boosted clocks.
22    ///
23    /// Applicable methods on `Device`: `.set_auto_boosted_clocks()`
24    #[wrap(c_variant = "NVML_RESTRICTED_API_SET_AUTO_BOOSTED_CLOCKS")]
25    AutoBoostedClocks,
26}
27
28/// Clock types. All speeds are in MHz.
29// Checked against local
30#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
31#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
32#[wrap(c_enum = "nvmlClockType_enum")]
33pub enum Clock {
34    /// Graphics clock domain.
35    #[wrap(c_variant = "NVML_CLOCK_GRAPHICS")]
36    Graphics,
37    /// SM (Streaming Multiprocessor) clock domain.
38    ///
39    /// What AMD calls a CU (Compute Unit) can be compared to this.
40    #[wrap(c_variant = "NVML_CLOCK_SM")]
41    SM,
42    /// Memory clock domain.
43    #[wrap(c_variant = "NVML_CLOCK_MEM")]
44    Memory,
45    /// Video encoder/decoder clock domain.
46    #[wrap(c_variant = "NVML_CLOCK_VIDEO")]
47    Video,
48}
49
50/// These are used in combo with `Clock` to specify a single clock value.
51// Checked against local
52#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
53#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
54#[wrap(c_enum = "nvmlClockId_enum")]
55pub enum ClockId {
56    /// Current actual clock value.
57    #[wrap(c_variant = "NVML_CLOCK_ID_CURRENT")]
58    Current,
59    /// Target application clock.
60    #[wrap(c_variant = "NVML_CLOCK_ID_APP_CLOCK_TARGET")]
61    TargetAppClock,
62    /// Default application clock target.
63    #[wrap(c_variant = "NVML_CLOCK_ID_APP_CLOCK_DEFAULT")]
64    DefaultAppClock,
65    /// OEM-defined maximum clock rate.
66    #[wrap(c_variant = "NVML_CLOCK_ID_CUSTOMER_BOOST_MAX")]
67    CustomerMaxBoost,
68}
69
70/// GPU brand.
71// Checked against local
72#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
73#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
74#[wrap(c_enum = "nvmlBrandType_enum")]
75pub enum Brand {
76    #[wrap(c_variant = "NVML_BRAND_UNKNOWN")]
77    Unknown,
78    /// Targeted at workstations.
79    #[wrap(c_variant = "NVML_BRAND_QUADRO")]
80    Quadro,
81    /// Targeted at high-end compute.
82    #[wrap(c_variant = "NVML_BRAND_TESLA")]
83    Tesla,
84    /// NVIDIA's multi-display cards.
85    #[wrap(c_variant = "NVML_BRAND_NVS")]
86    NVS,
87    /// Targeted at virtualization (vGPUs).
88    ///
89    /// Deprecated from API reporting, still here for backwards compatibility.
90    #[wrap(c_variant = "NVML_BRAND_GRID")]
91    GRID,
92    /// Targeted at gaming.
93    #[wrap(c_variant = "NVML_BRAND_GEFORCE")]
94    GeForce,
95    /// Targeted at... people who don't quite need quadros?
96    #[wrap(c_variant = "NVML_BRAND_TITAN")]
97    Titan,
98    /// Targeted at virtualized apps.
99    #[wrap(c_variant = "NVML_BRAND_NVIDIA_VAPPS")]
100    VApps,
101    /// Targeted at virtualized pcs.
102    #[wrap(c_variant = "NVML_BRAND_NVIDIA_VPC")]
103    VPC,
104    /// Targeted at virtualized servers.
105    #[wrap(c_variant = "NVML_BRAND_NVIDIA_VCS")]
106    VCS,
107    /// Targeted at virtualized work stations.
108    #[wrap(c_variant = "NVML_BRAND_NVIDIA_VWS")]
109    VWS,
110    /// Targeted at cloud gaming servers.
111    #[wrap(c_variant = "NVML_BRAND_NVIDIA_CLOUD_GAMING")]
112    CloudGaming,
113    /// Deprecated from API reporting, still here for backwards compatibility.
114    /// Symlinks to [`Brand::CloudGaming`].
115    #[wrap(c_variant = "NVML_BRAND_NVIDIA_VGAMING")]
116    VGaming,
117    /// Targeted at Quadro RTX cards.
118    #[wrap(c_variant = "NVML_BRAND_QUADRO_RTX")]
119    QuadroRTX,
120    /// Targeted at RTX cards.
121    #[wrap(c_variant = "NVML_BRAND_NVIDIA_RTX")]
122    NvidiaRTX,
123    /// Nvidia
124    #[wrap(c_variant = "NVML_BRAND_NVIDIA")]
125    Nvidia,
126    /// Targeted at gaming RTX cards.
127    #[wrap(c_variant = "NVML_BRAND_GEFORCE_RTX")]
128    GeForceRTX,
129    /// Targeted at Titan RTX cards.
130    #[wrap(c_variant = "NVML_BRAND_TITAN_RTX")]
131    TitanRTX,
132}
133
134/**
135Represents type of a bridge chip.
136
137NVIDIA does not provide docs (in the code, that is) explaining what each chip
138type is, so you're on your own there.
139*/
140// Checked against local
141#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
142#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
143#[wrap(c_enum = "nvmlBridgeChipType_enum")]
144pub enum BridgeChip {
145    #[wrap(c_variant = "NVML_BRIDGE_CHIP_PLX")]
146    PLX,
147    #[wrap(c_variant = "NVML_BRIDGE_CHIP_BRO4")]
148    BRO4,
149}
150
151/// Memory error types.
152// Checked against local
153#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
154#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
155#[wrap(c_enum = "nvmlMemoryErrorType_enum")]
156pub enum MemoryError {
157    /**
158    A memory error that was corrected.
159
160    ECC error: single bit error.
161    Texture memory: error fixed by a resend.
162    */
163    #[wrap(c_variant = "NVML_MEMORY_ERROR_TYPE_CORRECTED")]
164    Corrected,
165    /**
166    A memory error that was not corrected.
167
168    ECC error: double bit error.
169    Texture memory: error occurred and resend failed.
170    */
171    #[wrap(c_variant = "NVML_MEMORY_ERROR_TYPE_UNCORRECTED")]
172    Uncorrected,
173}
174
175/**
176ECC counter types.
177
178Note: Volatile counts are reset each time the driver loads. On Windows this is
179once per boot. On Linux this can be more frequent; the driver unloads when no
180active clients exist. If persistence mode is enabled or there is always a
181driver client active (such as X11), then Linux also sees per-boot behavior.
182If not, volatile counts are reset each time a compute app is run.
183*/
184// Checked against local
185#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
186#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
187#[wrap(c_enum = "nvmlEccCounterType_enum")]
188pub enum EccCounter {
189    /// Volatile counts are reset each time the driver loads.
190    #[wrap(c_variant = "NVML_VOLATILE_ECC")]
191    Volatile,
192    /// Aggregate counts persist across reboots (i.e. for the lifetime of the
193    /// device).
194    #[wrap(c_variant = "NVML_AGGREGATE_ECC")]
195    Aggregate,
196}
197
198/// Memory locations. See `Device.memory_error_counter()`.
199// Checked against local
200#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
201#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
202#[wrap(c_enum = "nvmlMemoryLocation_enum")]
203pub enum MemoryLocation {
204    /// GPU L1 cache.
205    #[wrap(c_variant = "NVML_MEMORY_LOCATION_L1_CACHE")]
206    L1Cache,
207    /// GPU L2 cache.
208    #[wrap(c_variant = "NVML_MEMORY_LOCATION_L2_CACHE")]
209    L2Cache,
210    /// GPU device memory.
211    #[wrap(c_variant = "NVML_MEMORY_LOCATION_DEVICE_MEMORY")]
212    Device,
213    /// GPU register file.
214    #[wrap(c_variant = "NVML_MEMORY_LOCATION_REGISTER_FILE")]
215    RegisterFile,
216    /// GPU texture memory.
217    #[wrap(c_variant = "NVML_MEMORY_LOCATION_TEXTURE_MEMORY")]
218    Texture,
219    /// Shared memory.
220    #[wrap(c_variant = "NVML_MEMORY_LOCATION_TEXTURE_SHM")]
221    Shared,
222    #[wrap(c_variant = "NVML_MEMORY_LOCATION_CBU")]
223    Cbu,
224    /// SRAM present on Turing and above.
225    #[wrap(c_variant = "NVML_MEMORY_LOCATION_SRAM")]
226    SRAM,
227}
228
229/// Driver models, Windows only.
230// Checked against local
231#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
232#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
233#[wrap(c_enum = "nvmlDriverModel_enum")]
234#[cfg(target_os = "windows")]
235pub enum DriverModel {
236    /// GPU treated as a display device.
237    #[wrap(c_variant = "NVML_DRIVER_WDDM")]
238    WDDM,
239    /// (TCC model) GPU treated as a generic device (recommended).
240    #[wrap(c_variant = "NVML_DRIVER_WDM")]
241    WDM,
242}
243
244/**
245GPU operation mode.
246
247Allows for the reduction of power usage and optimization of GPU throughput
248by disabling GPU features. Each mode is designed to meet specific needs.
249*/
250// Checked against local
251#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
252#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
253#[wrap(c_enum = "nvmlGom_enum")]
254pub enum OperationMode {
255    /// Everything is enabled and running at full speed.
256    #[wrap(c_variant = "NVML_GOM_ALL_ON")]
257    AllOn,
258    /// Designed for running only compute tasks; disables graphics operations.
259    #[wrap(c_variant = "NVML_GOM_COMPUTE")]
260    Compute,
261    /// Designed for running graphics applications that don't require high
262    /// bandwidth double precision.
263    #[wrap(c_variant = "NVML_GOM_LOW_DP")]
264    LowDP,
265}
266
267/// Available infoROM objects.
268// Checked against local
269#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
270#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
271#[wrap(c_enum = "nvmlInforomObject_enum")]
272pub enum InfoRom {
273    /// An object defined by OEM.
274    #[wrap(c_variant = "NVML_INFOROM_OEM")]
275    OEM,
276    /// The ECC object determining the level of ECC support.
277    #[wrap(c_variant = "NVML_INFOROM_ECC")]
278    ECC,
279    /// The power management object.
280    #[wrap(c_variant = "NVML_INFOROM_POWER")]
281    Power,
282}
283
284/// Represents the queryable PCIe utilization counters (in bytes). 1KB
285/// granularity.
286// Checked against local
287#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
288#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
289#[wrap(c_enum = "nvmlPcieUtilCounter_enum")]
290pub enum PcieUtilCounter {
291    #[wrap(c_variant = "NVML_PCIE_UTIL_TX_BYTES")]
292    Send,
293    #[wrap(c_variant = "NVML_PCIE_UTIL_RX_BYTES")]
294    Receive,
295}
296
297/**
298Allowed performance states.
299
300```text
301Value    Performance
302  0       (highest)
303 ...
304 15       (lowest)
305```
306*/
307// Checked against local
308#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
309#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
310#[wrap(c_enum = "nvmlPStates_enum")]
311pub enum PerformanceState {
312    /// Maximum performance.
313    #[wrap(c_variant = "NVML_PSTATE_0")]
314    Zero,
315    #[wrap(c_variant = "NVML_PSTATE_1")]
316    One,
317    #[wrap(c_variant = "NVML_PSTATE_2")]
318    Two,
319    #[wrap(c_variant = "NVML_PSTATE_3")]
320    Three,
321    #[wrap(c_variant = "NVML_PSTATE_4")]
322    Four,
323    #[wrap(c_variant = "NVML_PSTATE_5")]
324    Five,
325    #[wrap(c_variant = "NVML_PSTATE_6")]
326    Six,
327    #[wrap(c_variant = "NVML_PSTATE_7")]
328    Seven,
329    #[wrap(c_variant = "NVML_PSTATE_8")]
330    Eight,
331    #[wrap(c_variant = "NVML_PSTATE_9")]
332    Nine,
333    #[wrap(c_variant = "NVML_PSTATE_10")]
334    Ten,
335    #[wrap(c_variant = "NVML_PSTATE_11")]
336    Eleven,
337    #[wrap(c_variant = "NVML_PSTATE_12")]
338    Twelve,
339    #[wrap(c_variant = "NVML_PSTATE_13")]
340    Thirteen,
341    #[wrap(c_variant = "NVML_PSTATE_14")]
342    Fourteen,
343    /// Minimum peformance.
344    #[wrap(c_variant = "NVML_PSTATE_15")]
345    Fifteen,
346    /// Unknown performance state.
347    #[wrap(c_variant = "NVML_PSTATE_UNKNOWN")]
348    Unknown,
349}
350
351/// Causes for page retirement.
352// Checked against local
353#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
354#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
355#[wrap(c_enum = "nvmlPageRetirementCause_enum")]
356pub enum RetirementCause {
357    /// Page was retired due to multiple single bit ECC errors.
358    #[wrap(c_variant = "NVML_PAGE_RETIREMENT_CAUSE_MULTIPLE_SINGLE_BIT_ECC_ERRORS")]
359    MultipleSingleBitEccErrors,
360    /// Page was retired due to a single double bit ECC error.
361    #[wrap(c_variant = "NVML_PAGE_RETIREMENT_CAUSE_DOUBLE_BIT_ECC_ERROR")]
362    DoubleBitEccError,
363}
364
365/// Possible types of sampling events.
366// Checked against local
367#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
368#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
369#[wrap(c_enum = "nvmlSamplingType_enum")]
370pub enum Sampling {
371    /// Total power drawn by GPU.
372    #[wrap(c_variant = "NVML_TOTAL_POWER_SAMPLES")]
373    Power,
374    /// Percent of time during which one or more kernels was executing on the
375    /// GPU.
376    #[wrap(c_variant = "NVML_GPU_UTILIZATION_SAMPLES")]
377    GpuUtilization,
378    /// Percent of time during which global (device) memory was being read or
379    /// written.
380    #[wrap(c_variant = "NVML_MEMORY_UTILIZATION_SAMPLES")]
381    MemoryUtilization,
382    /// Percent of time during which NVENC remains busy.
383    #[wrap(c_variant = "NVML_ENC_UTILIZATION_SAMPLES")]
384    EncoderUtilization,
385    /// Percent of time during which NVDEC remains busy.
386    #[wrap(c_variant = "NVML_DEC_UTILIZATION_SAMPLES")]
387    DecoderUtilization,
388    /// Processor clock samples.
389    #[wrap(c_variant = "NVML_PROCESSOR_CLK_SAMPLES")]
390    ProcessorClock,
391    /// Memory clock samples.
392    #[wrap(c_variant = "NVML_MEMORY_CLK_SAMPLES")]
393    MemoryClock,
394}
395
396// Checked against local
397#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
398#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
399#[wrap(c_enum = "nvmlTemperatureSensors_enum")]
400pub enum TemperatureSensor {
401    /// Sensor for the GPU die.
402    #[wrap(c_variant = "NVML_TEMPERATURE_GPU")]
403    Gpu,
404}
405
406// Checked against local
407#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
408#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
409#[wrap(c_enum = "nvmlTemperatureThresholds_enum")]
410pub enum TemperatureThreshold {
411    /// Temperature at which the GPU will shut down for hardware protection.
412    #[wrap(c_variant = "NVML_TEMPERATURE_THRESHOLD_SHUTDOWN")]
413    Shutdown,
414    /// Temperature at which the GPU will begin hardware throttling.
415    #[wrap(c_variant = "NVML_TEMPERATURE_THRESHOLD_SLOWDOWN")]
416    Slowdown,
417    /// Memory temperature at which the GPU will begin software slowdown.
418    #[wrap(c_variant = "NVML_TEMPERATURE_THRESHOLD_MEM_MAX")]
419    MemoryMax,
420    /// GPU temperature at which the GPU can be throttled below the base clock.
421    #[wrap(c_variant = "NVML_TEMPERATURE_THRESHOLD_GPU_MAX")]
422    GpuMax,
423}
424
425/// Level relationships within a system between two GPUs.
426// Checked against local
427#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
428#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
429#[wrap(c_enum = "nvmlGpuLevel_enum")]
430pub enum TopologyLevel {
431    /// e.g. Tesla K80.
432    #[wrap(c_variant = "NVML_TOPOLOGY_INTERNAL")]
433    Internal,
434    /// All devices that only need traverse a single PCIe switch.
435    #[wrap(c_variant = "NVML_TOPOLOGY_SINGLE")]
436    Single,
437    /// All devices that need not traverse a host bridge.
438    #[wrap(c_variant = "NVML_TOPOLOGY_MULTIPLE")]
439    Multiple,
440    /// All devices that are connected to the same host bridge.
441    #[wrap(c_variant = "NVML_TOPOLOGY_HOSTBRIDGE")]
442    HostBridge,
443    /**
444    All devices that are connected to the same NUMA node but possibly
445    multiple host bridges.
446
447    This was `Cpu` in previous versions of NVML.
448    */
449    #[wrap(c_variant = "NVML_TOPOLOGY_NODE")]
450    Node,
451    /// All devices in the system
452    #[wrap(c_variant = "NVML_TOPOLOGY_SYSTEM")]
453    System,
454}
455
456/// Types of performance policy for which violation times can be queried.
457// Checked against local
458#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
459#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
460#[wrap(c_enum = "nvmlPerfPolicyType_enum")]
461pub enum PerformancePolicy {
462    #[wrap(c_variant = "NVML_PERF_POLICY_POWER")]
463    Power,
464    #[wrap(c_variant = "NVML_PERF_POLICY_THERMAL")]
465    Thermal,
466    #[wrap(c_variant = "NVML_PERF_POLICY_SYNC_BOOST")]
467    SyncBoost,
468    #[wrap(c_variant = "NVML_PERF_POLICY_BOARD_LIMIT")]
469    BoardLimit,
470    #[wrap(c_variant = "NVML_PERF_POLICY_LOW_UTILIZATION")]
471    LowUtilization,
472    /// Board reliability limit.
473    #[wrap(c_variant = "NVML_PERF_POLICY_RELIABILITY")]
474    Reliability,
475
476    /// Total time the GPU was limited by any of the above.
477    #[wrap(c_variant = "NVML_PERF_POLICY_TOTAL_APP_CLOCKS")]
478    TotalAppClocks,
479    /// Total time the GPU was held below base clocks.
480    #[wrap(c_variant = "NVML_PERF_POLICY_TOTAL_BASE_CLOCKS")]
481    TotalBaseClocks,
482}
483
484/// `ExclusiveProcess` was added in CUDA 4.0. Earlier CUDA versions supported a
485/// single exclusive mode, which is equivalent to `ExclusiveThread` in CUDA 4.0
486/// and beyond.
487// Checked against local
488#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
489#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
490#[wrap(c_enum = "nvmlComputeMode_enum")]
491pub enum ComputeMode {
492    /// Multiple contexts per device.
493    #[wrap(c_variant = "NVML_COMPUTEMODE_DEFAULT")]
494    Default,
495    /// *SUPPORT REMOVED*
496    ///
497    /// Only one context per device, usable from one thread at a time. *NOT
498    /// SUPPORTED*
499    #[wrap(c_variant = "NVML_COMPUTEMODE_EXCLUSIVE_THREAD")]
500    ExclusiveThread,
501    /// No contexts per device.
502    #[wrap(c_variant = "NVML_COMPUTEMODE_PROHIBITED")]
503    Prohibited,
504    /// Only one context per device, usable from multiple threads at a time.
505    #[wrap(c_variant = "NVML_COMPUTEMODE_EXCLUSIVE_PROCESS")]
506    ExclusiveProcess,
507}
508
509/// P2P capability index status.
510// Checked against local
511#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
512#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
513#[wrap(c_enum = "nvmlGpuP2PStatus_enum")]
514pub enum P2pStatus {
515    #[wrap(c_variant = "NVML_P2P_STATUS_OK")]
516    Ok,
517    #[wrap(c_variant = "NVML_P2P_STATUS_CHIPSET_NOT_SUPPORED")]
518    ChipsetNotSupported,
519    #[wrap(c_variant = "NVML_P2P_STATUS_GPU_NOT_SUPPORTED")]
520    GpuNotSupported,
521    #[wrap(c_variant = "NVML_P2P_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED")]
522    IohTopologyNotSupported,
523    #[wrap(c_variant = "NVML_P2P_STATUS_DISABLED_BY_REGKEY")]
524    DisabledByRegkey,
525    #[wrap(c_variant = "NVML_P2P_STATUS_NOT_SUPPORTED")]
526    NotSupported,
527    #[wrap(c_variant = "NVML_P2P_STATUS_UNKNOWN")]
528    Unknown,
529}
530
531// Checked against local
532#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
533#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
534#[wrap(c_enum = "nvmlGpuP2PCapsIndex_enum")]
535pub enum P2pCapabilitiesIndex {
536    #[wrap(c_variant = "NVML_P2P_CAPS_INDEX_READ")]
537    Read,
538    #[wrap(c_variant = "NVML_P2P_CAPS_INDEX_WRITE")]
539    Write,
540    #[wrap(c_variant = "NVML_P2P_CAPS_INDEX_NVLINK")]
541    NvLink,
542    #[wrap(c_variant = "NVML_P2P_CAPS_INDEX_ATOMICS")]
543    Atomics,
544    #[wrap(c_variant = "NVML_P2P_CAPS_INDEX_PROP")]
545    Prop,
546    #[wrap(c_variant = "NVML_P2P_CAPS_INDEX_UNKNOWN")]
547    Unknown,
548}
549
550/// Represents types for returned sample values.
551// Checked against local
552#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
553#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
554#[wrap(c_enum = "nvmlValueType_enum")]
555pub enum SampleValueType {
556    #[wrap(c_variant = "NVML_VALUE_TYPE_DOUBLE")]
557    Double,
558    #[wrap(c_variant = "NVML_VALUE_TYPE_UNSIGNED_INT")]
559    UnsignedInt,
560    #[wrap(c_variant = "NVML_VALUE_TYPE_UNSIGNED_LONG")]
561    UnsignedLong,
562    #[wrap(c_variant = "NVML_VALUE_TYPE_UNSIGNED_LONG_LONG")]
563    UnsignedLongLong,
564    #[wrap(c_variant = "NVML_VALUE_TYPE_SIGNED_LONG_LONG")]
565    SignedLongLong,
566}
567
568/// Represents encoder types that capacity can be queried for.
569#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
570#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
571#[wrap(c_enum = "nvmlEncoderQueryType_enum")]
572pub enum EncoderType {
573    #[wrap(c_variant = "NVML_ENCODER_QUERY_H264")]
574    H264,
575    #[wrap(c_variant = "NVML_ENCODER_QUERY_HEVC")]
576    HEVC,
577}
578
579/// The type of a frame buffer capture session
580///
581/// NVIDIA doesn't document the variants beyond their names.
582#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
583#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
584#[wrap(c_enum = "nvmlFBCSessionType_enum")]
585pub enum FbcSessionType {
586    #[wrap(c_variant = "NVML_FBC_SESSION_TYPE_UNKNOWN")]
587    Unknown,
588    #[wrap(c_variant = "NVML_FBC_SESSION_TYPE_TOSYS")]
589    ToSys,
590    #[wrap(c_variant = "NVML_FBC_SESSION_TYPE_CUDA")]
591    Cuda,
592    #[wrap(c_variant = "NVML_FBC_SESSION_TYPE_VID")]
593    Vid,
594    #[wrap(c_variant = "NVML_FBC_SESSION_TYPE_HWENC")]
595    HwEnc,
596}
597
598/// Options to pass to [`crate::Device::remove()`].
599#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
600#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
601#[wrap(c_enum = "nvmlDetachGpuState_enum")]
602pub enum DetachGpuState {
603    #[wrap(c_variant = "NVML_DETACH_GPU_KEEP")]
604    Keep,
605    #[wrap(c_variant = "NVML_DETACH_GPU_REMOVE")]
606    Remove,
607}
608
609/// Options to pass to [`crate::Device::remove()`].
610#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
611#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
612#[wrap(c_enum = "nvmlPcieLinkState_enum")]
613pub enum PcieLinkState {
614    #[wrap(c_variant = "NVML_PCIE_LINK_KEEP")]
615    Keep,
616    #[wrap(c_variant = "NVML_PCIE_LINK_SHUT_DOWN")]
617    ShutDown,
618}
619
620/// Clock limit IDs for use with [`crate::Device::set_gpu_locked_clocks()`].
621#[derive(EnumWrapper, Debug, Clone, Eq, PartialEq, Hash)]
622#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
623#[wrap(c_enum = "nvmlClockLimitId_enum")]
624pub enum ClockLimitId {
625    /// Bound clock speed by the TDP of the device.
626    #[wrap(c_variant = "NVML_CLOCK_LIMIT_ID_TDP")]
627    Tdp,
628    /// No bound for clock speed.
629    #[wrap(c_variant = "NVML_CLOCK_LIMIT_ID_UNLIMITED")]
630    Unlimited,
631}
nvml_wrapper/enum_wrappers/device.rs

nvml_wrapper/enum_wrappers/
device.rs
