Constantsยง
- NVML_
FI_ DEV_ C2C_ LINK_ COUNT - NVML_
FI_ DEV_ C2C_ LINK_ GET_ MAX_ BW - NVML_
FI_ DEV_ C2C_ LINK_ GET_ STATUS - NVML_
FI_ DEV_ CLOCKS_ EVENT_ REASON_ HW_ POWER_ BRAKE_ SLOWDOWN - NVML_
FI_ DEV_ CLOCKS_ EVENT_ REASON_ HW_ THERM_ SLOWDOWN - NVML_
FI_ DEV_ CLOCKS_ EVENT_ REASON_ SW_ THERM_ SLOWDOWN - NVML_
FI_ DEV_ DRAIN_ AND_ RESET_ STATUS - NVML_
FI_ DEV_ ECC_ CURRENT - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ CBU - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ DEV - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ L1 - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ L2 - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ REG - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ TEX - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ TOTAL - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ CBU - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ DEV - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ L1 - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ L2 - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ REG - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ TEX - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ TOTAL - NVML_
FI_ DEV_ ECC_ PENDING - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ DEV - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ L1 - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ L2 - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ REG - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ TEX - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ TOTAL - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ DEV - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ L1 - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ L2 - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ REG - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ TEX - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ TOTAL - NVML_
FI_ DEV_ ENERGY - NVML_
FI_ DEV_ GET_ GPU_ RECOVERY_ ACTION - NVML_
FI_ DEV_ IS_ MIG_ MODE_ INDEPENDENT_ MIG_ QUERY_ CAPABLE - NVML_
FI_ DEV_ IS_ RESETLESS_ MIG_ SUPPORTED - NVML_
FI_ DEV_ MEMORY_ TEMP - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L0 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L1 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L2 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L3 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L4 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L5 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L6 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L7 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L8 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L9 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L10 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L11 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ TOTAL - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L0 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L1 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L2 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L3 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L4 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L5 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L6 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L7 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L8 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L9 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L10 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L11 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ TOTAL - NVML_
FI_ DEV_ NVLINK_ COUNT_ BUFFER_ OVERRUN_ ERRORS - NVML_
FI_ DEV_ NVLINK_ COUNT_ EFFECTIVE_ BER - NVML_
FI_ DEV_ NVLINK_ COUNT_ EFFECTIVE_ ERRORS - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 0 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 1 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 2 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 3 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 4 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 5 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 6 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 7 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 8 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 9 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 10 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 11 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 12 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 13 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 14 - NVML_
FI_ DEV_ NVLINK_ COUNT_ FEC_ HISTORY_ 15 - NVML_
FI_ DEV_ NVLINK_ COUNT_ LINK_ RECOVERY_ EVENTS - NVML_
FI_ DEV_ NVLINK_ COUNT_ LINK_ RECOVERY_ FAILED_ EVENTS - NVML_
FI_ DEV_ NVLINK_ COUNT_ LINK_ RECOVERY_ SUCCESSFUL_ EVENTS - NVML_
FI_ DEV_ NVLINK_ COUNT_ LOCAL_ LINK_ INTEGRITY_ ERRORS - NVML_
FI_ DEV_ NVLINK_ COUNT_ MALFORMED_ PACKET_ ERRORS - NVML_
FI_ DEV_ NVLINK_ COUNT_ RAW_ BER - NVML_
FI_ DEV_ NVLINK_ COUNT_ RAW_ BER_ LANE0 - NVML_
FI_ DEV_ NVLINK_ COUNT_ RAW_ BER_ LANE1 - NVML_
FI_ DEV_ NVLINK_ COUNT_ RCV_ BYTES - NVML_
FI_ DEV_ NVLINK_ COUNT_ RCV_ ERRORS - NVML_
FI_ DEV_ NVLINK_ COUNT_ RCV_ GENERAL_ ERRORS - NVML_
FI_ DEV_ NVLINK_ COUNT_ RCV_ PACKETS - NVML_
FI_ DEV_ NVLINK_ COUNT_ RCV_ REMOTE_ ERRORS - NVML_
FI_ DEV_ NVLINK_ COUNT_ SYMBOL_ BER - NVML_
FI_ DEV_ NVLINK_ COUNT_ SYMBOL_ ERRORS - NVML_
FI_ DEV_ NVLINK_ COUNT_ VL15_ DROPPED - NVML_
FI_ DEV_ NVLINK_ COUNT_ XMIT_ BYTES - NVML_
FI_ DEV_ NVLINK_ COUNT_ XMIT_ DISCARDS - NVML_
FI_ DEV_ NVLINK_ COUNT_ XMIT_ PACKETS - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L0 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L1 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L2 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L3 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L4 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L5 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L6 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L7 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L8 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L9 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L10 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L11 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ TOTAL - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L0 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L1 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L2 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L3 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L4 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L5 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L6 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L7 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L8 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L9 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L10 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L11 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ TOTAL - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L0 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L1 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L2 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L3 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L4 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L5 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L6 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L7 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L8 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L9 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L10 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L11 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ TOTAL - NVML_
FI_ DEV_ NVLINK_ ERROR_ DL_ CRC - NVML_
FI_ DEV_ NVLINK_ ERROR_ DL_ RECOVERY - NVML_
FI_ DEV_ NVLINK_ ERROR_ DL_ REPLAY - NVML_
FI_ DEV_ NVLINK_ GET_ POWER_ STATE - NVML_
FI_ DEV_ NVLINK_ GET_ POWER_ THRESHOLD - NVML_
FI_ DEV_ NVLINK_ GET_ POWER_ THRESHOLD_ MAX - NVML_
FI_ DEV_ NVLINK_ GET_ POWER_ THRESHOLD_ MIN - NVML_
FI_ DEV_ NVLINK_ GET_ POWER_ THRESHOLD_ SUPPORTED - NVML_
FI_ DEV_ NVLINK_ GET_ POWER_ THRESHOLD_ UNITS - NVML_
FI_ DEV_ NVLINK_ GET_ SPEED - NVML_
FI_ DEV_ NVLINK_ GET_ STATE - NVML_
FI_ DEV_ NVLINK_ GET_ VERSION - NVML_
FI_ DEV_ NVLINK_ LINK_ COUNT - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L0 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L1 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L2 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L3 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L4 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L5 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L6 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L7 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L8 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L9 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L10 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L11 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ TOTAL - NVML_
FI_ DEV_ NVLINK_ REMOTE_ NVLINK_ ID - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L0 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L1 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L2 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L3 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L4 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L5 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L6 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L7 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L8 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L9 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L10 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L11 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ TOTAL - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ COMMON - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L0 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L1 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L2 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L3 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L4 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L5 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L6 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L7 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L8 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L9 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L10 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L11 - NVML_
FI_ DEV_ NVLINK_ THROUGHPUT_ DATA_ RX - NVML_
FI_ DEV_ NVLINK_ THROUGHPUT_ DATA_ TX - NVML_
FI_ DEV_ NVLINK_ THROUGHPUT_ RAW_ RX - NVML_
FI_ DEV_ NVLINK_ THROUGHPUT_ RAW_ TX - NVML_
FI_ DEV_ NVSWITCH_ CONNECTED_ LINK_ COUNT - NVML_
FI_ DEV_ PCIE_ COUNT_ BAD_ DLLP - NVML_
FI_ DEV_ PCIE_ COUNT_ BAD_ TLP - NVML_
FI_ DEV_ PCIE_ COUNT_ CORRECTABLE_ ERRORS - NVML_
FI_ DEV_ PCIE_ COUNT_ FATAL_ ERROR - NVML_
FI_ DEV_ PCIE_ COUNT_ LANE_ ERROR - NVML_
FI_ DEV_ PCIE_ COUNT_ LCRC_ ERROR - NVML_
FI_ DEV_ PCIE_ COUNT_ NAKS_ RECEIVED - NVML_
FI_ DEV_ PCIE_ COUNT_ NAKS_ SENT - NVML_
FI_ DEV_ PCIE_ COUNT_ NON_ FATAL_ ERROR - NVML_
FI_ DEV_ PCIE_ COUNT_ RECEIVER_ ERROR - NVML_
FI_ DEV_ PCIE_ COUNT_ RX_ BYTES - NVML_
FI_ DEV_ PCIE_ COUNT_ TX_ BYTES - NVML_
FI_ DEV_ PCIE_ COUNT_ UNSUPPORTED_ REQ - NVML_
FI_ DEV_ PCIE_ INBOUND_ ATOMICS_ MASK - NVML_
FI_ DEV_ PCIE_ L0_ TO_ RECOVERY_ COUNTER - NVML_
FI_ DEV_ PCIE_ OUTBOUND_ ATOMICS_ MASK - NVML_
FI_ DEV_ PCIE_ REPLAY_ COUNTER - NVML_
FI_ DEV_ PCIE_ REPLAY_ ROLLOVER_ COUNTER - NVML_
FI_ DEV_ PERF_ POLICY_ BOARD_ LIMIT - NVML_
FI_ DEV_ PERF_ POLICY_ LOW_ UTILIZATION - NVML_
FI_ DEV_ PERF_ POLICY_ POWER - NVML_
FI_ DEV_ PERF_ POLICY_ RELIABILITY - NVML_
FI_ DEV_ PERF_ POLICY_ SYNC_ BOOST - NVML_
FI_ DEV_ PERF_ POLICY_ THERMAL - NVML_
FI_ DEV_ PERF_ POLICY_ TOTAL_ APP_ CLOCKS - NVML_
FI_ DEV_ PERF_ POLICY_ TOTAL_ BASE_ CLOCKS - NVML_
FI_ DEV_ POWER_ AVERAGE - NVML_
FI_ DEV_ POWER_ CURRENT_ LIMIT - NVML_
FI_ DEV_ POWER_ DEFAULT_ LIMIT - NVML_
FI_ DEV_ POWER_ INSTANT - NVML_
FI_ DEV_ POWER_ MAX_ LIMIT - NVML_
FI_ DEV_ POWER_ MIN_ LIMIT - NVML_
FI_ DEV_ POWER_ REQUESTED_ LIMIT - NVML_
FI_ DEV_ POWER_ SYNC_ BALANCING_ AF - NVML_
FI_ DEV_ POWER_ SYNC_ BALANCING_ FREQ - NVML_
FI_ DEV_ REMAPPED_ COR - NVML_
FI_ DEV_ REMAPPED_ FAILURE - NVML_
FI_ DEV_ REMAPPED_ PENDING - NVML_
FI_ DEV_ REMAPPED_ UNC - NVML_
FI_ DEV_ RESET_ STATUS - NVML_
FI_ DEV_ RETIRED_ DBE - NVML_
FI_ DEV_ RETIRED_ PENDING - NVML_
FI_ DEV_ RETIRED_ PENDING_ DBE - NVML_
FI_ DEV_ RETIRED_ PENDING_ SBE - NVML_
FI_ DEV_ RETIRED_ SBE - NVML_
FI_ DEV_ TEMPERATURE_ GPU_ MAX_ TLIMIT - NVML_
FI_ DEV_ TEMPERATURE_ MEM_ MAX_ TLIMIT - NVML_
FI_ DEV_ TEMPERATURE_ SHUTDOWN_ TLIMIT - NVML_
FI_ DEV_ TEMPERATURE_ SLOWDOWN_ TLIMIT - NVML_
FI_ DEV_ TOTAL_ ENERGY_ CONSUMPTION - NVML_
FI_ MAX - NVML_
FI_ PWR_ SMOOTHING_ ACTIVE_ PRESET_ PROFILE - NVML_
FI_ PWR_ SMOOTHING_ ADMIN_ OVERRIDE_ PERCENT_ TMP_ FLOOR - NVML_
FI_ PWR_ SMOOTHING_ ADMIN_ OVERRIDE_ RAMP_ DOWN_ HYST_ VAL - NVML_
FI_ PWR_ SMOOTHING_ ADMIN_ OVERRIDE_ RAMP_ DOWN_ RATE - NVML_
FI_ PWR_ SMOOTHING_ ADMIN_ OVERRIDE_ RAMP_ UP_ RATE - NVML_
FI_ PWR_ SMOOTHING_ APPLIED_ TMP_ CEIL - NVML_
FI_ PWR_ SMOOTHING_ APPLIED_ TMP_ FLOOR - NVML_
FI_ PWR_ SMOOTHING_ ENABLED - NVML_
FI_ PWR_ SMOOTHING_ HW_ CIRCUITRY_ PERCENT_ LIFETIME_ REMAINING - NVML_
FI_ PWR_ SMOOTHING_ IMM_ RAMP_ DOWN_ ENABLED - NVML_
FI_ PWR_ SMOOTHING_ MAX_ NUM_ PRESET_ PROFILES - NVML_
FI_ PWR_ SMOOTHING_ MAX_ PERCENT_ TMP_ FLOOR_ SETTING - NVML_
FI_ PWR_ SMOOTHING_ MIN_ PERCENT_ TMP_ FLOOR_ SETTING - NVML_
FI_ PWR_ SMOOTHING_ PRIV_ LVL - NVML_
FI_ PWR_ SMOOTHING_ PROFILE_ PERCENT_ TMP_ FLOOR - NVML_
FI_ PWR_ SMOOTHING_ PROFILE_ RAMP_ DOWN_ HYST_ VAL - NVML_
FI_ PWR_ SMOOTHING_ PROFILE_ RAMP_ DOWN_ RATE - NVML_
FI_ PWR_ SMOOTHING_ PROFILE_ RAMP_ UP_ RATE