Struct nucleo_h7xx::pac::quadspi::RegisterBlock[−]

#[repr(C)]pub struct RegisterBlock {
    pub cr: Reg<u32, _CR>,
    pub dcr: Reg<u32, _DCR>,
    pub sr: Reg<u32, _SR>,
    pub fcr: Reg<u32, _FCR>,
    pub dlr: Reg<u32, _DLR>,
    pub ccr: Reg<u32, _CCR>,
    pub ar: Reg<u32, _AR>,
    pub abr: Reg<u32, _ABR>,
    pub dr: Reg<u32, _DR>,
    pub psmkr: Reg<u32, _PSMKR>,
    pub psmar: Reg<u32, _PSMAR>,
    pub pir: Reg<u32, _PIR>,
    pub lptr: Reg<u32, _LPTR>,
}

Register block

Fields

cr: Reg<u32, _CR>

0x00 - QUADSPI control register

dcr: Reg<u32, _DCR>

0x04 - QUADSPI device configuration register

sr: Reg<u32, _SR>

0x08 - QUADSPI status register

fcr: Reg<u32, _FCR>

0x0c - QUADSPI flag clear register

dlr: Reg<u32, _DLR>

0x10 - QUADSPI data length register

ccr: Reg<u32, _CCR>

0x14 - QUADSPI communication configuration register

ar: Reg<u32, _AR>

0x18 - QUADSPI address register

abr: Reg<u32, _ABR>

0x1c - QUADSPI alternate bytes registers

dr: Reg<u32, _DR>

0x20 - QUADSPI data register

psmkr: Reg<u32, _PSMKR>

0x24 - QUADSPI polling status mask register

psmar: Reg<u32, _PSMAR>

0x28 - QUADSPI polling status match register

pir: Reg<u32, _PIR>

0x2c - QUADSPI polling interval register

lptr: Reg<u32, _LPTR>

0x30 - QUADSPI low-power timeout register

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