Struct nucleo_h7xx::pac::hrtim_timd::RegisterBlock[]

#[repr(C)]pub struct RegisterBlock {
    pub timdcr: Reg<u32, _TIMDCR>,
    pub timdisr: Reg<u32, _TIMDISR>,
    pub timdicr: Reg<u32, _TIMDICR>,
    pub timddier5: Reg<u32, _TIMDDIER5>,
    pub cntdr: Reg<u32, _CNTDR>,
    pub perdr: Reg<u32, _PERDR>,
    pub repdr: Reg<u32, _REPDR>,
    pub cmp1dr: Reg<u32, _CMP1DR>,
    pub cmp1cdr: Reg<u32, _CMP1CDR>,
    pub cmp2dr: Reg<u32, _CMP2DR>,
    pub cmp3dr: Reg<u32, _CMP3DR>,
    pub cmp4dr: Reg<u32, _CMP4DR>,
    pub cpt1dr: Reg<u32, _CPT1DR>,
    pub cpt2dr: Reg<u32, _CPT2DR>,
    pub dtdr: Reg<u32, _DTDR>,
    pub setd1r: Reg<u32, _SETD1R>,
    pub rstd1r: Reg<u32, _RSTD1R>,
    pub setd2r: Reg<u32, _SETD2R>,
    pub rstd2r: Reg<u32, _RSTD2R>,
    pub eefdr1: Reg<u32, _EEFDR1>,
    pub eefdr2: Reg<u32, _EEFDR2>,
    pub rstdr: Reg<u32, _RSTDR>,
    pub chpdr: Reg<u32, _CHPDR>,
    pub cpt1dcr: Reg<u32, _CPT1DCR>,
    pub cpt2dcr: Reg<u32, _CPT2DCR>,
    pub outdr: Reg<u32, _OUTDR>,
    pub fltdr: Reg<u32, _FLTDR>,
}

Register block

Fields

timdcr: Reg<u32, _TIMDCR>

0x00 - Timerx Control Register

timdisr: Reg<u32, _TIMDISR>

0x04 - Timerx Interrupt Status Register

timdicr: Reg<u32, _TIMDICR>

0x08 - Timerx Interrupt Clear Register

timddier5: Reg<u32, _TIMDDIER5>

0x0c - TIMxDIER5

cntdr: Reg<u32, _CNTDR>

0x10 - Timerx Counter Register

perdr: Reg<u32, _PERDR>

0x14 - Timerx Period Register

repdr: Reg<u32, _REPDR>

0x18 - Timerx Repetition Register

cmp1dr: Reg<u32, _CMP1DR>

0x1c - Timerx Compare 1 Register

cmp1cdr: Reg<u32, _CMP1CDR>

0x20 - Timerx Compare 1 Compound Register

cmp2dr: Reg<u32, _CMP2DR>

0x24 - Timerx Compare 2 Register

cmp3dr: Reg<u32, _CMP3DR>

0x28 - Timerx Compare 3 Register

cmp4dr: Reg<u32, _CMP4DR>

0x2c - Timerx Compare 4 Register

cpt1dr: Reg<u32, _CPT1DR>

0x30 - Timerx Capture 1 Register

cpt2dr: Reg<u32, _CPT2DR>

0x34 - Timerx Capture 2 Register

dtdr: Reg<u32, _DTDR>

0x38 - Timerx Deadtime Register

setd1r: Reg<u32, _SETD1R>

0x3c - Timerx Output1 Set Register

rstd1r: Reg<u32, _RSTD1R>

0x40 - Timerx Output1 Reset Register

setd2r: Reg<u32, _SETD2R>

0x44 - Timerx Output2 Set Register

rstd2r: Reg<u32, _RSTD2R>

0x48 - Timerx Output2 Reset Register

eefdr1: Reg<u32, _EEFDR1>

0x4c - Timerx External Event Filtering Register 1

eefdr2: Reg<u32, _EEFDR2>

0x50 - Timerx External Event Filtering Register 2

rstdr: Reg<u32, _RSTDR>

0x54 - TimerA Reset Register

chpdr: Reg<u32, _CHPDR>

0x58 - Timerx Chopper Register

cpt1dcr: Reg<u32, _CPT1DCR>

0x5c - Timerx Capture 2 Control Register

cpt2dcr: Reg<u32, _CPT2DCR>

0x60 - CPT2xCR

outdr: Reg<u32, _OUTDR>

0x64 - Timerx Output Register

fltdr: Reg<u32, _FLTDR>

0x68 - Timerx Fault Register

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