Enum nucleo_h7xx::pac::dmamux1::ccr::DMAREQ_ID_A[]

#[repr(u8)]pub enum DMAREQ_ID_A {
    NONE,
    DMAMUX1_REQ_GEN0,
    DMAMUX1_REQ_GEN1,
    DMAMUX1_REQ_GEN2,
    DMAMUX1_REQ_GEN3,
    DMAMUX1_REQ_GEN4,
    DMAMUX1_REQ_GEN5,
    DMAMUX1_REQ_GEN6,
    DMAMUX1_REQ_GEN7,
    ADC1_DMA,
    ADC2_DMA,
    TIM1_CH1,
    TIM1_CH2,
    TIM1_CH3,
    TIM1_CH4,
    TIM1_UP,
    TIM1_TRIG,
    TIM1_COM,
    TIM2_CH1,
    TIM2_CH2,
    TIM2_CH3,
    TIM2_CH4,
    TIM2_UP,
    TIM3_CH1,
    TIM3_CH2,
    TIM3_CH3,
    TIM3_CH4,
    TIM3_UP,
    TIM3_TRIG,
    TIM4_CH1,
    TIM4_CH2,
    TIM4_CH3,
    TIM4_UP,
    I2C1_RX_DMA,
    I2C1_TX_DMA,
    I2C2_RX_DMA,
    I2C2_TX_DMA,
    SPI1_RX_DMA,
    SPI1_TX_DMA,
    SPI2_RX_DMA,
    SPI2_TX_DMA,
    USART1_RX_DMA,
    USART1_TX_DMA,
    USART2_RX_DMA,
    USART2_TX_DMA,
    USART3_RX_DMA,
    USART3_TX_DMA,
    TIM8_CH1,
    TIM8_CH2,
    TIM8_CH3,
    TIM8_CH4,
    TIM8_UP,
    TIM8_TRIG,
    TIM8_COM,
    TIM5_CH1,
    TIM5_CH2,
    TIM5_CH3,
    TIM5_CH4,
    TIM5_UP,
    TIM5_TRIG,
    SPI3_RX_DMA,
    SPI3_TX_DMA,
    UART4_RX_DMA,
    UART4_TX_DMA,
    UART5_RX_DMA,
    UART5_TX_DMA,
    DAC_CH1_DMA,
    DAC_CH2_DMA,
    TIM6_UP,
    TIM7_UP,
    USART6_RX_DMA,
    USART6_TX_DMA,
    I2C3_RX_DMA,
    I2C3_TX_DMA,
    DCMI_DMA,
    CRYP_IN_DMA,
    CRYP_OUT_DMA,
    HASH_IN_DMA,
    UART7_RX_DMA,
    UART7_TX_DMA,
    UART8_RX_DMA,
    UART8_TX_DMA,
    SPI4_RX_DMA,
    SPI4_TX_DMA,
    SPI5_RX_DMA,
    SPI5_TX_DMA,
    SAI1A_DMA,
    SAI1B_DMA,
    SAI2A_DMA,
    SAI2B_DMA,
    SWPMI_RX_DMA,
    SWPMI_TX_DMA,
    SPDIFRX_DAT_DMA,
    SPDIFRX_CTRL_DMA,
    HR_REQ1,
    HR_REQ2,
    HR_REQ3,
    HR_REQ4,
    HR_REQ5,
    HR_REQ6,
    DFSDM1_DMA0,
    DFSDM1_DMA1,
    DFSDM1_DMA2,
    DFSDM1_DMA3,
    TIM15_CH1,
    TIM15_UP,
    TIM15_TRIG,
    TIM15_COM,
    TIM16_CH1,
    TIM16_UP,
    TIM17_CH1,
    TIM17_UP,
    SAI3_A_DMA,
    SAI3_B_DMA,
    ADC3_DMA,
}

Input DMA request line selected

Value on reset: 0

Variants

NONE

0: No signal selected as request input

DMAMUX1_REQ_GEN0

1: Signal dmamux1_req_gen0 selected as request input

DMAMUX1_REQ_GEN1

2: Signal dmamux1_req_gen1 selected as request input

DMAMUX1_REQ_GEN2

3: Signal dmamux1_req_gen2 selected as request input

DMAMUX1_REQ_GEN3

4: Signal dmamux1_req_gen3 selected as request input

DMAMUX1_REQ_GEN4

5: Signal dmamux1_req_gen4 selected as request input

DMAMUX1_REQ_GEN5

6: Signal dmamux1_req_gen5 selected as request input

DMAMUX1_REQ_GEN6

7: Signal dmamux1_req_gen6 selected as request input

DMAMUX1_REQ_GEN7

8: Signal dmamux1_req_gen7 selected as request input

ADC1_DMA

9: Signal adc1_dma selected as request input

ADC2_DMA

10: Signal adc2_dma selected as request input

TIM1_CH1

11: Signal tim1_ch1 selected as request input

TIM1_CH2

12: Signal tim1_ch2 selected as request input

TIM1_CH3

13: Signal tim1_ch3 selected as request input

TIM1_CH4

14: Signal tim1_ch4 selected as request input

TIM1_UP

15: Signal tim1_up selected as request input

TIM1_TRIG

16: Signal tim1_trig selected as request input

TIM1_COM

17: Signal tim1_com selected as request input

TIM2_CH1

18: Signal tim2_ch1 selected as request input

TIM2_CH2

19: Signal tim2_ch2 selected as request input

TIM2_CH3

20: Signal tim2_ch3 selected as request input

TIM2_CH4

21: Signal tim2_ch4 selected as request input

TIM2_UP

22: Signal tim2_up selected as request input

TIM3_CH1

23: Signal tim3_ch1 selected as request input

TIM3_CH2

24: Signal tim3_ch2 selected as request input

TIM3_CH3

25: Signal tim3_ch3 selected as request input

TIM3_CH4

26: Signal tim3_ch4 selected as request input

TIM3_UP

27: Signal tim3_up selected as request input

TIM3_TRIG

28: Signal tim3_trig selected as request input

TIM4_CH1

29: Signal tim4_ch1 selected as request input

TIM4_CH2

30: Signal tim4_ch2 selected as request input

TIM4_CH3

31: Signal tim4_ch3 selected as request input

TIM4_UP

32: Signal tim4_up selected as request input

I2C1_RX_DMA

33: Signal i2c1_rx_dma selected as request input

I2C1_TX_DMA

34: Signal i2c1_tx_dma selected as request input

I2C2_RX_DMA

35: Signal i2c2_rx_dma selected as request input

I2C2_TX_DMA

36: Signal i2c2_tx_dma selected as request input

SPI1_RX_DMA

37: Signal spi1_rx_dma selected as request input

SPI1_TX_DMA

38: Signal spi1_tx_dma selected as request input

SPI2_RX_DMA

39: Signal spi2_rx_dma selected as request input

SPI2_TX_DMA

40: Signal spi2_tx_dma selected as request input

USART1_RX_DMA

41: Signal usart1_rx_dma selected as request input

USART1_TX_DMA

42: Signal usart1_tx_dma selected as request input

USART2_RX_DMA

43: Signal usart2_rx_dma selected as request input

USART2_TX_DMA

44: Signal usart2_tx_dma selected as request input

USART3_RX_DMA

45: Signal usart3_rx_dma selected as request input

USART3_TX_DMA

46: Signal usart3_tx_dma selected as request input

TIM8_CH1

47: Signal tim8_ch1 selected as request input

TIM8_CH2

48: Signal tim8_ch2 selected as request input

TIM8_CH3

49: Signal tim8_ch3 selected as request input

TIM8_CH4

50: Signal tim8_ch4 selected as request input

TIM8_UP

51: Signal tim8_up selected as request input

TIM8_TRIG

52: Signal tim8_trig selected as request input

TIM8_COM

53: Signal tim8_com selected as request input

TIM5_CH1

55: Signal tim5_ch1 selected as request input

TIM5_CH2

56: Signal tim5_ch2 selected as request input

TIM5_CH3

57: Signal tim5_ch3 selected as request input

TIM5_CH4

58: Signal tim5_ch4 selected as request input

TIM5_UP

59: Signal tim5_up selected as request input

TIM5_TRIG

60: Signal tim5_trig selected as request input

SPI3_RX_DMA

61: Signal spi3_rx_dma selected as request input

SPI3_TX_DMA

62: Signal spi3_tx_dma selected as request input

UART4_RX_DMA

63: Signal uart4_rx_dma selected as request input

UART4_TX_DMA

64: Signal uart4_tx_dma selected as request input

UART5_RX_DMA

65: Signal uart5_rx_dma selected as request input

UART5_TX_DMA

66: Signal uart5_tx_dma selected as request input

DAC_CH1_DMA

67: Signal dac_ch1_dma selected as request input

DAC_CH2_DMA

68: Signal dac_ch2_dma selected as request input

TIM6_UP

69: Signal tim6_up selected as request input

TIM7_UP

70: Signal tim7_up selected as request input

USART6_RX_DMA

71: Signal usart6_rx_dma selected as request input

USART6_TX_DMA

72: Signal usart6_tx_dma selected as request input

I2C3_RX_DMA

73: Signal i2c3_rx_dma selected as request input

I2C3_TX_DMA

74: Signal i2c3_tx_dma selected as request input

DCMI_DMA

75: Signal dcmi_dma selected as request input

CRYP_IN_DMA

76: Signal cryp_in_dma selected as request input

CRYP_OUT_DMA

77: Signal cryp_out_dma selected as request input

HASH_IN_DMA

78: Signal hash_in_dma selected as request input

UART7_RX_DMA

79: Signal uart7_rx_dma selected as request input

UART7_TX_DMA

80: Signal uart7_tx_dma selected as request input

UART8_RX_DMA

81: Signal uart8_rx_dma selected as request input

UART8_TX_DMA

82: Signal uart8_tx_dma selected as request input

SPI4_RX_DMA

83: Signal spi4_rx_dma selected as request input

SPI4_TX_DMA

84: Signal spi4_tx_dma selected as request input

SPI5_RX_DMA

85: Signal spi5_rx_dma selected as request input

SPI5_TX_DMA

86: Signal spi5_tx_dma selected as request input

SAI1A_DMA

87: Signal sai1a_dma selected as request input

SAI1B_DMA

88: Signal sai1b_dma selected as request input

SAI2A_DMA

89: Signal sai2a_dma selected as request input

SAI2B_DMA

90: Signal sai2b_dma selected as request input

SWPMI_RX_DMA

91: Signal swpmi_rx_dma selected as request input

SWPMI_TX_DMA

92: Signal swpmi_tx_dma selected as request input

SPDIFRX_DAT_DMA

93: Signal spdifrx_dat_dma selected as request input

SPDIFRX_CTRL_DMA

94: Signal spdifrx_ctrl_dma selected as request input

HR_REQ1

95: Signal hr_req(1) selected as request input

HR_REQ2

96: Signal hr_req(2) selected as request input

HR_REQ3

97: Signal hr_req(3) selected as request input

HR_REQ4

98: Signal hr_req(4) selected as request input

HR_REQ5

99: Signal hr_req(5) selected as request input

HR_REQ6

100: Signal hr_req(6) selected as request input

DFSDM1_DMA0

101: Signal dfsdm1_dma0 selected as request input

DFSDM1_DMA1

102: Signal dfsdm1_dma1 selected as request input

DFSDM1_DMA2

103: Signal dfsdm1_dma2 selected as request input

DFSDM1_DMA3

104: Signal dfsdm1_dma3 selected as request input

TIM15_CH1

105: Signal tim15_ch1 selected as request input

TIM15_UP

106: Signal tim15_up selected as request input

TIM15_TRIG

107: Signal tim15_trig selected as request input

TIM15_COM

108: Signal tim15_com selected as request input

TIM16_CH1

109: Signal tim16_ch1 selected as request input

TIM16_UP

110: Signal tim16_up selected as request input

TIM17_CH1

111: Signal tim17_ch1 selected as request input

TIM17_UP

112: Signal tim17_up selected as request input

SAI3_A_DMA

113: Signal sai3_a_dma selected as request input

SAI3_B_DMA

114: Signal sai3_b_dma selected as request input

ADC3_DMA

115: Signal adc3_dma selected as request input

Trait Implementations

impl Clone for DMAREQ_ID_A

impl Copy for DMAREQ_ID_A

impl Debug for DMAREQ_ID_A

impl PartialEq<DMAREQ_ID_A> for DMAREQ_ID_A

impl StructuralPartialEq for DMAREQ_ID_A

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> Same<T> for T

type Output = T

Should always be Self

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.