Struct nucleo_h7xx::pac::dma2d::RegisterBlock[−]

#[repr(C)]pub struct RegisterBlock {
    pub cr: Reg<u32, _CR>,
    pub isr: Reg<u32, _ISR>,
    pub ifcr: Reg<u32, _IFCR>,
    pub fgmar: Reg<u32, _FGMAR>,
    pub fgor: Reg<u32, _FGOR>,
    pub bgmar: Reg<u32, _BGMAR>,
    pub bgor: Reg<u32, _BGOR>,
    pub fgpfccr: Reg<u32, _FGPFCCR>,
    pub fgcolr: Reg<u32, _FGCOLR>,
    pub bgpfccr: Reg<u32, _BGPFCCR>,
    pub bgcolr: Reg<u32, _BGCOLR>,
    pub fgcmar: Reg<u32, _FGCMAR>,
    pub bgcmar: Reg<u32, _BGCMAR>,
    pub opfccr: Reg<u32, _OPFCCR>,
    pub ocolr: Reg<u32, _OCOLR>,
    pub omar: Reg<u32, _OMAR>,
    pub oor: Reg<u32, _OOR>,
    pub nlr: Reg<u32, _NLR>,
    pub lwr: Reg<u32, _LWR>,
    pub amtcr: Reg<u32, _AMTCR>,
}

Register block

Fields

cr: Reg<u32, _CR>

0x00 - DMA2D control register

isr: Reg<u32, _ISR>

0x04 - DMA2D Interrupt Status Register

ifcr: Reg<u32, _IFCR>

0x08 - DMA2D interrupt flag clear register

fgmar: Reg<u32, _FGMAR>

0x0c - DMA2D foreground memory address register

fgor: Reg<u32, _FGOR>

0x10 - DMA2D foreground offset register

bgmar: Reg<u32, _BGMAR>

0x14 - DMA2D background memory address register

bgor: Reg<u32, _BGOR>

0x18 - DMA2D background offset register

fgpfccr: Reg<u32, _FGPFCCR>

0x1c - DMA2D foreground PFC control register

fgcolr: Reg<u32, _FGCOLR>

0x20 - DMA2D foreground color register

bgpfccr: Reg<u32, _BGPFCCR>

0x24 - DMA2D background PFC control register

bgcolr: Reg<u32, _BGCOLR>

0x28 - DMA2D background color register

fgcmar: Reg<u32, _FGCMAR>

0x2c - DMA2D foreground CLUT memory address register

bgcmar: Reg<u32, _BGCMAR>

0x30 - DMA2D background CLUT memory address register

opfccr: Reg<u32, _OPFCCR>

0x34 - DMA2D output PFC control register

ocolr: Reg<u32, _OCOLR>

0x38 - DMA2D output color register

omar: Reg<u32, _OMAR>

0x3c - DMA2D output memory address register

oor: Reg<u32, _OOR>

0x40 - DMA2D output offset register

nlr: Reg<u32, _NLR>

0x44 - DMA2D number of line register

lwr: Reg<u32, _LWR>

0x48 - DMA2D line watermark register

amtcr: Reg<u32, _AMTCR>

0x4c - DMA2D AXI master timer configuration register

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