Struct nucleo_h7xx::pac::cryp::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub cr: Reg<u32, _CR>,
    pub sr: Reg<u32, _SR>,
    pub din: Reg<u32, _DIN>,
    pub dout: Reg<u32, _DOUT>,
    pub dmacr: Reg<u32, _DMACR>,
    pub imscr: Reg<u32, _IMSCR>,
    pub risr: Reg<u32, _RISR>,
    pub misr: Reg<u32, _MISR>,
    pub k0lr: Reg<u32, _K0LR>,
    pub k0rr: Reg<u32, _K0RR>,
    pub k1lr: Reg<u32, _K1LR>,
    pub k1rr: Reg<u32, _K1RR>,
    pub k2lr: Reg<u32, _K2LR>,
    pub k2rr: Reg<u32, _K2RR>,
    pub k3lr: Reg<u32, _K3LR>,
    pub k3rr: Reg<u32, _K3RR>,
    pub iv0lr: Reg<u32, _IV0LR>,
    pub iv0rr: Reg<u32, _IV0RR>,
    pub iv1lr: Reg<u32, _IV1LR>,
    pub iv1rr: Reg<u32, _IV1RR>,
    pub csgcmccm0r: Reg<u32, _CSGCMCCM0R>,
    pub csgcmccm1r: Reg<u32, _CSGCMCCM1R>,
    pub csgcmccm2r: Reg<u32, _CSGCMCCM2R>,
    pub csgcmccm3r: Reg<u32, _CSGCMCCM3R>,
    pub csgcmccm4r: Reg<u32, _CSGCMCCM4R>,
    pub csgcmccm5r: Reg<u32, _CSGCMCCM5R>,
    pub csgcmccm6r: Reg<u32, _CSGCMCCM6R>,
    pub csgcmccm7r: Reg<u32, _CSGCMCCM7R>,
    pub csgcm0r: Reg<u32, _CSGCM0R>,
    pub csgcm1r: Reg<u32, _CSGCM1R>,
    pub csgcm2r: Reg<u32, _CSGCM2R>,
    pub csgcm3r: Reg<u32, _CSGCM3R>,
    pub csgcm4r: Reg<u32, _CSGCM4R>,
    pub csgcm5r: Reg<u32, _CSGCM5R>,
    pub csgcm6r: Reg<u32, _CSGCM6R>,
    pub csgcm7r: Reg<u32, _CSGCM7R>,
}

Register block

Fields

cr: Reg<u32, _CR>

0x00 - control register

sr: Reg<u32, _SR>

0x04 - status register

din: Reg<u32, _DIN>

0x08 - data input register

dout: Reg<u32, _DOUT>

0x0c - data output register

dmacr: Reg<u32, _DMACR>

0x10 - DMA control register

imscr: Reg<u32, _IMSCR>

0x14 - interrupt mask set/clear register

risr: Reg<u32, _RISR>

0x18 - raw interrupt status register

misr: Reg<u32, _MISR>

0x1c - masked interrupt status register

k0lr: Reg<u32, _K0LR>

0x20 - key registers

k0rr: Reg<u32, _K0RR>

0x24 - key registers

k1lr: Reg<u32, _K1LR>

0x28 - key registers

k1rr: Reg<u32, _K1RR>

0x2c - key registers

k2lr: Reg<u32, _K2LR>

0x30 - key registers

k2rr: Reg<u32, _K2RR>

0x34 - key registers

k3lr: Reg<u32, _K3LR>

0x38 - key registers

k3rr: Reg<u32, _K3RR>

0x3c - key registers

iv0lr: Reg<u32, _IV0LR>

0x40 - initialization vector registers

iv0rr: Reg<u32, _IV0RR>

0x44 - initialization vector registers

iv1lr: Reg<u32, _IV1LR>

0x48 - initialization vector registers

iv1rr: Reg<u32, _IV1RR>

0x4c - initialization vector registers

csgcmccm0r: Reg<u32, _CSGCMCCM0R>

0x50 - context swap register

csgcmccm1r: Reg<u32, _CSGCMCCM1R>

0x54 - context swap register

csgcmccm2r: Reg<u32, _CSGCMCCM2R>

0x58 - context swap register

csgcmccm3r: Reg<u32, _CSGCMCCM3R>

0x5c - context swap register

csgcmccm4r: Reg<u32, _CSGCMCCM4R>

0x60 - context swap register

csgcmccm5r: Reg<u32, _CSGCMCCM5R>

0x64 - context swap register

csgcmccm6r: Reg<u32, _CSGCMCCM6R>

0x68 - context swap register

csgcmccm7r: Reg<u32, _CSGCMCCM7R>

0x6c - context swap register

csgcm0r: Reg<u32, _CSGCM0R>

0x70 - context swap register

csgcm1r: Reg<u32, _CSGCM1R>

0x74 - context swap register

csgcm2r: Reg<u32, _CSGCM2R>

0x78 - context swap register

csgcm3r: Reg<u32, _CSGCM3R>

0x7c - context swap register

csgcm4r: Reg<u32, _CSGCM4R>

0x80 - context swap register

csgcm5r: Reg<u32, _CSGCM5R>

0x84 - context swap register

csgcm6r: Reg<u32, _CSGCM6R>

0x88 - context swap register

csgcm7r: Reg<u32, _CSGCM7R>

0x8c - context swap register