1#[doc = "Reader of register ADCR"]
2pub type R = crate::R<u32, super::ADCR>;
3#[doc = "Writer for register ADCR"]
4pub type W = crate::W<u32, super::ADCR>;
5#[doc = "Register ADCR `reset()`'s with value 0"]
6impl crate::ResetValue for super::ADCR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `ADEN`"]
14pub type ADEN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `ADEN`"]
16pub struct ADEN_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> ADEN_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34 self.w
35 }
36}
37#[doc = "Reader of field `ADIE`"]
38pub type ADIE_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `ADIE`"]
40pub struct ADIE_W<'a> {
41 w: &'a mut W,
42}
43impl<'a> ADIE_W<'a> {
44 #[doc = r"Sets the field bit"]
45 #[inline(always)]
46 pub fn set_bit(self) -> &'a mut W {
47 self.bit(true)
48 }
49 #[doc = r"Clears the field bit"]
50 #[inline(always)]
51 pub fn clear_bit(self) -> &'a mut W {
52 self.bit(false)
53 }
54 #[doc = r"Writes raw bits to the field"]
55 #[inline(always)]
56 pub fn bit(self, value: bool) -> &'a mut W {
57 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58 self.w
59 }
60}
61#[doc = "Reader of field `ADMD`"]
62pub type ADMD_R = crate::R<u8, u8>;
63#[doc = "Write proxy for field `ADMD`"]
64pub struct ADMD_W<'a> {
65 w: &'a mut W,
66}
67impl<'a> ADMD_W<'a> {
68 #[doc = r"Writes raw bits to the field"]
69 #[inline(always)]
70 pub unsafe fn bits(self, value: u8) -> &'a mut W {
71 self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
72 self.w
73 }
74}
75#[doc = "Reader of field `TRGS`"]
76pub type TRGS_R = crate::R<u8, u8>;
77#[doc = "Write proxy for field `TRGS`"]
78pub struct TRGS_W<'a> {
79 w: &'a mut W,
80}
81impl<'a> TRGS_W<'a> {
82 #[doc = r"Writes raw bits to the field"]
83 #[inline(always)]
84 pub unsafe fn bits(self, value: u8) -> &'a mut W {
85 self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
86 self.w
87 }
88}
89#[doc = "Reader of field `TRGCOND`"]
90pub type TRGCOND_R = crate::R<u8, u8>;
91#[doc = "Write proxy for field `TRGCOND`"]
92pub struct TRGCOND_W<'a> {
93 w: &'a mut W,
94}
95impl<'a> TRGCOND_W<'a> {
96 #[doc = r"Writes raw bits to the field"]
97 #[inline(always)]
98 pub unsafe fn bits(self, value: u8) -> &'a mut W {
99 self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6);
100 self.w
101 }
102}
103#[doc = "Reader of field `TRGEN`"]
104pub type TRGEN_R = crate::R<bool, bool>;
105#[doc = "Write proxy for field `TRGEN`"]
106pub struct TRGEN_W<'a> {
107 w: &'a mut W,
108}
109impl<'a> TRGEN_W<'a> {
110 #[doc = r"Sets the field bit"]
111 #[inline(always)]
112 pub fn set_bit(self) -> &'a mut W {
113 self.bit(true)
114 }
115 #[doc = r"Clears the field bit"]
116 #[inline(always)]
117 pub fn clear_bit(self) -> &'a mut W {
118 self.bit(false)
119 }
120 #[doc = r"Writes raw bits to the field"]
121 #[inline(always)]
122 pub fn bit(self, value: bool) -> &'a mut W {
123 self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
124 self.w
125 }
126}
127#[doc = "Reader of field `PTEN`"]
128pub type PTEN_R = crate::R<bool, bool>;
129#[doc = "Write proxy for field `PTEN`"]
130pub struct PTEN_W<'a> {
131 w: &'a mut W,
132}
133impl<'a> PTEN_W<'a> {
134 #[doc = r"Sets the field bit"]
135 #[inline(always)]
136 pub fn set_bit(self) -> &'a mut W {
137 self.bit(true)
138 }
139 #[doc = r"Clears the field bit"]
140 #[inline(always)]
141 pub fn clear_bit(self) -> &'a mut W {
142 self.bit(false)
143 }
144 #[doc = r"Writes raw bits to the field"]
145 #[inline(always)]
146 pub fn bit(self, value: bool) -> &'a mut W {
147 self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
148 self.w
149 }
150}
151#[doc = "Reader of field `DIFFEN`"]
152pub type DIFFEN_R = crate::R<bool, bool>;
153#[doc = "Write proxy for field `DIFFEN`"]
154pub struct DIFFEN_W<'a> {
155 w: &'a mut W,
156}
157impl<'a> DIFFEN_W<'a> {
158 #[doc = r"Sets the field bit"]
159 #[inline(always)]
160 pub fn set_bit(self) -> &'a mut W {
161 self.bit(true)
162 }
163 #[doc = r"Clears the field bit"]
164 #[inline(always)]
165 pub fn clear_bit(self) -> &'a mut W {
166 self.bit(false)
167 }
168 #[doc = r"Writes raw bits to the field"]
169 #[inline(always)]
170 pub fn bit(self, value: bool) -> &'a mut W {
171 self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
172 self.w
173 }
174}
175#[doc = "Reader of field `ADST`"]
176pub type ADST_R = crate::R<bool, bool>;
177#[doc = "Write proxy for field `ADST`"]
178pub struct ADST_W<'a> {
179 w: &'a mut W,
180}
181impl<'a> ADST_W<'a> {
182 #[doc = r"Sets the field bit"]
183 #[inline(always)]
184 pub fn set_bit(self) -> &'a mut W {
185 self.bit(true)
186 }
187 #[doc = r"Clears the field bit"]
188 #[inline(always)]
189 pub fn clear_bit(self) -> &'a mut W {
190 self.bit(false)
191 }
192 #[doc = r"Writes raw bits to the field"]
193 #[inline(always)]
194 pub fn bit(self, value: bool) -> &'a mut W {
195 self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
196 self.w
197 }
198}
199#[doc = "Reader of field `DMOF`"]
200pub type DMOF_R = crate::R<bool, bool>;
201#[doc = "Write proxy for field `DMOF`"]
202pub struct DMOF_W<'a> {
203 w: &'a mut W,
204}
205impl<'a> DMOF_W<'a> {
206 #[doc = r"Sets the field bit"]
207 #[inline(always)]
208 pub fn set_bit(self) -> &'a mut W {
209 self.bit(true)
210 }
211 #[doc = r"Clears the field bit"]
212 #[inline(always)]
213 pub fn clear_bit(self) -> &'a mut W {
214 self.bit(false)
215 }
216 #[doc = r"Writes raw bits to the field"]
217 #[inline(always)]
218 pub fn bit(self, value: bool) -> &'a mut W {
219 self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
220 self.w
221 }
222}
223impl R {
224 #[doc = "Bit 0 - A/D Converter Enable 1 = Enable 0 = Disable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption."]
225 #[inline(always)]
226 pub fn aden(&self) -> ADEN_R {
227 ADEN_R::new((self.bits & 0x01) != 0)
228 }
229 #[doc = "Bit 1 - A/D Interrupt Enable 1 = Enable A/D interrupt function 0 = Disable A/D interrupt function A/D conversion end interrupt request is generated if ADIE bit is set to 1."]
230 #[inline(always)]
231 pub fn adie(&self) -> ADIE_R {
232 ADIE_R::new(((self.bits >> 1) & 0x01) != 0)
233 }
234 #[doc = "Bits 2:3 - A/D Converter Operation Mode 00 = Single conversion 01 = Reserved 10 = Single-cycle scan 11 = Continuous scan When changing the operation mode, software should disable ADST bit firstly."]
235 #[inline(always)]
236 pub fn admd(&self) -> ADMD_R {
237 ADMD_R::new(((self.bits >> 2) & 0x03) as u8)
238 }
239 #[doc = "Bits 4:5 - Hardware Trigger Source 00 = A/D conversion is started by external STADC pin. Others = Reserved Software should disable TRGE and ADST before change TRGS. In hardware trigger mode, the ADST bit is set by the external trigger from STADC."]
240 #[inline(always)]
241 pub fn trgs(&self) -> TRGS_R {
242 TRGS_R::new(((self.bits >> 4) & 0x03) as u8)
243 }
244 #[doc = "Bits 6:7 - External Trigger Condition These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger. 00 = Low level 01 = High level 10 = Falling edge 11 = Positive edge"]
245 #[inline(always)]
246 pub fn trgcond(&self) -> TRGCOND_R {
247 TRGCOND_R::new(((self.bits >> 6) & 0x03) as u8)
248 }
249 #[doc = "Bit 8 - External Trigger Enable Enable or disable triggering of A/D conversion by external STADC pin. 1= Enable 0= Disable"]
250 #[inline(always)]
251 pub fn trgen(&self) -> TRGEN_R {
252 TRGEN_R::new(((self.bits >> 8) & 0x01) != 0)
253 }
254 #[doc = "Bit 9 - PDMA Transfer Enable 1 = Enable PDMA data transfer in ADDR 0~7 0 = Disable PDMA data transfer. When A/D conversion is completed, the converted data is loaded into ADDR 0~7, software can enable this bit to generate a PDMA data transfer request. When PTEN=1, software must set ADIE=0 to disable interrupt."]
255 #[inline(always)]
256 pub fn pten(&self) -> PTEN_R {
257 PTEN_R::new(((self.bits >> 9) & 0x01) != 0)
258 }
259 #[doc = "Bit 10 - A/D Differential Input Mode Enable 1 = A/D is in differential analog input mode 0 = A/D is in single-end analog input mode Differential input voltage (Vdiff) = Vplus - Vminus The Vplus of differential input paired channel 0 is from ADC0 pin; Vminus is from ADC1 pin. The Vplus of differential input paired channel 1 is from ADC2 pin; Vminus is from ADC3 pin. The Vplus of differential input paired channel 2 is from ADC4 pin; Vminus is from ADC5 pin. The Vplus of differential input paired channel 3 is from ADC6 pin; Vminus is from ADC7 pin. In differential input mode, only one of the two corresponding channels needs to be enabled in ADCHER. The conversion result will be placed to the corresponding data register of the enabled channel. If both channels of a differential input paired channel are enabled, the ADC will convert it twice in scan mode. And then write the conversion result to the two corresponding data registers."]
260 #[inline(always)]
261 pub fn diffen(&self) -> DIFFEN_R {
262 DIFFEN_R::new(((self.bits >> 10) & 0x01) != 0)
263 }
264 #[doc = "Bit 11 - A/D Conversion Start 1 = Conversion start. 0 = Conversion stopped and A/D converter enter idle state. ADST bit can be controlled by two sources: software write and external pin STADC. ADST is cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode on specified channels. In continuous scan mode, A/D conversion is continuously performed sequentially until this bit is cleared to 0 or chip reset."]
265 #[inline(always)]
266 pub fn adst(&self) -> ADST_R {
267 ADST_R::new(((self.bits >> 11) & 0x01) != 0)
268 }
269 #[doc = "Bit 31 - A/D differential input Mode Output Format This bit is only supported in Low Density. 1 = A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement format. 0 = A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format."]
270 #[inline(always)]
271 pub fn dmof(&self) -> DMOF_R {
272 DMOF_R::new(((self.bits >> 31) & 0x01) != 0)
273 }
274}
275impl W {
276 #[doc = "Bit 0 - A/D Converter Enable 1 = Enable 0 = Disable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption."]
277 #[inline(always)]
278 pub fn aden(&mut self) -> ADEN_W {
279 ADEN_W { w: self }
280 }
281 #[doc = "Bit 1 - A/D Interrupt Enable 1 = Enable A/D interrupt function 0 = Disable A/D interrupt function A/D conversion end interrupt request is generated if ADIE bit is set to 1."]
282 #[inline(always)]
283 pub fn adie(&mut self) -> ADIE_W {
284 ADIE_W { w: self }
285 }
286 #[doc = "Bits 2:3 - A/D Converter Operation Mode 00 = Single conversion 01 = Reserved 10 = Single-cycle scan 11 = Continuous scan When changing the operation mode, software should disable ADST bit firstly."]
287 #[inline(always)]
288 pub fn admd(&mut self) -> ADMD_W {
289 ADMD_W { w: self }
290 }
291 #[doc = "Bits 4:5 - Hardware Trigger Source 00 = A/D conversion is started by external STADC pin. Others = Reserved Software should disable TRGE and ADST before change TRGS. In hardware trigger mode, the ADST bit is set by the external trigger from STADC."]
292 #[inline(always)]
293 pub fn trgs(&mut self) -> TRGS_W {
294 TRGS_W { w: self }
295 }
296 #[doc = "Bits 6:7 - External Trigger Condition These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger. 00 = Low level 01 = High level 10 = Falling edge 11 = Positive edge"]
297 #[inline(always)]
298 pub fn trgcond(&mut self) -> TRGCOND_W {
299 TRGCOND_W { w: self }
300 }
301 #[doc = "Bit 8 - External Trigger Enable Enable or disable triggering of A/D conversion by external STADC pin. 1= Enable 0= Disable"]
302 #[inline(always)]
303 pub fn trgen(&mut self) -> TRGEN_W {
304 TRGEN_W { w: self }
305 }
306 #[doc = "Bit 9 - PDMA Transfer Enable 1 = Enable PDMA data transfer in ADDR 0~7 0 = Disable PDMA data transfer. When A/D conversion is completed, the converted data is loaded into ADDR 0~7, software can enable this bit to generate a PDMA data transfer request. When PTEN=1, software must set ADIE=0 to disable interrupt."]
307 #[inline(always)]
308 pub fn pten(&mut self) -> PTEN_W {
309 PTEN_W { w: self }
310 }
311 #[doc = "Bit 10 - A/D Differential Input Mode Enable 1 = A/D is in differential analog input mode 0 = A/D is in single-end analog input mode Differential input voltage (Vdiff) = Vplus - Vminus The Vplus of differential input paired channel 0 is from ADC0 pin; Vminus is from ADC1 pin. The Vplus of differential input paired channel 1 is from ADC2 pin; Vminus is from ADC3 pin. The Vplus of differential input paired channel 2 is from ADC4 pin; Vminus is from ADC5 pin. The Vplus of differential input paired channel 3 is from ADC6 pin; Vminus is from ADC7 pin. In differential input mode, only one of the two corresponding channels needs to be enabled in ADCHER. The conversion result will be placed to the corresponding data register of the enabled channel. If both channels of a differential input paired channel are enabled, the ADC will convert it twice in scan mode. And then write the conversion result to the two corresponding data registers."]
312 #[inline(always)]
313 pub fn diffen(&mut self) -> DIFFEN_W {
314 DIFFEN_W { w: self }
315 }
316 #[doc = "Bit 11 - A/D Conversion Start 1 = Conversion start. 0 = Conversion stopped and A/D converter enter idle state. ADST bit can be controlled by two sources: software write and external pin STADC. ADST is cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode on specified channels. In continuous scan mode, A/D conversion is continuously performed sequentially until this bit is cleared to 0 or chip reset."]
317 #[inline(always)]
318 pub fn adst(&mut self) -> ADST_W {
319 ADST_W { w: self }
320 }
321 #[doc = "Bit 31 - A/D differential input Mode Output Format This bit is only supported in Low Density. 1 = A/D Conversion result will be filled in RSLT at ADDRx registers with 2'complement format. 0 = A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format."]
322 #[inline(always)]
323 pub fn dmof(&mut self) -> DMOF_W {
324 DMOF_W { w: self }
325 }
326}