Struct nrf5340_net_pac::dppic_ns::chenclr::W [−][src]
pub struct W(_);
Expand description
Register CHENCLR
writer
Implementations
Bit 0 - Channel 0 enable clear register. Writing 0 has no effect.
Bit 1 - Channel 1 enable clear register. Writing 0 has no effect.
Bit 2 - Channel 2 enable clear register. Writing 0 has no effect.
Bit 3 - Channel 3 enable clear register. Writing 0 has no effect.
Bit 4 - Channel 4 enable clear register. Writing 0 has no effect.
Bit 5 - Channel 5 enable clear register. Writing 0 has no effect.
Bit 6 - Channel 6 enable clear register. Writing 0 has no effect.
Bit 7 - Channel 7 enable clear register. Writing 0 has no effect.
Bit 8 - Channel 8 enable clear register. Writing 0 has no effect.
Bit 9 - Channel 9 enable clear register. Writing 0 has no effect.
Bit 10 - Channel 10 enable clear register. Writing 0 has no effect.
Bit 11 - Channel 11 enable clear register. Writing 0 has no effect.
Bit 12 - Channel 12 enable clear register. Writing 0 has no effect.
Bit 13 - Channel 13 enable clear register. Writing 0 has no effect.
Bit 14 - Channel 14 enable clear register. Writing 0 has no effect.
Bit 15 - Channel 15 enable clear register. Writing 0 has no effect.
Methods from Deref<Target = W<CHENCLR_SPEC>>
Trait Implementations
Performs the conversion.