nrf5340_app_pac/spu_s/
intenset.rs

1#[doc = "Register `INTENSET` reader"]
2pub struct R(crate::R<INTENSET_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTENSET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTENSET_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTENSET` writer"]
17pub struct W(crate::W<INTENSET_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTENSET_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTENSET_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RAMACCERR` reader - Write '1' to enable interrupt for event RAMACCERR"]
38pub type RAMACCERR_R = crate::BitReader<RAMACCERR_A>;
39#[doc = "Write '1' to enable interrupt for event RAMACCERR\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41pub enum RAMACCERR_A {
42    #[doc = "0: Read: Disabled"]
43    DISABLED = 0,
44    #[doc = "1: Read: Enabled"]
45    ENABLED = 1,
46}
47impl From<RAMACCERR_A> for bool {
48    #[inline(always)]
49    fn from(variant: RAMACCERR_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl RAMACCERR_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> RAMACCERR_A {
57        match self.bits {
58            false => RAMACCERR_A::DISABLED,
59            true => RAMACCERR_A::ENABLED,
60        }
61    }
62    #[doc = "Checks if the value of the field is `DISABLED`"]
63    #[inline(always)]
64    pub fn is_disabled(&self) -> bool {
65        *self == RAMACCERR_A::DISABLED
66    }
67    #[doc = "Checks if the value of the field is `ENABLED`"]
68    #[inline(always)]
69    pub fn is_enabled(&self) -> bool {
70        *self == RAMACCERR_A::ENABLED
71    }
72}
73#[doc = "Write '1' to enable interrupt for event RAMACCERR\n\nValue on reset: 0"]
74#[derive(Clone, Copy, Debug, PartialEq)]
75pub enum RAMACCERR_AW {
76    #[doc = "1: Enable"]
77    SET = 1,
78}
79impl From<RAMACCERR_AW> for bool {
80    #[inline(always)]
81    fn from(variant: RAMACCERR_AW) -> Self {
82        variant as u8 != 0
83    }
84}
85#[doc = "Field `RAMACCERR` writer - Write '1' to enable interrupt for event RAMACCERR"]
86pub type RAMACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RAMACCERR_AW, O>;
87impl<'a, const O: u8> RAMACCERR_W<'a, O> {
88    #[doc = "Enable"]
89    #[inline(always)]
90    pub fn set(self) -> &'a mut W {
91        self.variant(RAMACCERR_AW::SET)
92    }
93}
94#[doc = "Field `FLASHACCERR` reader - Write '1' to enable interrupt for event FLASHACCERR"]
95pub type FLASHACCERR_R = crate::BitReader<FLASHACCERR_A>;
96#[doc = "Write '1' to enable interrupt for event FLASHACCERR\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq)]
98pub enum FLASHACCERR_A {
99    #[doc = "0: Read: Disabled"]
100    DISABLED = 0,
101    #[doc = "1: Read: Enabled"]
102    ENABLED = 1,
103}
104impl From<FLASHACCERR_A> for bool {
105    #[inline(always)]
106    fn from(variant: FLASHACCERR_A) -> Self {
107        variant as u8 != 0
108    }
109}
110impl FLASHACCERR_R {
111    #[doc = "Get enumerated values variant"]
112    #[inline(always)]
113    pub fn variant(&self) -> FLASHACCERR_A {
114        match self.bits {
115            false => FLASHACCERR_A::DISABLED,
116            true => FLASHACCERR_A::ENABLED,
117        }
118    }
119    #[doc = "Checks if the value of the field is `DISABLED`"]
120    #[inline(always)]
121    pub fn is_disabled(&self) -> bool {
122        *self == FLASHACCERR_A::DISABLED
123    }
124    #[doc = "Checks if the value of the field is `ENABLED`"]
125    #[inline(always)]
126    pub fn is_enabled(&self) -> bool {
127        *self == FLASHACCERR_A::ENABLED
128    }
129}
130#[doc = "Write '1' to enable interrupt for event FLASHACCERR\n\nValue on reset: 0"]
131#[derive(Clone, Copy, Debug, PartialEq)]
132pub enum FLASHACCERR_AW {
133    #[doc = "1: Enable"]
134    SET = 1,
135}
136impl From<FLASHACCERR_AW> for bool {
137    #[inline(always)]
138    fn from(variant: FLASHACCERR_AW) -> Self {
139        variant as u8 != 0
140    }
141}
142#[doc = "Field `FLASHACCERR` writer - Write '1' to enable interrupt for event FLASHACCERR"]
143pub type FLASHACCERR_W<'a, const O: u8> =
144    crate::BitWriter<'a, u32, INTENSET_SPEC, FLASHACCERR_AW, O>;
145impl<'a, const O: u8> FLASHACCERR_W<'a, O> {
146    #[doc = "Enable"]
147    #[inline(always)]
148    pub fn set(self) -> &'a mut W {
149        self.variant(FLASHACCERR_AW::SET)
150    }
151}
152#[doc = "Field `PERIPHACCERR` reader - Write '1' to enable interrupt for event PERIPHACCERR"]
153pub type PERIPHACCERR_R = crate::BitReader<PERIPHACCERR_A>;
154#[doc = "Write '1' to enable interrupt for event PERIPHACCERR\n\nValue on reset: 0"]
155#[derive(Clone, Copy, Debug, PartialEq)]
156pub enum PERIPHACCERR_A {
157    #[doc = "0: Read: Disabled"]
158    DISABLED = 0,
159    #[doc = "1: Read: Enabled"]
160    ENABLED = 1,
161}
162impl From<PERIPHACCERR_A> for bool {
163    #[inline(always)]
164    fn from(variant: PERIPHACCERR_A) -> Self {
165        variant as u8 != 0
166    }
167}
168impl PERIPHACCERR_R {
169    #[doc = "Get enumerated values variant"]
170    #[inline(always)]
171    pub fn variant(&self) -> PERIPHACCERR_A {
172        match self.bits {
173            false => PERIPHACCERR_A::DISABLED,
174            true => PERIPHACCERR_A::ENABLED,
175        }
176    }
177    #[doc = "Checks if the value of the field is `DISABLED`"]
178    #[inline(always)]
179    pub fn is_disabled(&self) -> bool {
180        *self == PERIPHACCERR_A::DISABLED
181    }
182    #[doc = "Checks if the value of the field is `ENABLED`"]
183    #[inline(always)]
184    pub fn is_enabled(&self) -> bool {
185        *self == PERIPHACCERR_A::ENABLED
186    }
187}
188#[doc = "Write '1' to enable interrupt for event PERIPHACCERR\n\nValue on reset: 0"]
189#[derive(Clone, Copy, Debug, PartialEq)]
190pub enum PERIPHACCERR_AW {
191    #[doc = "1: Enable"]
192    SET = 1,
193}
194impl From<PERIPHACCERR_AW> for bool {
195    #[inline(always)]
196    fn from(variant: PERIPHACCERR_AW) -> Self {
197        variant as u8 != 0
198    }
199}
200#[doc = "Field `PERIPHACCERR` writer - Write '1' to enable interrupt for event PERIPHACCERR"]
201pub type PERIPHACCERR_W<'a, const O: u8> =
202    crate::BitWriter<'a, u32, INTENSET_SPEC, PERIPHACCERR_AW, O>;
203impl<'a, const O: u8> PERIPHACCERR_W<'a, O> {
204    #[doc = "Enable"]
205    #[inline(always)]
206    pub fn set(self) -> &'a mut W {
207        self.variant(PERIPHACCERR_AW::SET)
208    }
209}
210impl R {
211    #[doc = "Bit 0 - Write '1' to enable interrupt for event RAMACCERR"]
212    #[inline(always)]
213    pub fn ramaccerr(&self) -> RAMACCERR_R {
214        RAMACCERR_R::new((self.bits & 1) != 0)
215    }
216    #[doc = "Bit 1 - Write '1' to enable interrupt for event FLASHACCERR"]
217    #[inline(always)]
218    pub fn flashaccerr(&self) -> FLASHACCERR_R {
219        FLASHACCERR_R::new(((self.bits >> 1) & 1) != 0)
220    }
221    #[doc = "Bit 2 - Write '1' to enable interrupt for event PERIPHACCERR"]
222    #[inline(always)]
223    pub fn periphaccerr(&self) -> PERIPHACCERR_R {
224        PERIPHACCERR_R::new(((self.bits >> 2) & 1) != 0)
225    }
226}
227impl W {
228    #[doc = "Bit 0 - Write '1' to enable interrupt for event RAMACCERR"]
229    #[inline(always)]
230    pub fn ramaccerr(&mut self) -> RAMACCERR_W<0> {
231        RAMACCERR_W::new(self)
232    }
233    #[doc = "Bit 1 - Write '1' to enable interrupt for event FLASHACCERR"]
234    #[inline(always)]
235    pub fn flashaccerr(&mut self) -> FLASHACCERR_W<1> {
236        FLASHACCERR_W::new(self)
237    }
238    #[doc = "Bit 2 - Write '1' to enable interrupt for event PERIPHACCERR"]
239    #[inline(always)]
240    pub fn periphaccerr(&mut self) -> PERIPHACCERR_W<2> {
241        PERIPHACCERR_W::new(self)
242    }
243    #[doc = "Writes raw bits to the register."]
244    #[inline(always)]
245    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
246        self.0.bits(bits);
247        self
248    }
249}
250#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
251pub struct INTENSET_SPEC;
252impl crate::RegisterSpec for INTENSET_SPEC {
253    type Ux = u32;
254}
255#[doc = "`read()` method returns [intenset::R](R) reader structure"]
256impl crate::Readable for INTENSET_SPEC {
257    type Reader = R;
258}
259#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
260impl crate::Writable for INTENSET_SPEC {
261    type Writer = W;
262}
263#[doc = "`reset()` method sets INTENSET to value 0"]
264impl crate::Resettable for INTENSET_SPEC {
265    #[inline(always)]
266    fn reset_value() -> Self::Ux {
267        0
268    }
269}
nrf5340_app_pac/spu_s/intenset.rs

nrf5340_app_pac/spu_s/
intenset.rs
