nrf5340_app_pac/clock_ns/
hfclkctrl.rs

1#[doc = "Register `HFCLKCTRL` reader"]
2pub struct R(crate::R<HFCLKCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HFCLKCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HFCLKCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HFCLKCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HFCLKCTRL` writer"]
17pub struct W(crate::W<HFCLKCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HFCLKCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HFCLKCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HFCLKCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `HCLK` reader - High frequency clock HCLK"]
38pub type HCLK_R = crate::FieldReader<u8, HCLK_A>;
39#[doc = "High frequency clock HCLK\n\nValue on reset: 1"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41#[repr(u8)]
42pub enum HCLK_A {
43    #[doc = "0: Divide HFCLK by 1"]
44    DIV1 = 0,
45    #[doc = "1: Divide HFCLK by 2"]
46    DIV2 = 1,
47}
48impl From<HCLK_A> for u8 {
49    #[inline(always)]
50    fn from(variant: HCLK_A) -> Self {
51        variant as _
52    }
53}
54impl HCLK_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> Option<HCLK_A> {
58        match self.bits {
59            0 => Some(HCLK_A::DIV1),
60            1 => Some(HCLK_A::DIV2),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `DIV1`"]
65    #[inline(always)]
66    pub fn is_div1(&self) -> bool {
67        *self == HCLK_A::DIV1
68    }
69    #[doc = "Checks if the value of the field is `DIV2`"]
70    #[inline(always)]
71    pub fn is_div2(&self) -> bool {
72        *self == HCLK_A::DIV2
73    }
74}
75#[doc = "Field `HCLK` writer - High frequency clock HCLK"]
76pub type HCLK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HFCLKCTRL_SPEC, u8, HCLK_A, 2, O>;
77impl<'a, const O: u8> HCLK_W<'a, O> {
78    #[doc = "Divide HFCLK by 1"]
79    #[inline(always)]
80    pub fn div1(self) -> &'a mut W {
81        self.variant(HCLK_A::DIV1)
82    }
83    #[doc = "Divide HFCLK by 2"]
84    #[inline(always)]
85    pub fn div2(self) -> &'a mut W {
86        self.variant(HCLK_A::DIV2)
87    }
88}
89impl R {
90    #[doc = "Bits 0:1 - High frequency clock HCLK"]
91    #[inline(always)]
92    pub fn hclk(&self) -> HCLK_R {
93        HCLK_R::new((self.bits & 3) as u8)
94    }
95}
96impl W {
97    #[doc = "Bits 0:1 - High frequency clock HCLK"]
98    #[inline(always)]
99    pub fn hclk(&mut self) -> HCLK_W<0> {
100        HCLK_W::new(self)
101    }
102    #[doc = "Writes raw bits to the register."]
103    #[inline(always)]
104    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
105        self.0.bits(bits);
106        self
107    }
108}
109#[doc = "HFCLK128M frequency configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfclkctrl](index.html) module"]
110pub struct HFCLKCTRL_SPEC;
111impl crate::RegisterSpec for HFCLKCTRL_SPEC {
112    type Ux = u32;
113}
114#[doc = "`read()` method returns [hfclkctrl::R](R) reader structure"]
115impl crate::Readable for HFCLKCTRL_SPEC {
116    type Reader = R;
117}
118#[doc = "`write(|w| ..)` method takes [hfclkctrl::W](W) writer structure"]
119impl crate::Writable for HFCLKCTRL_SPEC {
120    type Writer = W;
121}
122#[doc = "`reset()` method sets HFCLKCTRL to value 0x01"]
123impl crate::Resettable for HFCLKCTRL_SPEC {
124    #[inline(always)]
125    fn reset_value() -> Self::Ux {
126        0x01
127    }
128}
nrf5340_app_pac/clock_ns/hfclkctrl.rs

nrf5340_app_pac/clock_ns/
hfclkctrl.rs
