Struct nrf5340_app_pac::cti_s::RegisterBlock

source · [−]
#[repr(C)]
pub struct RegisterBlock {
Show 26 fields
    pub cticontrol: CTICONTROL,
    pub ctiintack: CTIINTACK,
    pub ctiappset: CTIAPPSET,
    pub ctiappclear: CTIAPPCLEAR,
    pub ctiapppulse: CTIAPPPULSE,
    pub ctiinen: [CTIINEN; 8],
    pub ctiouten: [CTIOUTEN; 8],
    pub ctitriginstatus: CTITRIGINSTATUS,
    pub ctitrigoutstatus: CTITRIGOUTSTATUS,
    pub ctichinstatus: CTICHINSTATUS,
    pub ctigate: CTIGATE,
    pub devarch: DEVARCH,
    pub devid: DEVID,
    pub devtype: DEVTYPE,
    pub pidr4: PIDR4,
    pub pidr5: PIDR5,
    pub pidr6: PIDR6,
    pub pidr7: PIDR7,
    pub pidr0: PIDR0,
    pub pidr1: PIDR1,
    pub pidr2: PIDR2,
    pub pidr3: PIDR3,
    pub cidr0: CIDR0,
    pub cidr1: CIDR1,
    pub cidr2: CIDR2,
    pub cidr3: CIDR3,
    /* private fields */

}
Expand description

Register block

Fields

cticontrol: CTICONTROL

0x00 - CTI Control register

ctiintack: CTIINTACK

0x10 - CTI Interrupt Acknowledge register

ctiappset: CTIAPPSET

0x14 - CTI Application Trigger Set register

ctiappclear: CTIAPPCLEAR

0x18 - CTI Application Trigger Clear register

ctiapppulse: CTIAPPPULSE

0x1c - CTI Application Pulse register

ctiinen: [CTIINEN; 8]

0x20..0x40 - Description collection: CTI Trigger input

ctiouten: [CTIOUTEN; 8]

0xa0..0xc0 - Description collection: CTI Trigger output

ctitriginstatus: CTITRIGINSTATUS

0x130 - CTI Trigger In Status register

ctitrigoutstatus: CTITRIGOUTSTATUS

0x134 - CTI Trigger Out Status register

ctichinstatus: CTICHINSTATUS

0x138 - CTI Channel In Status register

ctigate: CTIGATE

0x140 - Enable CTI Channel Gate register

devarch: DEVARCH

0xfbc - Device Architecture register

devid: DEVID

0xfc8 - Device Configuration register

devtype: DEVTYPE

0xfcc - Device Type Identifier register

pidr4: PIDR4

0xfd0 - Peripheral ID4 Register

pidr5: PIDR5

0xfd4 - Peripheral ID5 register

pidr6: PIDR6

0xfd8 - Peripheral ID6 register

pidr7: PIDR7

0xfdc - Peripheral ID7 register

pidr0: PIDR0

0xfe0 - Peripheral ID0 Register

pidr1: PIDR1

0xfe4 - Peripheral ID1 Register

pidr2: PIDR2

0xfe8 - Peripheral ID2 Register

pidr3: PIDR3

0xfec - Peripheral ID3 Register

cidr0: CIDR0

0xff0 - Component ID0 Register

cidr1: CIDR1

0xff4 - Component ID1 Register

cidr2: CIDR2

0xff8 - Component ID2 Register

cidr3: CIDR3

0xffc - Component ID3 Register

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