nrf5340_app_pac/tad_s/
traceportspeed.rs

1#[doc = "Register `TRACEPORTSPEED` reader"]
2pub struct R(crate::R<TRACEPORTSPEED_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TRACEPORTSPEED_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TRACEPORTSPEED_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TRACEPORTSPEED_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TRACEPORTSPEED` writer"]
17pub struct W(crate::W<TRACEPORTSPEED_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TRACEPORTSPEED_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TRACEPORTSPEED_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TRACEPORTSPEED_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TRACEPORTSPEED` reader - Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock."]
38pub type TRACEPORTSPEED_R = crate::FieldReader<u8, TRACEPORTSPEED_A>;
39#[doc = "Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41#[repr(u8)]
42pub enum TRACEPORTSPEED_A {
43    #[doc = "0: Trace Port clock is: 64MHz"]
44    _64MHZ = 0,
45    #[doc = "1: Trace Port clock is: 32MHz"]
46    _32MHZ = 1,
47    #[doc = "2: Trace Port clock is: 16MHz"]
48    _16MHZ = 2,
49    #[doc = "3: Trace Port clock is: 8MHz"]
50    _8MHZ = 3,
51}
52impl From<TRACEPORTSPEED_A> for u8 {
53    #[inline(always)]
54    fn from(variant: TRACEPORTSPEED_A) -> Self {
55        variant as _
56    }
57}
58impl TRACEPORTSPEED_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> TRACEPORTSPEED_A {
62        match self.bits {
63            0 => TRACEPORTSPEED_A::_64MHZ,
64            1 => TRACEPORTSPEED_A::_32MHZ,
65            2 => TRACEPORTSPEED_A::_16MHZ,
66            3 => TRACEPORTSPEED_A::_8MHZ,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `_64MHZ`"]
71    #[inline(always)]
72    pub fn is_64mhz(&self) -> bool {
73        *self == TRACEPORTSPEED_A::_64MHZ
74    }
75    #[doc = "Checks if the value of the field is `_32MHZ`"]
76    #[inline(always)]
77    pub fn is_32mhz(&self) -> bool {
78        *self == TRACEPORTSPEED_A::_32MHZ
79    }
80    #[doc = "Checks if the value of the field is `_16MHZ`"]
81    #[inline(always)]
82    pub fn is_16mhz(&self) -> bool {
83        *self == TRACEPORTSPEED_A::_16MHZ
84    }
85    #[doc = "Checks if the value of the field is `_8MHZ`"]
86    #[inline(always)]
87    pub fn is_8mhz(&self) -> bool {
88        *self == TRACEPORTSPEED_A::_8MHZ
89    }
90}
91#[doc = "Field `TRACEPORTSPEED` writer - Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock."]
92pub type TRACEPORTSPEED_W<'a, const O: u8> =
93    crate::FieldWriterSafe<'a, u32, TRACEPORTSPEED_SPEC, u8, TRACEPORTSPEED_A, 2, O>;
94impl<'a, const O: u8> TRACEPORTSPEED_W<'a, O> {
95    #[doc = "Trace Port clock is: 64MHz"]
96    #[inline(always)]
97    pub fn _64mhz(self) -> &'a mut W {
98        self.variant(TRACEPORTSPEED_A::_64MHZ)
99    }
100    #[doc = "Trace Port clock is: 32MHz"]
101    #[inline(always)]
102    pub fn _32mhz(self) -> &'a mut W {
103        self.variant(TRACEPORTSPEED_A::_32MHZ)
104    }
105    #[doc = "Trace Port clock is: 16MHz"]
106    #[inline(always)]
107    pub fn _16mhz(self) -> &'a mut W {
108        self.variant(TRACEPORTSPEED_A::_16MHZ)
109    }
110    #[doc = "Trace Port clock is: 8MHz"]
111    #[inline(always)]
112    pub fn _8mhz(self) -> &'a mut W {
113        self.variant(TRACEPORTSPEED_A::_8MHZ)
114    }
115}
116impl R {
117    #[doc = "Bits 0:1 - Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock."]
118    #[inline(always)]
119    pub fn traceportspeed(&self) -> TRACEPORTSPEED_R {
120        TRACEPORTSPEED_R::new((self.bits & 3) as u8)
121    }
122}
123impl W {
124    #[doc = "Bits 0:1 - Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock."]
125    #[inline(always)]
126    pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W<0> {
127        TRACEPORTSPEED_W::new(self)
128    }
129    #[doc = "Writes raw bits to the register."]
130    #[inline(always)]
131    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
132        self.0.bits(bits);
133        self
134    }
135}
136#[doc = "Clocking options for the Trace Port debug interface Reset behavior is the same as debug components\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [traceportspeed](index.html) module"]
137pub struct TRACEPORTSPEED_SPEC;
138impl crate::RegisterSpec for TRACEPORTSPEED_SPEC {
139    type Ux = u32;
140}
141#[doc = "`read()` method returns [traceportspeed::R](R) reader structure"]
142impl crate::Readable for TRACEPORTSPEED_SPEC {
143    type Reader = R;
144}
145#[doc = "`write(|w| ..)` method takes [traceportspeed::W](W) writer structure"]
146impl crate::Writable for TRACEPORTSPEED_SPEC {
147    type Writer = W;
148}
149#[doc = "`reset()` method sets TRACEPORTSPEED to value 0"]
150impl crate::Resettable for TRACEPORTSPEED_SPEC {
151    #[inline(always)]
152    fn reset_value() -> Self::Ux {
153        0
154    }
155}
nrf5340_app_pac/tad_s/traceportspeed.rs

nrf5340_app_pac/tad_s/
traceportspeed.rs
