Struct nrf52svd::Peripherals

pub struct Peripherals<'a> {
    pub CPUID: &'a CPUID,
    pub DCB: &'a DCB,
    pub DWT: &'a DWT,
    pub FPB: &'a FPB,
    pub FPU: &'a FPU,
    pub ITM: &'a ITM,
    pub MPU: &'a MPU,
    pub NVIC: &'a NVIC,
    pub SCB: &'a SCB,
    pub SYST: &'a SYST,
    pub TPIU: &'a TPIU,
    pub FICR: &'a FICR,
    pub UICR: &'a UICR,
    pub BPROT: &'a BPROT,
    pub POWER: &'a POWER,
    pub CLOCK: &'a CLOCK,
    pub RADIO: &'a RADIO,
    pub UARTE0: &'a UARTE0,
    pub UART0: &'a UART0,
    pub SPIM0: &'a SPIM0,
    pub SPIS0: &'a SPIS0,
    pub TWIM0: &'a TWIM0,
    pub TWIS0: &'a TWIS0,
    pub SPI0: &'a SPI0,
    pub TWI0: &'a TWI0,
    pub SPIM1: &'a SPIM1,
    pub SPIS1: &'a SPIS1,
    pub TWIM1: &'a TWIM1,
    pub TWIS1: &'a TWIS1,
    pub SPI1: &'a SPI1,
    pub TWI1: &'a TWI1,
    pub NFCT: &'a NFCT,
    pub GPIOTE: &'a GPIOTE,
    pub SAADC: &'a SAADC,
    pub TIMER0: &'a TIMER0,
    pub TIMER1: &'a TIMER1,
    pub TIMER2: &'a TIMER2,
    pub RTC0: &'a RTC0,
    pub TEMP: &'a TEMP,
    pub RNG: &'a RNG,
    pub ECB: &'a ECB,
    pub CCM: &'a CCM,
    pub AAR: &'a AAR,
    pub WDT: &'a WDT,
    pub RTC1: &'a RTC1,
    pub QDEC: &'a QDEC,
    pub COMP: &'a COMP,
    pub LPCOMP: &'a LPCOMP,
    pub SWI0: &'a SWI0,
    pub EGU0: &'a EGU0,
    pub SWI1: &'a SWI1,
    pub EGU1: &'a EGU1,
    pub SWI2: &'a SWI2,
    pub EGU2: &'a EGU2,
    pub SWI3: &'a SWI3,
    pub EGU3: &'a EGU3,
    pub SWI4: &'a SWI4,
    pub EGU4: &'a EGU4,
    pub SWI5: &'a SWI5,
    pub EGU5: &'a EGU5,
    pub TIMER3: &'a TIMER3,
    pub TIMER4: &'a TIMER4,
    pub PWM0: &'a PWM0,
    pub PDM: &'a PDM,
    pub NVMC: &'a NVMC,
    pub PPI: &'a PPI,
    pub MWU: &'a MWU,
    pub PWM1: &'a PWM1,
    pub PWM2: &'a PWM2,
    pub SPIM2: &'a SPIM2,
    pub SPIS2: &'a SPIS2,
    pub SPI2: &'a SPI2,
    pub RTC2: &'a RTC2,
    pub I2S: &'a I2S,
    pub P0: &'a P0,
}

All the peripherals

Fields

CPUID: &'a CPUID

CPUID

DCB: &'a DCB

DCB

DWT: &'a DWT

DWT

FPB: &'a FPB

FPB

FPU: &'a FPU

FPU

ITM: &'a ITM

ITM

MPU: &'a MPU

MPU

NVIC: &'a NVIC

NVIC

SCB: &'a SCB

SCB

SYST: &'a SYST

SYST

TPIU: &'a TPIU

TPIU

FICR: &'a FICR

FICR

UICR: &'a UICR

UICR

BPROT: &'a BPROT

BPROT

POWER: &'a POWER

POWER

CLOCK: &'a CLOCK

CLOCK

RADIO: &'a RADIO

RADIO

UARTE0: &'a UARTE0

UARTE0

UART0: &'a UART0

UART0

SPIM0: &'a SPIM0

SPIM0

SPIS0: &'a SPIS0

SPIS0

TWIM0: &'a TWIM0

TWIM0

TWIS0: &'a TWIS0

TWIS0

SPI0: &'a SPI0

SPI0

TWI0: &'a TWI0

TWI0

SPIM1: &'a SPIM1

SPIM1

SPIS1: &'a SPIS1

SPIS1

TWIM1: &'a TWIM1

TWIM1

TWIS1: &'a TWIS1

TWIS1

SPI1: &'a SPI1

SPI1

TWI1: &'a TWI1

TWI1

NFCT: &'a NFCT

NFCT

GPIOTE: &'a GPIOTE

GPIOTE

SAADC: &'a SAADC

SAADC

TIMER0: &'a TIMER0

TIMER0

TIMER1: &'a TIMER1

TIMER1

TIMER2: &'a TIMER2

TIMER2

RTC0: &'a RTC0

RTC0

TEMP: &'a TEMP

TEMP

RNG: &'a RNG

RNG

ECB: &'a ECB

ECB

CCM: &'a CCM

CCM

AAR: &'a AAR

AAR

WDT: &'a WDT

WDT

RTC1: &'a RTC1

RTC1

QDEC: &'a QDEC

QDEC

COMP: &'a COMP

COMP

LPCOMP: &'a LPCOMP

LPCOMP

SWI0: &'a SWI0

SWI0

EGU0: &'a EGU0

EGU0

SWI1: &'a SWI1

SWI1

EGU1: &'a EGU1

EGU1

SWI2: &'a SWI2

SWI2

EGU2: &'a EGU2

EGU2

SWI3: &'a SWI3

SWI3

EGU3: &'a EGU3

EGU3

SWI4: &'a SWI4

SWI4

EGU4: &'a EGU4

EGU4

SWI5: &'a SWI5

SWI5

EGU5: &'a EGU5

EGU5

TIMER3: &'a TIMER3

TIMER3

TIMER4: &'a TIMER4

TIMER4

PWM0: &'a PWM0

PWM0

PDM: &'a PDM

PDM

NVMC: &'a NVMC

NVMC

PPI: &'a PPI

PPI

MWU: &'a MWU

MWU

PWM1: &'a PWM1

PWM1

PWM2: &'a PWM2

PWM2

SPIM2: &'a SPIM2

SPIM2

SPIS2: &'a SPIS2

SPIS2

SPI2: &'a SPI2

SPI2

RTC2: &'a RTC2

RTC2

I2S: &'a I2S

I2S

P0: &'a P0

P0

Methods

impl<'a> Peripherals<'a>

unsafe fn all() -> Self

Grants access to all the peripherals