Struct nrf52840_hal::pac::radio::intenclr::W

pub struct W(/* private fields */);

Register INTENCLR writer

Implementations

impl W

pub fn ready( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, READY_AW, BitM, 0>

Bit 0 - Write ‘1’ to disable interrupt for READY event

pub fn address( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, ADDRESS_AW, BitM, 1>

Bit 1 - Write ‘1’ to disable interrupt for ADDRESS event

pub fn payload( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, PAYLOAD_AW, BitM, 2>

Bit 2 - Write ‘1’ to disable interrupt for PAYLOAD event

pub fn end(&mut self) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, END_AW, BitM, 3>

Bit 3 - Write ‘1’ to disable interrupt for END event

pub fn disabled( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, DISABLED_AW, BitM, 4>

Bit 4 - Write ‘1’ to disable interrupt for DISABLED event

pub fn devmatch( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, DEVMATCH_AW, BitM, 5>

Bit 5 - Write ‘1’ to disable interrupt for DEVMATCH event

pub fn devmiss( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, DEVMISS_AW, BitM, 6>

Bit 6 - Write ‘1’ to disable interrupt for DEVMISS event

pub fn rssiend( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, RSSIEND_AW, BitM, 7>

Bit 7 - Write ‘1’ to disable interrupt for RSSIEND event

pub fn bcmatch( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, BCMATCH_AW, BitM, 10>

Bit 10 - Write ‘1’ to disable interrupt for BCMATCH event

pub fn crcok( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, CRCOK_AW, BitM, 12>

Bit 12 - Write ‘1’ to disable interrupt for CRCOK event

pub fn crcerror( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, CRCERROR_AW, BitM, 13>

Bit 13 - Write ‘1’ to disable interrupt for CRCERROR event

pub fn framestart( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, FRAMESTART_AW, BitM, 14>

Bit 14 - Write ‘1’ to disable interrupt for FRAMESTART event

pub fn edend( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, EDEND_AW, BitM, 15>

Bit 15 - Write ‘1’ to disable interrupt for EDEND event

pub fn edstopped( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, EDSTOPPED_AW, BitM, 16>

Bit 16 - Write ‘1’ to disable interrupt for EDSTOPPED event

pub fn ccaidle( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, CCAIDLE_AW, BitM, 17>

Bit 17 - Write ‘1’ to disable interrupt for CCAIDLE event

pub fn ccabusy( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, CCABUSY_AW, BitM, 18>

Bit 18 - Write ‘1’ to disable interrupt for CCABUSY event

pub fn ccastopped( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, CCASTOPPED_AW, BitM, 19>

Bit 19 - Write ‘1’ to disable interrupt for CCASTOPPED event

pub fn rateboost( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, RATEBOOST_AW, BitM, 20>

Bit 20 - Write ‘1’ to disable interrupt for RATEBOOST event

pub fn txready( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, TXREADY_AW, BitM, 21>

Bit 21 - Write ‘1’ to disable interrupt for TXREADY event

pub fn rxready( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, RXREADY_AW, BitM, 22>

Bit 22 - Write ‘1’ to disable interrupt for RXREADY event

pub fn mhrmatch( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, MHRMATCH_AW, BitM, 23>

Bit 23 - Write ‘1’ to disable interrupt for MHRMATCH event

pub fn phyend( &mut self ) -> BitWriterRaw<'_, u32, INTENCLR_SPEC, PHYEND_AW, BitM, 27>

Bit 27 - Write ‘1’ to disable interrupt for PHYEND event

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<INTENCLR_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<INTENCLR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<INTENCLR_SPEC>> for W

fn from(writer: W<INTENCLR_SPEC>) -> W

Converts to this type from the input type.