#[repr(C)]
pub struct RegisterBlock {
Show 27 fields pub tasks_startrx: TASKS_STARTRX, pub tasks_stoprx: TASKS_STOPRX, pub tasks_starttx: TASKS_STARTTX, pub tasks_stoptx: TASKS_STOPTX, pub tasks_flushrx: TASKS_FLUSHRX, pub events_cts: EVENTS_CTS, pub events_ncts: EVENTS_NCTS, pub events_rxdrdy: EVENTS_RXDRDY, pub events_endrx: EVENTS_ENDRX, pub events_txdrdy: EVENTS_TXDRDY, pub events_endtx: EVENTS_ENDTX, pub events_error: EVENTS_ERROR, pub events_rxto: EVENTS_RXTO, pub events_rxstarted: EVENTS_RXSTARTED, pub events_txstarted: EVENTS_TXSTARTED, pub events_txstopped: EVENTS_TXSTOPPED, pub shorts: SHORTS, pub inten: INTEN, pub intenset: INTENSET, pub intenclr: INTENCLR, pub errorsrc: ERRORSRC, pub enable: ENABLE, pub psel: PSEL, pub baudrate: BAUDRATE, pub rxd: RXD, pub txd: TXD, pub config: CONFIG, /* private fields */
}
Expand description

Register block

Fields

tasks_startrx: TASKS_STARTRX

0x00 - Start UART receiver

tasks_stoprx: TASKS_STOPRX

0x04 - Stop UART receiver

tasks_starttx: TASKS_STARTTX

0x08 - Start UART transmitter

tasks_stoptx: TASKS_STOPTX

0x0c - Stop UART transmitter

tasks_flushrx: TASKS_FLUSHRX

0x2c - Flush RX FIFO into RX buffer

events_cts: EVENTS_CTS

0x100 - CTS is activated (set low). Clear To Send.

events_ncts: EVENTS_NCTS

0x104 - CTS is deactivated (set high). Not Clear To Send.

events_rxdrdy: EVENTS_RXDRDY

0x108 - Data received in RXD (but potentially not yet transferred to Data RAM)

events_endrx: EVENTS_ENDRX

0x110 - Receive buffer is filled up

events_txdrdy: EVENTS_TXDRDY

0x11c - Data sent from TXD

events_endtx: EVENTS_ENDTX

0x120 - Last TX byte transmitted

events_error: EVENTS_ERROR

0x124 - Error detected

events_rxto: EVENTS_RXTO

0x144 - Receiver timeout

events_rxstarted: EVENTS_RXSTARTED

0x14c - UART receiver has started

events_txstarted: EVENTS_TXSTARTED

0x150 - UART transmitter has started

events_txstopped: EVENTS_TXSTOPPED

0x158 - Transmitter stopped

shorts: SHORTS

0x200 - Shortcuts between local events and tasks

inten: INTEN

0x300 - Enable or disable interrupt

intenset: INTENSET

0x304 - Enable interrupt

intenclr: INTENCLR

0x308 - Disable interrupt

errorsrc: ERRORSRC

0x480 - Error source Note : this register is read / write one to clear.

enable: ENABLE

0x500 - Enable UART

psel: PSEL

0x508..0x518 - Unspecified

baudrate: BAUDRATE

0x524 - Baud rate. Accuracy depends on the HFCLK source selected.

rxd: RXD

0x534..0x540 - RXD EasyDMA channel

txd: TXD

0x544..0x550 - TXD EasyDMA channel

config: CONFIG

0x56c - Configuration of parity and hardware flow control

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