Struct nrf52833_hal::pac::spim0::iftiming::rxdelay::W[][src]

pub struct W(_);
Expand description

Register RXDELAY writer

Implementations

Bits 0:2 - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK.

Writes raw bits to the register.

Methods from Deref<Target = W<RXDELAY_SPEC>>

Writes raw bits to the register.

Trait Implementations

The resulting type after dereferencing.

Dereferences the value.

Mutably dereferences the value.

Performs the conversion.

Auto Trait Implementations

Blanket Implementations

Gets the TypeId of self. Read more

Casts the value.

Immutably borrows from an owned value. Read more

Mutably borrows from an owned value. Read more

Casts the value.

Performs the conversion.

Performs the conversion.

Performs the conversion.

Performs the conversion.

Casts the value.

Should always be Self

Casts the value.

The type returned in the event of a conversion error.

Performs the conversion.

The type returned in the event of a conversion error.

Performs the conversion.

Casts the value.

Casts the value.