Struct nrf52833_hal::pac::egu0::inten::W

pub struct W(_);

Register INTEN writer

Implementations

impl W

pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>

Bit 0 - Enable or disable interrupt for event TRIGGERED[0]

pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>

Bit 1 - Enable or disable interrupt for event TRIGGERED[1]

pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>

Bit 2 - Enable or disable interrupt for event TRIGGERED[2]

pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>

Bit 3 - Enable or disable interrupt for event TRIGGERED[3]

pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>

Bit 4 - Enable or disable interrupt for event TRIGGERED[4]

pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>

Bit 5 - Enable or disable interrupt for event TRIGGERED[5]

pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>

Bit 6 - Enable or disable interrupt for event TRIGGERED[6]

pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>

Bit 7 - Enable or disable interrupt for event TRIGGERED[7]

pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>

Bit 8 - Enable or disable interrupt for event TRIGGERED[8]

pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>

Bit 9 - Enable or disable interrupt for event TRIGGERED[9]

pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>

Bit 10 - Enable or disable interrupt for event TRIGGERED[10]

pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>

Bit 11 - Enable or disable interrupt for event TRIGGERED[11]

pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>

Bit 12 - Enable or disable interrupt for event TRIGGERED[12]

pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>

Bit 13 - Enable or disable interrupt for event TRIGGERED[13]

pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>

Bit 14 - Enable or disable interrupt for event TRIGGERED[14]

pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>

Bit 15 - Enable or disable interrupt for event TRIGGERED[15]

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<INTEN_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<INTEN_SPEC>

The resulting type after dereferencing.

pub fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

pub fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<INTEN_SPEC>> for W

pub fn from(writer: W<INTEN_SPEC>) -> W

Performs the conversion.