Crate nrf52820_pac

Crate nrf52820_pac 

Source
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Peripheral access API for NRF52820 microcontrollers (generated using svd2rust v0.25.1 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

pub use spi0 as spi1;
pub use spim0 as spim1;
pub use spis0 as spis1;
pub use twi0 as twi1;
pub use twim0 as twim1;
pub use twis0 as twis1;
pub use timer0 as timer1;
pub use timer0 as timer2;
pub use rtc0 as rtc1;
pub use egu0 as egu1;
pub use swi0 as swi1;
pub use egu0 as egu2;
pub use swi0 as swi2;
pub use egu0 as egu3;
pub use swi0 as swi3;
pub use egu0 as egu4;
pub use swi0 as swi4;
pub use egu0 as egu5;
pub use swi0 as swi5;
pub use timer0 as timer3;

Modules§

aar
Accelerated Address Resolver
acl
Access control lists
approtect
Access Port Protection
ccm
AES CCM Mode Encryption
clock
Clock control
comp
Comparator
ecb
AES ECB Mode Encryption
egu0
Event generator unit 0
ficr
Factory information configuration registers
generic
Common register and bit access and modify traits
gpiote
GPIO Tasks and Events
nvmc
Non Volatile Memory Controller
p0
GPIO Port 1
power
Power control
ppi
Programmable Peripheral Interconnect
qdec
Quadrature Decoder
radio
2.4 GHz radio
rng
Random Number Generator
rtc0
Real time counter 0
spi0
Serial Peripheral Interface 0
spim0
Serial Peripheral Interface Master with EasyDMA 0
spis0
SPI Slave 0
swi0
Software interrupt 0
temp
Temperature Sensor
timer0
Timer/Counter 0
twi0
I2C compatible Two-Wire Interface 0
twim0
I2C compatible Two-Wire Master Interface with EasyDMA 0
twis0
I2C compatible Two-Wire Slave Interface with EasyDMA 0
uart0
Universal Asynchronous Receiver/Transmitter
uarte0
UART with EasyDMA
uicr
User information configuration registers
usbd
Universal serial bus device
wdt
Watchdog Timer

Structs§

AAR
Accelerated Address Resolver
ACL
Access control lists
APPROTECT
Access Port Protection
CBP
Cache and branch predictor maintenance operations
CCM
AES CCM Mode Encryption
CLOCK
Clock control
COMP
Comparator
CPUID
CPUID
CorePeripherals
Core peripherals
DCB
Debug Control Block
DWT
Data Watchpoint and Trace unit
ECB
AES ECB Mode Encryption
EGU0
Event generator unit 0
EGU1
Event generator unit 1
EGU2
Event generator unit 2
EGU3
Event generator unit 3
EGU4
Event generator unit 4
EGU5
Event generator unit 5
FICR
Factory information configuration registers
FPB
Flash Patch and Breakpoint unit
GPIOTE
GPIO Tasks and Events
ITM
Instrumentation Trace Macrocell
MPU
Memory Protection Unit
NVIC
Nested Vector Interrupt Controller
NVMC
Non Volatile Memory Controller
P0
GPIO Port 1
POWER
Power control
PPI
Programmable Peripheral Interconnect
Peripherals
All the peripherals
QDEC
Quadrature Decoder
RADIO
2.4 GHz radio
RNG
Random Number Generator
RTC0
Real time counter 0
RTC1
Real time counter 1
SCB
System Control Block
SPI0
Serial Peripheral Interface 0
SPI1
Serial Peripheral Interface 1
SPIM0
Serial Peripheral Interface Master with EasyDMA 0
SPIM1
Serial Peripheral Interface Master with EasyDMA 1
SPIS0
SPI Slave 0
SPIS1
SPI Slave 1
SWI0
Software interrupt 0
SWI1
Software interrupt 1
SWI2
Software interrupt 2
SWI3
Software interrupt 3
SWI4
Software interrupt 4
SWI5
Software interrupt 5
SYST
SysTick: System Timer
TEMP
Temperature Sensor
TIMER0
Timer/Counter 0
TIMER1
Timer/Counter 1
TIMER2
Timer/Counter 2
TIMER3
Timer/Counter 3
TPIU
Trace Port Interface Unit
TWI0
I2C compatible Two-Wire Interface 0
TWI1
I2C compatible Two-Wire Interface 1
TWIM0
I2C compatible Two-Wire Master Interface with EasyDMA 0
TWIM1
I2C compatible Two-Wire Master Interface with EasyDMA 1
TWIS0
I2C compatible Two-Wire Slave Interface with EasyDMA 0
TWIS1
I2C compatible Two-Wire Slave Interface with EasyDMA 1
UART0
Universal Asynchronous Receiver/Transmitter
UARTE0
UART with EasyDMA
UICR
User information configuration registers
USBD
Universal serial bus device
WDT
Watchdog Timer

Enums§

Interrupt
Enumeration of all the interrupts.

Constants§

NVIC_PRIO_BITS
Number available in the NVIC for configuring priority