Struct nrf52811_pac::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _NRFFW>>

pub fn nrffw(&mut self) -> NRFFW_W<'_>

Bits 0:31 - Reserved for Nordic firmware design

impl W<u32, Reg<u32, _NRFHW>>

pub fn nrfhw(&mut self) -> NRFHW_W<'_>

Bits 0:31 - Reserved for Nordic hardware design

impl W<u32, Reg<u32, _CUSTOMER>>

pub fn customer(&mut self) -> CUSTOMER_W<'_>

Bits 0:31 - Reserved for customer

impl W<u32, Reg<u32, _PSELRESET>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - GPIO pin number onto which nRESET is exposed

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _APPROTECT>>

pub fn pall(&mut self) -> PALL_W<'_>

Bits 0:7 - Enable or disable access port protection.

impl W<u32, Reg<u32, _CONFIG0>>

pub fn region0(&mut self) -> REGION0_W<'_>

Bit 0 - Enable protection for region 0. Write '0' has no effect.

pub fn region1(&mut self) -> REGION1_W<'_>

Bit 1 - Enable protection for region 1. Write '0' has no effect.

pub fn region2(&mut self) -> REGION2_W<'_>

Bit 2 - Enable protection for region 2. Write '0' has no effect.

pub fn region3(&mut self) -> REGION3_W<'_>

Bit 3 - Enable protection for region 3. Write '0' has no effect.

pub fn region4(&mut self) -> REGION4_W<'_>

Bit 4 - Enable protection for region 4. Write '0' has no effect.

pub fn region5(&mut self) -> REGION5_W<'_>

Bit 5 - Enable protection for region 5. Write '0' has no effect.

pub fn region6(&mut self) -> REGION6_W<'_>

Bit 6 - Enable protection for region 6. Write '0' has no effect.

pub fn region7(&mut self) -> REGION7_W<'_>

Bit 7 - Enable protection for region 7. Write '0' has no effect.

pub fn region8(&mut self) -> REGION8_W<'_>

Bit 8 - Enable protection for region 8. Write '0' has no effect.

pub fn region9(&mut self) -> REGION9_W<'_>

Bit 9 - Enable protection for region 9. Write '0' has no effect.

pub fn region10(&mut self) -> REGION10_W<'_>

Bit 10 - Enable protection for region 10. Write '0' has no effect.

pub fn region11(&mut self) -> REGION11_W<'_>

Bit 11 - Enable protection for region 11. Write '0' has no effect.

pub fn region12(&mut self) -> REGION12_W<'_>

Bit 12 - Enable protection for region 12. Write '0' has no effect.

pub fn region13(&mut self) -> REGION13_W<'_>

Bit 13 - Enable protection for region 13. Write '0' has no effect.

pub fn region14(&mut self) -> REGION14_W<'_>

Bit 14 - Enable protection for region 14. Write '0' has no effect.

pub fn region15(&mut self) -> REGION15_W<'_>

Bit 15 - Enable protection for region 15. Write '0' has no effect.

pub fn region16(&mut self) -> REGION16_W<'_>

Bit 16 - Enable protection for region 16. Write '0' has no effect.

pub fn region17(&mut self) -> REGION17_W<'_>

Bit 17 - Enable protection for region 17. Write '0' has no effect.

pub fn region18(&mut self) -> REGION18_W<'_>

Bit 18 - Enable protection for region 18. Write '0' has no effect.

pub fn region19(&mut self) -> REGION19_W<'_>

Bit 19 - Enable protection for region 19. Write '0' has no effect.

pub fn region20(&mut self) -> REGION20_W<'_>

Bit 20 - Enable protection for region 20. Write '0' has no effect.

pub fn region21(&mut self) -> REGION21_W<'_>

Bit 21 - Enable protection for region 21. Write '0' has no effect.

pub fn region22(&mut self) -> REGION22_W<'_>

Bit 22 - Enable protection for region 22. Write '0' has no effect.

pub fn region23(&mut self) -> REGION23_W<'_>

Bit 23 - Enable protection for region 23. Write '0' has no effect.

pub fn region24(&mut self) -> REGION24_W<'_>

Bit 24 - Enable protection for region 24. Write '0' has no effect.

pub fn region25(&mut self) -> REGION25_W<'_>

Bit 25 - Enable protection for region 25. Write '0' has no effect.

pub fn region26(&mut self) -> REGION26_W<'_>

Bit 26 - Enable protection for region 26. Write '0' has no effect.

pub fn region27(&mut self) -> REGION27_W<'_>

Bit 27 - Enable protection for region 27. Write '0' has no effect.

pub fn region28(&mut self) -> REGION28_W<'_>

Bit 28 - Enable protection for region 28. Write '0' has no effect.

pub fn region29(&mut self) -> REGION29_W<'_>

Bit 29 - Enable protection for region 29. Write '0' has no effect.

pub fn region30(&mut self) -> REGION30_W<'_>

Bit 30 - Enable protection for region 30. Write '0' has no effect.

pub fn region31(&mut self) -> REGION31_W<'_>

Bit 31 - Enable protection for region 31. Write '0' has no effect.

impl W<u32, Reg<u32, _CONFIG1>>

pub fn region32(&mut self) -> REGION32_W<'_>

Bit 0 - Enable protection for region 32. Write '0' has no effect.

pub fn region33(&mut self) -> REGION33_W<'_>

Bit 1 - Enable protection for region 33. Write '0' has no effect.

pub fn region34(&mut self) -> REGION34_W<'_>

Bit 2 - Enable protection for region 34. Write '0' has no effect.

pub fn region35(&mut self) -> REGION35_W<'_>

Bit 3 - Enable protection for region 35. Write '0' has no effect.

pub fn region36(&mut self) -> REGION36_W<'_>

Bit 4 - Enable protection for region 36. Write '0' has no effect.

pub fn region37(&mut self) -> REGION37_W<'_>

Bit 5 - Enable protection for region 37. Write '0' has no effect.

pub fn region38(&mut self) -> REGION38_W<'_>

Bit 6 - Enable protection for region 38. Write '0' has no effect.

pub fn region39(&mut self) -> REGION39_W<'_>

Bit 7 - Enable protection for region 39. Write '0' has no effect.

pub fn region40(&mut self) -> REGION40_W<'_>

Bit 8 - Enable protection for region 40. Write '0' has no effect.

pub fn region41(&mut self) -> REGION41_W<'_>

Bit 9 - Enable protection for region 41. Write '0' has no effect.

pub fn region42(&mut self) -> REGION42_W<'_>

Bit 10 - Enable protection for region 42. Write '0' has no effect.

pub fn region43(&mut self) -> REGION43_W<'_>

Bit 11 - Enable protection for region 43. Write '0' has no effect.

pub fn region44(&mut self) -> REGION44_W<'_>

Bit 12 - Enable protection for region 44. Write '0' has no effect.

pub fn region45(&mut self) -> REGION45_W<'_>

Bit 13 - Enable protection for region 45. Write '0' has no effect.

pub fn region46(&mut self) -> REGION46_W<'_>

Bit 14 - Enable protection for region 46. Write '0' has no effect.

pub fn region47(&mut self) -> REGION47_W<'_>

Bit 15 - Enable protection for region 47. Write '0' has no effect.

impl W<u32, Reg<u32, _DISABLEINDEBUG>>

pub fn disableindebug(&mut self) -> DISABLEINDEBUG_W<'_>

Bit 0 - Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode.

impl W<u32, Reg<u32, _TASKS_HFCLKSTART>>

pub fn tasks_hfclkstart(&mut self) -> TASKS_HFCLKSTART_W<'_>

Bit 0 - Start HFCLK crystal oscillator

impl W<u32, Reg<u32, _TASKS_HFCLKSTOP>>

pub fn tasks_hfclkstop(&mut self) -> TASKS_HFCLKSTOP_W<'_>

Bit 0 - Stop HFCLK crystal oscillator

impl W<u32, Reg<u32, _TASKS_LFCLKSTART>>

pub fn tasks_lfclkstart(&mut self) -> TASKS_LFCLKSTART_W<'_>

Bit 0 - Start LFCLK source

impl W<u32, Reg<u32, _TASKS_LFCLKSTOP>>

pub fn tasks_lfclkstop(&mut self) -> TASKS_LFCLKSTOP_W<'_>

Bit 0 - Stop LFCLK source

impl W<u32, Reg<u32, _TASKS_CAL>>

pub fn tasks_cal(&mut self) -> TASKS_CAL_W<'_>

Bit 0 - Start calibration of LFRC oscillator

impl W<u32, Reg<u32, _TASKS_CTSTART>>

pub fn tasks_ctstart(&mut self) -> TASKS_CTSTART_W<'_>

Bit 0 - Start calibration timer

impl W<u32, Reg<u32, _TASKS_CTSTOP>>

pub fn tasks_ctstop(&mut self) -> TASKS_CTSTOP_W<'_>

Bit 0 - Stop calibration timer

impl W<u32, Reg<u32, _EVENTS_HFCLKSTARTED>>

pub fn events_hfclkstarted(&mut self) -> EVENTS_HFCLKSTARTED_W<'_>

Bit 0 - HFCLK oscillator started

impl W<u32, Reg<u32, _EVENTS_LFCLKSTARTED>>

pub fn events_lfclkstarted(&mut self) -> EVENTS_LFCLKSTARTED_W<'_>

Bit 0 - LFCLK started

impl W<u32, Reg<u32, _EVENTS_DONE>>

pub fn events_done(&mut self) -> EVENTS_DONE_W<'_>

Bit 0 - Calibration of LFCLK RC oscillator complete event

impl W<u32, Reg<u32, _EVENTS_CTTO>>

pub fn events_ctto(&mut self) -> EVENTS_CTTO_W<'_>

Bit 0 - Calibration timer timeout

impl W<u32, Reg<u32, _INTENSET>>

pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>

Bit 0 - Write '1' to enable interrupt for event HFCLKSTARTED

pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>

Bit 1 - Write '1' to enable interrupt for event LFCLKSTARTED

pub fn done(&mut self) -> DONE_W<'_>

Bit 3 - Write '1' to enable interrupt for event DONE

pub fn ctto(&mut self) -> CTTO_W<'_>

Bit 4 - Write '1' to enable interrupt for event CTTO

impl W<u32, Reg<u32, _INTENCLR>>

pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>

Bit 0 - Write '1' to disable interrupt for event HFCLKSTARTED

pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>

Bit 1 - Write '1' to disable interrupt for event LFCLKSTARTED

pub fn done(&mut self) -> DONE_W<'_>

Bit 3 - Write '1' to disable interrupt for event DONE

pub fn ctto(&mut self) -> CTTO_W<'_>

Bit 4 - Write '1' to disable interrupt for event CTTO

impl W<u32, Reg<u32, _LFCLKSRC>>

pub fn src(&mut self) -> SRC_W<'_>

Bits 0:1 - Clock source

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 16 - Enable or disable bypass of LFCLK crystal oscillator with external clock source

pub fn external(&mut self) -> EXTERNAL_W<'_>

Bit 17 - Enable or disable external source for LFCLK

impl W<u32, Reg<u32, _CTIV>>

pub fn ctiv(&mut self) -> CTIV_W<'_>

Bits 0:6 - Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.

impl W<u32, Reg<u32, _POWER>>

pub fn s0power(&mut self) -> S0POWER_W<'_>

Bit 0 - Keep RAM section S0 ON or OFF in System ON mode.

pub fn s1power(&mut self) -> S1POWER_W<'_>

Bit 1 - Keep RAM section S1 ON or OFF in System ON mode.

pub fn s0retention(&mut self) -> S0RETENTION_W<'_>

Bit 16 - Keep retention on RAM section S0 when RAM section is in OFF

pub fn s1retention(&mut self) -> S1RETENTION_W<'_>

Bit 17 - Keep retention on RAM section S1 when RAM section is in OFF

impl W<u32, Reg<u32, _POWERSET>>

pub fn s0power(&mut self) -> S0POWER_W<'_>

Bit 0 - Keep RAM section S0 of RAMn on or off in System ON mode

pub fn s1power(&mut self) -> S1POWER_W<'_>

Bit 1 - Keep RAM section S1 of RAMn on or off in System ON mode

pub fn s0retention(&mut self) -> S0RETENTION_W<'_>

Bit 16 - Keep retention on RAM section S0 when RAM section is switched off

pub fn s1retention(&mut self) -> S1RETENTION_W<'_>

Bit 17 - Keep retention on RAM section S1 when RAM section is switched off

impl W<u32, Reg<u32, _POWERCLR>>

pub fn s0power(&mut self) -> S0POWER_W<'_>

Bit 0 - Keep RAM section S0 of RAMn on or off in System ON mode

pub fn s1power(&mut self) -> S1POWER_W<'_>

Bit 1 - Keep RAM section S1 of RAMn on or off in System ON mode

pub fn s0retention(&mut self) -> S0RETENTION_W<'_>

Bit 16 - Keep retention on RAM section S0 when RAM section is switched off

pub fn s1retention(&mut self) -> S1RETENTION_W<'_>

Bit 17 - Keep retention on RAM section S1 when RAM section is switched off

impl W<u32, Reg<u32, _TASKS_CONSTLAT>>

pub fn tasks_constlat(&mut self) -> TASKS_CONSTLAT_W<'_>

Bit 0 - Enable Constant Latency mode

impl W<u32, Reg<u32, _TASKS_LOWPWR>>

pub fn tasks_lowpwr(&mut self) -> TASKS_LOWPWR_W<'_>

Bit 0 - Enable Low-power mode (variable latency)

impl W<u32, Reg<u32, _EVENTS_POFWARN>>

pub fn events_pofwarn(&mut self) -> EVENTS_POFWARN_W<'_>

Bit 0 - Power failure warning

impl W<u32, Reg<u32, _EVENTS_SLEEPENTER>>

pub fn events_sleepenter(&mut self) -> EVENTS_SLEEPENTER_W<'_>

Bit 0 - CPU entered WFI/WFE sleep

impl W<u32, Reg<u32, _EVENTS_SLEEPEXIT>>

pub fn events_sleepexit(&mut self) -> EVENTS_SLEEPEXIT_W<'_>

Bit 0 - CPU exited WFI/WFE sleep

impl W<u32, Reg<u32, _INTENSET>>

pub fn pofwarn(&mut self) -> POFWARN_W<'_>

Bit 2 - Write '1' to enable interrupt for event POFWARN

pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>

Bit 5 - Write '1' to enable interrupt for event SLEEPENTER

pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>

Bit 6 - Write '1' to enable interrupt for event SLEEPEXIT

impl W<u32, Reg<u32, _INTENCLR>>

pub fn pofwarn(&mut self) -> POFWARN_W<'_>

Bit 2 - Write '1' to disable interrupt for event POFWARN

pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>

Bit 5 - Write '1' to disable interrupt for event SLEEPENTER

pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>

Bit 6 - Write '1' to disable interrupt for event SLEEPEXIT

impl W<u32, Reg<u32, _RESETREAS>>

pub fn resetpin(&mut self) -> RESETPIN_W<'_>

Bit 0 - Reset from pin-reset detected

pub fn dog(&mut self) -> DOG_W<'_>

Bit 1 - Reset from watchdog detected

pub fn sreq(&mut self) -> SREQ_W<'_>

Bit 2 - Reset from soft reset detected

pub fn lockup(&mut self) -> LOCKUP_W<'_>

Bit 3 - Reset from CPU lock-up detected

pub fn off(&mut self) -> OFF_W<'_>

Bit 16 - Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO

pub fn dif(&mut self) -> DIF_W<'_>

Bit 18 - Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode

impl W<u32, Reg<u32, _SYSTEMOFF>>

pub fn systemoff(&mut self) -> SYSTEMOFF_W<'_>

Bit 0 - Enable System OFF mode

impl W<u32, Reg<u32, _POFCON>>

pub fn pof(&mut self) -> POF_W<'_>

Bit 0 - Enable or disable power failure comparator

pub fn threshold(&mut self) -> THRESHOLD_W<'_>

Bits 1:4 - Power failure comparator threshold setting

impl W<u32, Reg<u32, _GPREGRET>>

pub fn gpregret(&mut self) -> GPREGRET_W<'_>

Bits 0:7 - General purpose retention register

impl W<u32, Reg<u32, _GPREGRET2>>

pub fn gpregret(&mut self) -> GPREGRET_W<'_>

Bits 0:7 - General purpose retention register

impl W<u32, Reg<u32, _DCDCEN>>

pub fn dcdcen(&mut self) -> DCDCEN_W<'_>

Bit 0 - Enable or disable DC/DC converter

impl W<u32, Reg<u32, _OUT>>

pub fn pin0(&mut self) -> PIN0_W<'_>

Bit 0 - Pin 0

pub fn pin1(&mut self) -> PIN1_W<'_>

Bit 1 - Pin 1

pub fn pin2(&mut self) -> PIN2_W<'_>

Bit 2 - Pin 2

pub fn pin3(&mut self) -> PIN3_W<'_>

Bit 3 - Pin 3

pub fn pin4(&mut self) -> PIN4_W<'_>

Bit 4 - Pin 4

pub fn pin5(&mut self) -> PIN5_W<'_>

Bit 5 - Pin 5

pub fn pin6(&mut self) -> PIN6_W<'_>

Bit 6 - Pin 6

pub fn pin7(&mut self) -> PIN7_W<'_>

Bit 7 - Pin 7

pub fn pin8(&mut self) -> PIN8_W<'_>

Bit 8 - Pin 8

pub fn pin9(&mut self) -> PIN9_W<'_>

Bit 9 - Pin 9

pub fn pin10(&mut self) -> PIN10_W<'_>

Bit 10 - Pin 10

pub fn pin11(&mut self) -> PIN11_W<'_>

Bit 11 - Pin 11

pub fn pin12(&mut self) -> PIN12_W<'_>

Bit 12 - Pin 12

pub fn pin13(&mut self) -> PIN13_W<'_>

Bit 13 - Pin 13

pub fn pin14(&mut self) -> PIN14_W<'_>

Bit 14 - Pin 14

pub fn pin15(&mut self) -> PIN15_W<'_>

Bit 15 - Pin 15

pub fn pin16(&mut self) -> PIN16_W<'_>

Bit 16 - Pin 16

pub fn pin17(&mut self) -> PIN17_W<'_>

Bit 17 - Pin 17

pub fn pin18(&mut self) -> PIN18_W<'_>

Bit 18 - Pin 18

pub fn pin19(&mut self) -> PIN19_W<'_>

Bit 19 - Pin 19

pub fn pin20(&mut self) -> PIN20_W<'_>

Bit 20 - Pin 20

pub fn pin21(&mut self) -> PIN21_W<'_>

Bit 21 - Pin 21

pub fn pin22(&mut self) -> PIN22_W<'_>

Bit 22 - Pin 22

pub fn pin23(&mut self) -> PIN23_W<'_>

Bit 23 - Pin 23

pub fn pin24(&mut self) -> PIN24_W<'_>

Bit 24 - Pin 24

pub fn pin25(&mut self) -> PIN25_W<'_>

Bit 25 - Pin 25

pub fn pin26(&mut self) -> PIN26_W<'_>

Bit 26 - Pin 26

pub fn pin27(&mut self) -> PIN27_W<'_>

Bit 27 - Pin 27

pub fn pin28(&mut self) -> PIN28_W<'_>

Bit 28 - Pin 28

pub fn pin29(&mut self) -> PIN29_W<'_>

Bit 29 - Pin 29

pub fn pin30(&mut self) -> PIN30_W<'_>

Bit 30 - Pin 30

pub fn pin31(&mut self) -> PIN31_W<'_>

Bit 31 - Pin 31

impl W<u32, Reg<u32, _OUTSET>>

pub fn pin0(&mut self) -> PIN0_W<'_>

Bit 0 - Pin 0

pub fn pin1(&mut self) -> PIN1_W<'_>

Bit 1 - Pin 1

pub fn pin2(&mut self) -> PIN2_W<'_>

Bit 2 - Pin 2

pub fn pin3(&mut self) -> PIN3_W<'_>

Bit 3 - Pin 3

pub fn pin4(&mut self) -> PIN4_W<'_>

Bit 4 - Pin 4

pub fn pin5(&mut self) -> PIN5_W<'_>

Bit 5 - Pin 5

pub fn pin6(&mut self) -> PIN6_W<'_>

Bit 6 - Pin 6

pub fn pin7(&mut self) -> PIN7_W<'_>

Bit 7 - Pin 7

pub fn pin8(&mut self) -> PIN8_W<'_>

Bit 8 - Pin 8

pub fn pin9(&mut self) -> PIN9_W<'_>

Bit 9 - Pin 9

pub fn pin10(&mut self) -> PIN10_W<'_>

Bit 10 - Pin 10

pub fn pin11(&mut self) -> PIN11_W<'_>

Bit 11 - Pin 11

pub fn pin12(&mut self) -> PIN12_W<'_>

Bit 12 - Pin 12

pub fn pin13(&mut self) -> PIN13_W<'_>

Bit 13 - Pin 13

pub fn pin14(&mut self) -> PIN14_W<'_>

Bit 14 - Pin 14

pub fn pin15(&mut self) -> PIN15_W<'_>

Bit 15 - Pin 15

pub fn pin16(&mut self) -> PIN16_W<'_>

Bit 16 - Pin 16

pub fn pin17(&mut self) -> PIN17_W<'_>

Bit 17 - Pin 17

pub fn pin18(&mut self) -> PIN18_W<'_>

Bit 18 - Pin 18

pub fn pin19(&mut self) -> PIN19_W<'_>

Bit 19 - Pin 19

pub fn pin20(&mut self) -> PIN20_W<'_>

Bit 20 - Pin 20

pub fn pin21(&mut self) -> PIN21_W<'_>

Bit 21 - Pin 21

pub fn pin22(&mut self) -> PIN22_W<'_>

Bit 22 - Pin 22

pub fn pin23(&mut self) -> PIN23_W<'_>

Bit 23 - Pin 23

pub fn pin24(&mut self) -> PIN24_W<'_>

Bit 24 - Pin 24

pub fn pin25(&mut self) -> PIN25_W<'_>

Bit 25 - Pin 25

pub fn pin26(&mut self) -> PIN26_W<'_>

Bit 26 - Pin 26

pub fn pin27(&mut self) -> PIN27_W<'_>

Bit 27 - Pin 27

pub fn pin28(&mut self) -> PIN28_W<'_>

Bit 28 - Pin 28

pub fn pin29(&mut self) -> PIN29_W<'_>

Bit 29 - Pin 29

pub fn pin30(&mut self) -> PIN30_W<'_>

Bit 30 - Pin 30

pub fn pin31(&mut self) -> PIN31_W<'_>

Bit 31 - Pin 31

impl W<u32, Reg<u32, _OUTCLR>>

pub fn pin0(&mut self) -> PIN0_W<'_>

Bit 0 - Pin 0

pub fn pin1(&mut self) -> PIN1_W<'_>

Bit 1 - Pin 1

pub fn pin2(&mut self) -> PIN2_W<'_>

Bit 2 - Pin 2

pub fn pin3(&mut self) -> PIN3_W<'_>

Bit 3 - Pin 3

pub fn pin4(&mut self) -> PIN4_W<'_>

Bit 4 - Pin 4

pub fn pin5(&mut self) -> PIN5_W<'_>

Bit 5 - Pin 5

pub fn pin6(&mut self) -> PIN6_W<'_>

Bit 6 - Pin 6

pub fn pin7(&mut self) -> PIN7_W<'_>

Bit 7 - Pin 7

pub fn pin8(&mut self) -> PIN8_W<'_>

Bit 8 - Pin 8

pub fn pin9(&mut self) -> PIN9_W<'_>

Bit 9 - Pin 9

pub fn pin10(&mut self) -> PIN10_W<'_>

Bit 10 - Pin 10

pub fn pin11(&mut self) -> PIN11_W<'_>

Bit 11 - Pin 11

pub fn pin12(&mut self) -> PIN12_W<'_>

Bit 12 - Pin 12

pub fn pin13(&mut self) -> PIN13_W<'_>

Bit 13 - Pin 13

pub fn pin14(&mut self) -> PIN14_W<'_>

Bit 14 - Pin 14

pub fn pin15(&mut self) -> PIN15_W<'_>

Bit 15 - Pin 15

pub fn pin16(&mut self) -> PIN16_W<'_>

Bit 16 - Pin 16

pub fn pin17(&mut self) -> PIN17_W<'_>

Bit 17 - Pin 17

pub fn pin18(&mut self) -> PIN18_W<'_>

Bit 18 - Pin 18

pub fn pin19(&mut self) -> PIN19_W<'_>

Bit 19 - Pin 19

pub fn pin20(&mut self) -> PIN20_W<'_>

Bit 20 - Pin 20

pub fn pin21(&mut self) -> PIN21_W<'_>

Bit 21 - Pin 21

pub fn pin22(&mut self) -> PIN22_W<'_>

Bit 22 - Pin 22

pub fn pin23(&mut self) -> PIN23_W<'_>

Bit 23 - Pin 23

pub fn pin24(&mut self) -> PIN24_W<'_>

Bit 24 - Pin 24

pub fn pin25(&mut self) -> PIN25_W<'_>

Bit 25 - Pin 25

pub fn pin26(&mut self) -> PIN26_W<'_>

Bit 26 - Pin 26

pub fn pin27(&mut self) -> PIN27_W<'_>

Bit 27 - Pin 27

pub fn pin28(&mut self) -> PIN28_W<'_>

Bit 28 - Pin 28

pub fn pin29(&mut self) -> PIN29_W<'_>

Bit 29 - Pin 29

pub fn pin30(&mut self) -> PIN30_W<'_>

Bit 30 - Pin 30

pub fn pin31(&mut self) -> PIN31_W<'_>

Bit 31 - Pin 31

impl W<u32, Reg<u32, _DIR>>

pub fn pin0(&mut self) -> PIN0_W<'_>

Bit 0 - Pin 0

pub fn pin1(&mut self) -> PIN1_W<'_>

Bit 1 - Pin 1

pub fn pin2(&mut self) -> PIN2_W<'_>

Bit 2 - Pin 2

pub fn pin3(&mut self) -> PIN3_W<'_>

Bit 3 - Pin 3

pub fn pin4(&mut self) -> PIN4_W<'_>

Bit 4 - Pin 4

pub fn pin5(&mut self) -> PIN5_W<'_>

Bit 5 - Pin 5

pub fn pin6(&mut self) -> PIN6_W<'_>

Bit 6 - Pin 6

pub fn pin7(&mut self) -> PIN7_W<'_>

Bit 7 - Pin 7

pub fn pin8(&mut self) -> PIN8_W<'_>

Bit 8 - Pin 8

pub fn pin9(&mut self) -> PIN9_W<'_>

Bit 9 - Pin 9

pub fn pin10(&mut self) -> PIN10_W<'_>

Bit 10 - Pin 10

pub fn pin11(&mut self) -> PIN11_W<'_>

Bit 11 - Pin 11

pub fn pin12(&mut self) -> PIN12_W<'_>

Bit 12 - Pin 12

pub fn pin13(&mut self) -> PIN13_W<'_>

Bit 13 - Pin 13

pub fn pin14(&mut self) -> PIN14_W<'_>

Bit 14 - Pin 14

pub fn pin15(&mut self) -> PIN15_W<'_>

Bit 15 - Pin 15

pub fn pin16(&mut self) -> PIN16_W<'_>

Bit 16 - Pin 16

pub fn pin17(&mut self) -> PIN17_W<'_>

Bit 17 - Pin 17

pub fn pin18(&mut self) -> PIN18_W<'_>

Bit 18 - Pin 18

pub fn pin19(&mut self) -> PIN19_W<'_>

Bit 19 - Pin 19

pub fn pin20(&mut self) -> PIN20_W<'_>

Bit 20 - Pin 20

pub fn pin21(&mut self) -> PIN21_W<'_>

Bit 21 - Pin 21

pub fn pin22(&mut self) -> PIN22_W<'_>

Bit 22 - Pin 22

pub fn pin23(&mut self) -> PIN23_W<'_>

Bit 23 - Pin 23

pub fn pin24(&mut self) -> PIN24_W<'_>

Bit 24 - Pin 24

pub fn pin25(&mut self) -> PIN25_W<'_>

Bit 25 - Pin 25

pub fn pin26(&mut self) -> PIN26_W<'_>

Bit 26 - Pin 26

pub fn pin27(&mut self) -> PIN27_W<'_>

Bit 27 - Pin 27

pub fn pin28(&mut self) -> PIN28_W<'_>

Bit 28 - Pin 28

pub fn pin29(&mut self) -> PIN29_W<'_>

Bit 29 - Pin 29

pub fn pin30(&mut self) -> PIN30_W<'_>

Bit 30 - Pin 30

pub fn pin31(&mut self) -> PIN31_W<'_>

Bit 31 - Pin 31

impl W<u32, Reg<u32, _DIRSET>>

pub fn pin0(&mut self) -> PIN0_W<'_>

Bit 0 - Set as output pin 0

pub fn pin1(&mut self) -> PIN1_W<'_>

Bit 1 - Set as output pin 1

pub fn pin2(&mut self) -> PIN2_W<'_>

Bit 2 - Set as output pin 2

pub fn pin3(&mut self) -> PIN3_W<'_>

Bit 3 - Set as output pin 3

pub fn pin4(&mut self) -> PIN4_W<'_>

Bit 4 - Set as output pin 4

pub fn pin5(&mut self) -> PIN5_W<'_>

Bit 5 - Set as output pin 5

pub fn pin6(&mut self) -> PIN6_W<'_>

Bit 6 - Set as output pin 6

pub fn pin7(&mut self) -> PIN7_W<'_>

Bit 7 - Set as output pin 7

pub fn pin8(&mut self) -> PIN8_W<'_>

Bit 8 - Set as output pin 8

pub fn pin9(&mut self) -> PIN9_W<'_>

Bit 9 - Set as output pin 9

pub fn pin10(&mut self) -> PIN10_W<'_>

Bit 10 - Set as output pin 10

pub fn pin11(&mut self) -> PIN11_W<'_>

Bit 11 - Set as output pin 11

pub fn pin12(&mut self) -> PIN12_W<'_>

Bit 12 - Set as output pin 12

pub fn pin13(&mut self) -> PIN13_W<'_>

Bit 13 - Set as output pin 13

pub fn pin14(&mut self) -> PIN14_W<'_>

Bit 14 - Set as output pin 14

pub fn pin15(&mut self) -> PIN15_W<'_>

Bit 15 - Set as output pin 15

pub fn pin16(&mut self) -> PIN16_W<'_>

Bit 16 - Set as output pin 16

pub fn pin17(&mut self) -> PIN17_W<'_>

Bit 17 - Set as output pin 17

pub fn pin18(&mut self) -> PIN18_W<'_>

Bit 18 - Set as output pin 18

pub fn pin19(&mut self) -> PIN19_W<'_>

Bit 19 - Set as output pin 19

pub fn pin20(&mut self) -> PIN20_W<'_>

Bit 20 - Set as output pin 20

pub fn pin21(&mut self) -> PIN21_W<'_>

Bit 21 - Set as output pin 21

pub fn pin22(&mut self) -> PIN22_W<'_>

Bit 22 - Set as output pin 22

pub fn pin23(&mut self) -> PIN23_W<'_>

Bit 23 - Set as output pin 23

pub fn pin24(&mut self) -> PIN24_W<'_>

Bit 24 - Set as output pin 24

pub fn pin25(&mut self) -> PIN25_W<'_>

Bit 25 - Set as output pin 25

pub fn pin26(&mut self) -> PIN26_W<'_>

Bit 26 - Set as output pin 26

pub fn pin27(&mut self) -> PIN27_W<'_>

Bit 27 - Set as output pin 27

pub fn pin28(&mut self) -> PIN28_W<'_>

Bit 28 - Set as output pin 28

pub fn pin29(&mut self) -> PIN29_W<'_>

Bit 29 - Set as output pin 29

pub fn pin30(&mut self) -> PIN30_W<'_>

Bit 30 - Set as output pin 30

pub fn pin31(&mut self) -> PIN31_W<'_>

Bit 31 - Set as output pin 31

impl W<u32, Reg<u32, _DIRCLR>>

pub fn pin0(&mut self) -> PIN0_W<'_>

Bit 0 - Set as input pin 0

pub fn pin1(&mut self) -> PIN1_W<'_>

Bit 1 - Set as input pin 1

pub fn pin2(&mut self) -> PIN2_W<'_>

Bit 2 - Set as input pin 2

pub fn pin3(&mut self) -> PIN3_W<'_>

Bit 3 - Set as input pin 3

pub fn pin4(&mut self) -> PIN4_W<'_>

Bit 4 - Set as input pin 4

pub fn pin5(&mut self) -> PIN5_W<'_>

Bit 5 - Set as input pin 5

pub fn pin6(&mut self) -> PIN6_W<'_>

Bit 6 - Set as input pin 6

pub fn pin7(&mut self) -> PIN7_W<'_>

Bit 7 - Set as input pin 7

pub fn pin8(&mut self) -> PIN8_W<'_>

Bit 8 - Set as input pin 8

pub fn pin9(&mut self) -> PIN9_W<'_>

Bit 9 - Set as input pin 9

pub fn pin10(&mut self) -> PIN10_W<'_>

Bit 10 - Set as input pin 10

pub fn pin11(&mut self) -> PIN11_W<'_>

Bit 11 - Set as input pin 11

pub fn pin12(&mut self) -> PIN12_W<'_>

Bit 12 - Set as input pin 12

pub fn pin13(&mut self) -> PIN13_W<'_>

Bit 13 - Set as input pin 13

pub fn pin14(&mut self) -> PIN14_W<'_>

Bit 14 - Set as input pin 14

pub fn pin15(&mut self) -> PIN15_W<'_>

Bit 15 - Set as input pin 15

pub fn pin16(&mut self) -> PIN16_W<'_>

Bit 16 - Set as input pin 16

pub fn pin17(&mut self) -> PIN17_W<'_>

Bit 17 - Set as input pin 17

pub fn pin18(&mut self) -> PIN18_W<'_>

Bit 18 - Set as input pin 18

pub fn pin19(&mut self) -> PIN19_W<'_>

Bit 19 - Set as input pin 19

pub fn pin20(&mut self) -> PIN20_W<'_>

Bit 20 - Set as input pin 20

pub fn pin21(&mut self) -> PIN21_W<'_>

Bit 21 - Set as input pin 21

pub fn pin22(&mut self) -> PIN22_W<'_>

Bit 22 - Set as input pin 22

pub fn pin23(&mut self) -> PIN23_W<'_>

Bit 23 - Set as input pin 23

pub fn pin24(&mut self) -> PIN24_W<'_>

Bit 24 - Set as input pin 24

pub fn pin25(&mut self) -> PIN25_W<'_>

Bit 25 - Set as input pin 25

pub fn pin26(&mut self) -> PIN26_W<'_>

Bit 26 - Set as input pin 26

pub fn pin27(&mut self) -> PIN27_W<'_>

Bit 27 - Set as input pin 27

pub fn pin28(&mut self) -> PIN28_W<'_>

Bit 28 - Set as input pin 28

pub fn pin29(&mut self) -> PIN29_W<'_>

Bit 29 - Set as input pin 29

pub fn pin30(&mut self) -> PIN30_W<'_>

Bit 30 - Set as input pin 30

pub fn pin31(&mut self) -> PIN31_W<'_>

Bit 31 - Set as input pin 31

impl W<u32, Reg<u32, _LATCH>>

pub fn pin0(&mut self) -> PIN0_W<'_>

Bit 0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.

pub fn pin1(&mut self) -> PIN1_W<'_>

Bit 1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.

pub fn pin2(&mut self) -> PIN2_W<'_>

Bit 2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.

pub fn pin3(&mut self) -> PIN3_W<'_>

Bit 3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.

pub fn pin4(&mut self) -> PIN4_W<'_>

Bit 4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.

pub fn pin5(&mut self) -> PIN5_W<'_>

Bit 5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.

pub fn pin6(&mut self) -> PIN6_W<'_>

Bit 6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.

pub fn pin7(&mut self) -> PIN7_W<'_>

Bit 7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.

pub fn pin8(&mut self) -> PIN8_W<'_>

Bit 8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.

pub fn pin9(&mut self) -> PIN9_W<'_>

Bit 9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.

pub fn pin10(&mut self) -> PIN10_W<'_>

Bit 10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.

pub fn pin11(&mut self) -> PIN11_W<'_>

Bit 11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.

pub fn pin12(&mut self) -> PIN12_W<'_>

Bit 12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.

pub fn pin13(&mut self) -> PIN13_W<'_>

Bit 13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.

pub fn pin14(&mut self) -> PIN14_W<'_>

Bit 14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.

pub fn pin15(&mut self) -> PIN15_W<'_>

Bit 15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.

pub fn pin16(&mut self) -> PIN16_W<'_>

Bit 16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.

pub fn pin17(&mut self) -> PIN17_W<'_>

Bit 17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.

pub fn pin18(&mut self) -> PIN18_W<'_>

Bit 18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.

pub fn pin19(&mut self) -> PIN19_W<'_>

Bit 19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.

pub fn pin20(&mut self) -> PIN20_W<'_>

Bit 20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.

pub fn pin21(&mut self) -> PIN21_W<'_>

Bit 21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.

pub fn pin22(&mut self) -> PIN22_W<'_>

Bit 22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.

pub fn pin23(&mut self) -> PIN23_W<'_>

Bit 23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.

pub fn pin24(&mut self) -> PIN24_W<'_>

Bit 24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.

pub fn pin25(&mut self) -> PIN25_W<'_>

Bit 25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.

pub fn pin26(&mut self) -> PIN26_W<'_>

Bit 26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.

pub fn pin27(&mut self) -> PIN27_W<'_>

Bit 27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.

pub fn pin28(&mut self) -> PIN28_W<'_>

Bit 28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.

pub fn pin29(&mut self) -> PIN29_W<'_>

Bit 29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.

pub fn pin30(&mut self) -> PIN30_W<'_>

Bit 30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.

pub fn pin31(&mut self) -> PIN31_W<'_>

Bit 31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.

impl W<u32, Reg<u32, _DETECTMODE>>

pub fn detectmode(&mut self) -> DETECTMODE_W<'_>

Bit 0 - Select between default DETECT signal behaviour and LDETECT mode

impl W<u32, Reg<u32, _PIN_CNF>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Pin direction. Same physical register as DIR register

pub fn input(&mut self) -> INPUT_W<'_>

Bit 1 - Connect or disconnect input buffer

pub fn pull(&mut self) -> PULL_W<'_>

Bits 2:3 - Pull configuration

pub fn drive(&mut self) -> DRIVE_W<'_>

Bits 8:10 - Drive configuration

pub fn sense(&mut self) -> SENSE_W<'_>

Bits 16:17 - Pin sensing mechanism

impl W<u32, Reg<u32, _DFEGPIO>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn port(&mut self) -> PORT_W<'_>

Bit 5 - Port number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - Data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:12 - Maximum number of buffer words to transfer

impl W<u32, Reg<u32, _TASKS_TXEN>>

pub fn tasks_txen(&mut self) -> TASKS_TXEN_W<'_>

Bit 0 - Enable RADIO in TX mode

impl W<u32, Reg<u32, _TASKS_RXEN>>

pub fn tasks_rxen(&mut self) -> TASKS_RXEN_W<'_>

Bit 0 - Enable RADIO in RX mode

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Start RADIO

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop RADIO

impl W<u32, Reg<u32, _TASKS_DISABLE>>

pub fn tasks_disable(&mut self) -> TASKS_DISABLE_W<'_>

Bit 0 - Disable RADIO

impl W<u32, Reg<u32, _TASKS_RSSISTART>>

pub fn tasks_rssistart(&mut self) -> TASKS_RSSISTART_W<'_>

Bit 0 - Start the RSSI and take one single sample of the receive signal strength

impl W<u32, Reg<u32, _TASKS_RSSISTOP>>

pub fn tasks_rssistop(&mut self) -> TASKS_RSSISTOP_W<'_>

Bit 0 - Stop the RSSI measurement

impl W<u32, Reg<u32, _TASKS_BCSTART>>

pub fn tasks_bcstart(&mut self) -> TASKS_BCSTART_W<'_>

Bit 0 - Start the bit counter

impl W<u32, Reg<u32, _TASKS_BCSTOP>>

pub fn tasks_bcstop(&mut self) -> TASKS_BCSTOP_W<'_>

Bit 0 - Stop the bit counter

impl W<u32, Reg<u32, _TASKS_EDSTART>>

pub fn tasks_edstart(&mut self) -> TASKS_EDSTART_W<'_>

Bit 0 - Start the energy detect measurement used in IEEE 802.15.4 mode

impl W<u32, Reg<u32, _TASKS_EDSTOP>>

pub fn tasks_edstop(&mut self) -> TASKS_EDSTOP_W<'_>

Bit 0 - Stop the energy detect measurement

impl W<u32, Reg<u32, _TASKS_CCASTART>>

pub fn tasks_ccastart(&mut self) -> TASKS_CCASTART_W<'_>

Bit 0 - Start the clear channel assessment used in IEEE 802.15.4 mode

impl W<u32, Reg<u32, _TASKS_CCASTOP>>

pub fn tasks_ccastop(&mut self) -> TASKS_CCASTOP_W<'_>

Bit 0 - Stop the clear channel assessment

impl W<u32, Reg<u32, _EVENTS_READY>>

pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>

Bit 0 - RADIO has ramped up and is ready to be started

impl W<u32, Reg<u32, _EVENTS_ADDRESS>>

pub fn events_address(&mut self) -> EVENTS_ADDRESS_W<'_>

Bit 0 - Address sent or received

impl W<u32, Reg<u32, _EVENTS_PAYLOAD>>

pub fn events_payload(&mut self) -> EVENTS_PAYLOAD_W<'_>

Bit 0 - Packet payload sent or received

impl W<u32, Reg<u32, _EVENTS_END>>

pub fn events_end(&mut self) -> EVENTS_END_W<'_>

Bit 0 - Packet sent or received

impl W<u32, Reg<u32, _EVENTS_DISABLED>>

pub fn events_disabled(&mut self) -> EVENTS_DISABLED_W<'_>

Bit 0 - RADIO has been disabled

impl W<u32, Reg<u32, _EVENTS_DEVMATCH>>

pub fn events_devmatch(&mut self) -> EVENTS_DEVMATCH_W<'_>

Bit 0 - A device address match occurred on the last received packet

impl W<u32, Reg<u32, _EVENTS_DEVMISS>>

pub fn events_devmiss(&mut self) -> EVENTS_DEVMISS_W<'_>

Bit 0 - No device address match occurred on the last received packet

impl W<u32, Reg<u32, _EVENTS_RSSIEND>>

pub fn events_rssiend(&mut self) -> EVENTS_RSSIEND_W<'_>

Bit 0 - Sampling of receive signal strength complete

impl W<u32, Reg<u32, _EVENTS_BCMATCH>>

pub fn events_bcmatch(&mut self) -> EVENTS_BCMATCH_W<'_>

Bit 0 - Bit counter reached bit count value

impl W<u32, Reg<u32, _EVENTS_CRCOK>>

pub fn events_crcok(&mut self) -> EVENTS_CRCOK_W<'_>

Bit 0 - Packet received with CRC ok

impl W<u32, Reg<u32, _EVENTS_CRCERROR>>

pub fn events_crcerror(&mut self) -> EVENTS_CRCERROR_W<'_>

Bit 0 - Packet received with CRC error

impl W<u32, Reg<u32, _EVENTS_FRAMESTART>>

pub fn events_framestart(&mut self) -> EVENTS_FRAMESTART_W<'_>

Bit 0 - IEEE 802.15.4 length field received

impl W<u32, Reg<u32, _EVENTS_EDEND>>

pub fn events_edend(&mut self) -> EVENTS_EDEND_W<'_>

Bit 0 - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register

impl W<u32, Reg<u32, _EVENTS_EDSTOPPED>>

pub fn events_edstopped(&mut self) -> EVENTS_EDSTOPPED_W<'_>

Bit 0 - The sampling of energy detection has stopped

impl W<u32, Reg<u32, _EVENTS_CCAIDLE>>

pub fn events_ccaidle(&mut self) -> EVENTS_CCAIDLE_W<'_>

Bit 0 - Wireless medium in idle - clear to send

impl W<u32, Reg<u32, _EVENTS_CCABUSY>>

pub fn events_ccabusy(&mut self) -> EVENTS_CCABUSY_W<'_>

Bit 0 - Wireless medium busy - do not send

impl W<u32, Reg<u32, _EVENTS_CCASTOPPED>>

pub fn events_ccastopped(&mut self) -> EVENTS_CCASTOPPED_W<'_>

Bit 0 - The CCA has stopped

impl W<u32, Reg<u32, _EVENTS_RATEBOOST>>

pub fn events_rateboost(&mut self) -> EVENTS_RATEBOOST_W<'_>

Bit 0 - Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.

impl W<u32, Reg<u32, _EVENTS_TXREADY>>

pub fn events_txready(&mut self) -> EVENTS_TXREADY_W<'_>

Bit 0 - RADIO has ramped up and is ready to be started TX path

impl W<u32, Reg<u32, _EVENTS_RXREADY>>

pub fn events_rxready(&mut self) -> EVENTS_RXREADY_W<'_>

Bit 0 - RADIO has ramped up and is ready to be started RX path

impl W<u32, Reg<u32, _EVENTS_MHRMATCH>>

pub fn events_mhrmatch(&mut self) -> EVENTS_MHRMATCH_W<'_>

Bit 0 - MAC header match found

impl W<u32, Reg<u32, _EVENTS_PHYEND>>

pub fn events_phyend(&mut self) -> EVENTS_PHYEND_W<'_>

Bit 0 - Generated when last bit is sent on air

impl W<u32, Reg<u32, _EVENTS_CTEPRESENT>>

pub fn events_ctepresent(&mut self) -> EVENTS_CTEPRESENT_W<'_>

Bit 0 - CTE is present (early warning right after receiving CTEInfo byte)

impl W<u32, Reg<u32, _SHORTS>>

pub fn ready_start(&mut self) -> READY_START_W<'_>

Bit 0 - Shortcut between event READY and task START

pub fn end_disable(&mut self) -> END_DISABLE_W<'_>

Bit 1 - Shortcut between event END and task DISABLE

pub fn disabled_txen(&mut self) -> DISABLED_TXEN_W<'_>

Bit 2 - Shortcut between event DISABLED and task TXEN

pub fn disabled_rxen(&mut self) -> DISABLED_RXEN_W<'_>

Bit 3 - Shortcut between event DISABLED and task RXEN

pub fn address_rssistart(&mut self) -> ADDRESS_RSSISTART_W<'_>

Bit 4 - Shortcut between event ADDRESS and task RSSISTART

pub fn end_start(&mut self) -> END_START_W<'_>

Bit 5 - Shortcut between event END and task START

pub fn address_bcstart(&mut self) -> ADDRESS_BCSTART_W<'_>

Bit 6 - Shortcut between event ADDRESS and task BCSTART

pub fn disabled_rssistop(&mut self) -> DISABLED_RSSISTOP_W<'_>

Bit 8 - Shortcut between event DISABLED and task RSSISTOP

pub fn rxready_ccastart(&mut self) -> RXREADY_CCASTART_W<'_>

Bit 11 - Shortcut between event RXREADY and task CCASTART

pub fn ccaidle_txen(&mut self) -> CCAIDLE_TXEN_W<'_>

Bit 12 - Shortcut between event CCAIDLE and task TXEN

pub fn ccabusy_disable(&mut self) -> CCABUSY_DISABLE_W<'_>

Bit 13 - Shortcut between event CCABUSY and task DISABLE

pub fn framestart_bcstart(&mut self) -> FRAMESTART_BCSTART_W<'_>

Bit 14 - Shortcut between event FRAMESTART and task BCSTART

pub fn ready_edstart(&mut self) -> READY_EDSTART_W<'_>

Bit 15 - Shortcut between event READY and task EDSTART

pub fn edend_disable(&mut self) -> EDEND_DISABLE_W<'_>

Bit 16 - Shortcut between event EDEND and task DISABLE

pub fn ccaidle_stop(&mut self) -> CCAIDLE_STOP_W<'_>

Bit 17 - Shortcut between event CCAIDLE and task STOP

pub fn txready_start(&mut self) -> TXREADY_START_W<'_>

Bit 18 - Shortcut between event TXREADY and task START

pub fn rxready_start(&mut self) -> RXREADY_START_W<'_>

Bit 19 - Shortcut between event RXREADY and task START

pub fn phyend_disable(&mut self) -> PHYEND_DISABLE_W<'_>

Bit 20 - Shortcut between event PHYEND and task DISABLE

pub fn phyend_start(&mut self) -> PHYEND_START_W<'_>

Bit 21 - Shortcut between event PHYEND and task START

impl W<u32, Reg<u32, _INTENSET>>

pub fn ready(&mut self) -> READY_W<'_>

Bit 0 - Write '1' to enable interrupt for event READY

pub fn address(&mut self) -> ADDRESS_W<'_>

Bit 1 - Write '1' to enable interrupt for event ADDRESS

pub fn payload(&mut self) -> PAYLOAD_W<'_>

Bit 2 - Write '1' to enable interrupt for event PAYLOAD

pub fn end(&mut self) -> END_W<'_>

Bit 3 - Write '1' to enable interrupt for event END

pub fn disabled(&mut self) -> DISABLED_W<'_>

Bit 4 - Write '1' to enable interrupt for event DISABLED

pub fn devmatch(&mut self) -> DEVMATCH_W<'_>

Bit 5 - Write '1' to enable interrupt for event DEVMATCH

pub fn devmiss(&mut self) -> DEVMISS_W<'_>

Bit 6 - Write '1' to enable interrupt for event DEVMISS

pub fn rssiend(&mut self) -> RSSIEND_W<'_>

Bit 7 - Write '1' to enable interrupt for event RSSIEND

pub fn bcmatch(&mut self) -> BCMATCH_W<'_>

Bit 10 - Write '1' to enable interrupt for event BCMATCH

pub fn crcok(&mut self) -> CRCOK_W<'_>

Bit 12 - Write '1' to enable interrupt for event CRCOK

pub fn crcerror(&mut self) -> CRCERROR_W<'_>

Bit 13 - Write '1' to enable interrupt for event CRCERROR

pub fn framestart(&mut self) -> FRAMESTART_W<'_>

Bit 14 - Write '1' to enable interrupt for event FRAMESTART

pub fn edend(&mut self) -> EDEND_W<'_>

Bit 15 - Write '1' to enable interrupt for event EDEND

pub fn edstopped(&mut self) -> EDSTOPPED_W<'_>

Bit 16 - Write '1' to enable interrupt for event EDSTOPPED

pub fn ccaidle(&mut self) -> CCAIDLE_W<'_>

Bit 17 - Write '1' to enable interrupt for event CCAIDLE

pub fn ccabusy(&mut self) -> CCABUSY_W<'_>

Bit 18 - Write '1' to enable interrupt for event CCABUSY

pub fn ccastopped(&mut self) -> CCASTOPPED_W<'_>

Bit 19 - Write '1' to enable interrupt for event CCASTOPPED

pub fn rateboost(&mut self) -> RATEBOOST_W<'_>

Bit 20 - Write '1' to enable interrupt for event RATEBOOST

pub fn txready(&mut self) -> TXREADY_W<'_>

Bit 21 - Write '1' to enable interrupt for event TXREADY

pub fn rxready(&mut self) -> RXREADY_W<'_>

Bit 22 - Write '1' to enable interrupt for event RXREADY

pub fn mhrmatch(&mut self) -> MHRMATCH_W<'_>

Bit 23 - Write '1' to enable interrupt for event MHRMATCH

pub fn phyend(&mut self) -> PHYEND_W<'_>

Bit 27 - Write '1' to enable interrupt for event PHYEND

pub fn ctepresent(&mut self) -> CTEPRESENT_W<'_>

Bit 28 - Write '1' to enable interrupt for event CTEPRESENT

impl W<u32, Reg<u32, _INTENCLR>>

pub fn ready(&mut self) -> READY_W<'_>

Bit 0 - Write '1' to disable interrupt for event READY

pub fn address(&mut self) -> ADDRESS_W<'_>

Bit 1 - Write '1' to disable interrupt for event ADDRESS

pub fn payload(&mut self) -> PAYLOAD_W<'_>

Bit 2 - Write '1' to disable interrupt for event PAYLOAD

pub fn end(&mut self) -> END_W<'_>

Bit 3 - Write '1' to disable interrupt for event END

pub fn disabled(&mut self) -> DISABLED_W<'_>

Bit 4 - Write '1' to disable interrupt for event DISABLED

pub fn devmatch(&mut self) -> DEVMATCH_W<'_>

Bit 5 - Write '1' to disable interrupt for event DEVMATCH

pub fn devmiss(&mut self) -> DEVMISS_W<'_>

Bit 6 - Write '1' to disable interrupt for event DEVMISS

pub fn rssiend(&mut self) -> RSSIEND_W<'_>

Bit 7 - Write '1' to disable interrupt for event RSSIEND

pub fn bcmatch(&mut self) -> BCMATCH_W<'_>

Bit 10 - Write '1' to disable interrupt for event BCMATCH

pub fn crcok(&mut self) -> CRCOK_W<'_>

Bit 12 - Write '1' to disable interrupt for event CRCOK

pub fn crcerror(&mut self) -> CRCERROR_W<'_>

Bit 13 - Write '1' to disable interrupt for event CRCERROR

pub fn framestart(&mut self) -> FRAMESTART_W<'_>

Bit 14 - Write '1' to disable interrupt for event FRAMESTART

pub fn edend(&mut self) -> EDEND_W<'_>

Bit 15 - Write '1' to disable interrupt for event EDEND

pub fn edstopped(&mut self) -> EDSTOPPED_W<'_>

Bit 16 - Write '1' to disable interrupt for event EDSTOPPED

pub fn ccaidle(&mut self) -> CCAIDLE_W<'_>

Bit 17 - Write '1' to disable interrupt for event CCAIDLE

pub fn ccabusy(&mut self) -> CCABUSY_W<'_>

Bit 18 - Write '1' to disable interrupt for event CCABUSY

pub fn ccastopped(&mut self) -> CCASTOPPED_W<'_>

Bit 19 - Write '1' to disable interrupt for event CCASTOPPED

pub fn rateboost(&mut self) -> RATEBOOST_W<'_>

Bit 20 - Write '1' to disable interrupt for event RATEBOOST

pub fn txready(&mut self) -> TXREADY_W<'_>

Bit 21 - Write '1' to disable interrupt for event TXREADY

pub fn rxready(&mut self) -> RXREADY_W<'_>

Bit 22 - Write '1' to disable interrupt for event RXREADY

pub fn mhrmatch(&mut self) -> MHRMATCH_W<'_>

Bit 23 - Write '1' to disable interrupt for event MHRMATCH

pub fn phyend(&mut self) -> PHYEND_W<'_>

Bit 27 - Write '1' to disable interrupt for event PHYEND

pub fn ctepresent(&mut self) -> CTEPRESENT_W<'_>

Bit 28 - Write '1' to disable interrupt for event CTEPRESENT

impl W<u32, Reg<u32, _PACKETPTR>>

pub fn packetptr(&mut self) -> PACKETPTR_W<'_>

Bits 0:31 - Packet pointer

impl W<u32, Reg<u32, _FREQUENCY>>

pub fn frequency(&mut self) -> FREQUENCY_W<'_>

Bits 0:6 - Radio channel frequency

pub fn map(&mut self) -> MAP_W<'_>

Bit 8 - Channel map selection.

impl W<u32, Reg<u32, _TXPOWER>>

pub fn txpower(&mut self) -> TXPOWER_W<'_>

Bits 0:7 - RADIO output power

impl W<u32, Reg<u32, _MODE>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:3 - Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation.

impl W<u32, Reg<u32, _PCNF0>>

pub fn lflen(&mut self) -> LFLEN_W<'_>

Bits 0:3 - Length on air of LENGTH field in number of bits.

pub fn s0len(&mut self) -> S0LEN_W<'_>

Bit 8 - Length on air of S0 field in number of bytes.

pub fn s1len(&mut self) -> S1LEN_W<'_>

Bits 16:19 - Length on air of S1 field in number of bits.

pub fn s1incl(&mut self) -> S1INCL_W<'_>

Bit 20 - Include or exclude S1 field in RAM

pub fn cilen(&mut self) -> CILEN_W<'_>

Bits 22:23 - Length of code indicator - long range

pub fn plen(&mut self) -> PLEN_W<'_>

Bits 24:25 - Length of preamble on air. Decision point: TASKS_START task

pub fn crcinc(&mut self) -> CRCINC_W<'_>

Bit 26 - Indicates if LENGTH field contains CRC or not

pub fn termlen(&mut self) -> TERMLEN_W<'_>

Bits 29:30 - Length of TERM field in Long Range operation

impl W<u32, Reg<u32, _PCNF1>>

pub fn maxlen(&mut self) -> MAXLEN_W<'_>

Bits 0:7 - Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.

pub fn statlen(&mut self) -> STATLEN_W<'_>

Bits 8:15 - Static length in number of bytes

pub fn balen(&mut self) -> BALEN_W<'_>

Bits 16:18 - Base address length in number of bytes

pub fn endian(&mut self) -> ENDIAN_W<'_>

Bit 24 - On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields.

pub fn whiteen(&mut self) -> WHITEEN_W<'_>

Bit 25 - Enable or disable packet whitening

impl W<u32, Reg<u32, _BASE0>>

pub fn base0(&mut self) -> BASE0_W<'_>

Bits 0:31 - Base address 0

impl W<u32, Reg<u32, _BASE1>>

pub fn base1(&mut self) -> BASE1_W<'_>

Bits 0:31 - Base address 1

impl W<u32, Reg<u32, _PREFIX0>>

pub fn ap0(&mut self) -> AP0_W<'_>

Bits 0:7 - Address prefix 0.

pub fn ap1(&mut self) -> AP1_W<'_>

Bits 8:15 - Address prefix 1.

pub fn ap2(&mut self) -> AP2_W<'_>

Bits 16:23 - Address prefix 2.

pub fn ap3(&mut self) -> AP3_W<'_>

Bits 24:31 - Address prefix 3.

impl W<u32, Reg<u32, _PREFIX1>>

pub fn ap4(&mut self) -> AP4_W<'_>

Bits 0:7 - Address prefix 4.

pub fn ap5(&mut self) -> AP5_W<'_>

Bits 8:15 - Address prefix 5.

pub fn ap6(&mut self) -> AP6_W<'_>

Bits 16:23 - Address prefix 6.

pub fn ap7(&mut self) -> AP7_W<'_>

Bits 24:31 - Address prefix 7.

impl W<u32, Reg<u32, _TXADDRESS>>

pub fn txaddress(&mut self) -> TXADDRESS_W<'_>

Bits 0:2 - Transmit address select

impl W<u32, Reg<u32, _RXADDRESSES>>

pub fn addr0(&mut self) -> ADDR0_W<'_>

Bit 0 - Enable or disable reception on logical address 0.

pub fn addr1(&mut self) -> ADDR1_W<'_>

Bit 1 - Enable or disable reception on logical address 1.

pub fn addr2(&mut self) -> ADDR2_W<'_>

Bit 2 - Enable or disable reception on logical address 2.

pub fn addr3(&mut self) -> ADDR3_W<'_>

Bit 3 - Enable or disable reception on logical address 3.

pub fn addr4(&mut self) -> ADDR4_W<'_>

Bit 4 - Enable or disable reception on logical address 4.

pub fn addr5(&mut self) -> ADDR5_W<'_>

Bit 5 - Enable or disable reception on logical address 5.

pub fn addr6(&mut self) -> ADDR6_W<'_>

Bit 6 - Enable or disable reception on logical address 6.

pub fn addr7(&mut self) -> ADDR7_W<'_>

Bit 7 - Enable or disable reception on logical address 7.

impl W<u32, Reg<u32, _CRCCNF>>

pub fn len(&mut self) -> LEN_W<'_>

Bits 0:1 - CRC length in number of bytes.

pub fn skipaddr(&mut self) -> SKIPADDR_W<'_>

Bits 8:9 - Include or exclude packet address field out of CRC calculation.

impl W<u32, Reg<u32, _CRCPOLY>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:23 - CRC polynomial

impl W<u32, Reg<u32, _CRCINIT>>

pub fn crcinit(&mut self) -> CRCINIT_W<'_>

Bits 0:23 - CRC initial value

impl W<u32, Reg<u32, _TIFS>>

pub fn tifs(&mut self) -> TIFS_W<'_>

Bits 0:9 - Interframe spacing in us

impl W<u32, Reg<u32, _DATAWHITEIV>>

pub fn datawhiteiv(&mut self) -> DATAWHITEIV_W<'_>

Bits 0:6 - Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.

impl W<u32, Reg<u32, _BCC>>

pub fn bcc(&mut self) -> BCC_W<'_>

Bits 0:31 - Bit counter compare

impl W<u32, Reg<u32, _DAB>>

pub fn dab(&mut self) -> DAB_W<'_>

Bits 0:31 - Device address base segment n

impl W<u32, Reg<u32, _DAP>>

pub fn dap(&mut self) -> DAP_W<'_>

Bits 0:15 - Device address prefix n

impl W<u32, Reg<u32, _DACNF>>

pub fn ena0(&mut self) -> ENA0_W<'_>

Bit 0 - Enable or disable device address matching using device address 0

pub fn ena1(&mut self) -> ENA1_W<'_>

Bit 1 - Enable or disable device address matching using device address 1

pub fn ena2(&mut self) -> ENA2_W<'_>

Bit 2 - Enable or disable device address matching using device address 2

pub fn ena3(&mut self) -> ENA3_W<'_>

Bit 3 - Enable or disable device address matching using device address 3

pub fn ena4(&mut self) -> ENA4_W<'_>

Bit 4 - Enable or disable device address matching using device address 4

pub fn ena5(&mut self) -> ENA5_W<'_>

Bit 5 - Enable or disable device address matching using device address 5

pub fn ena6(&mut self) -> ENA6_W<'_>

Bit 6 - Enable or disable device address matching using device address 6

pub fn ena7(&mut self) -> ENA7_W<'_>

Bit 7 - Enable or disable device address matching using device address 7

pub fn txadd0(&mut self) -> TXADD0_W<'_>

Bit 8 - TxAdd for device address 0

pub fn txadd1(&mut self) -> TXADD1_W<'_>

Bit 9 - TxAdd for device address 1

pub fn txadd2(&mut self) -> TXADD2_W<'_>

Bit 10 - TxAdd for device address 2

pub fn txadd3(&mut self) -> TXADD3_W<'_>

Bit 11 - TxAdd for device address 3

pub fn txadd4(&mut self) -> TXADD4_W<'_>

Bit 12 - TxAdd for device address 4

pub fn txadd5(&mut self) -> TXADD5_W<'_>

Bit 13 - TxAdd for device address 5

pub fn txadd6(&mut self) -> TXADD6_W<'_>

Bit 14 - TxAdd for device address 6

pub fn txadd7(&mut self) -> TXADD7_W<'_>

Bit 15 - TxAdd for device address 7

impl W<u32, Reg<u32, _MHRMATCHCONF>>

pub fn mhrmatchconf(&mut self) -> MHRMATCHCONF_W<'_>

Bits 0:31 - Search pattern configuration

impl W<u32, Reg<u32, _MHRMATCHMAS>>

pub fn mhrmatchmas(&mut self) -> MHRMATCHMAS_W<'_>

Bits 0:31 - Pattern mask

impl W<u32, Reg<u32, _MODECNF0>>

pub fn ru(&mut self) -> RU_W<'_>

Bit 0 - Radio ramp-up time

pub fn dtx(&mut self) -> DTX_W<'_>

Bits 8:9 - Default TX value

impl W<u32, Reg<u32, _SFD>>

pub fn sfd(&mut self) -> SFD_W<'_>

Bits 0:7 - IEEE 802.15.4 start of frame delimiter

impl W<u32, Reg<u32, _EDCNT>>

pub fn edcnt(&mut self) -> EDCNT_W<'_>

Bits 0:20 - IEEE 802.15.4 energy detect loop count

impl W<u32, Reg<u32, _EDSAMPLE>>

pub fn edlvl(&mut self) -> EDLVL_W<'_>

Bits 0:7 - IEEE 802.15.4 energy detect level

impl W<u32, Reg<u32, _CCACTRL>>

pub fn ccamode(&mut self) -> CCAMODE_W<'_>

Bits 0:2 - CCA mode of operation

pub fn ccaedthres(&mut self) -> CCAEDTHRES_W<'_>

Bits 8:15 - CCA energy busy threshold. Used in all the CCA modes except CarrierMode.

pub fn ccacorrthres(&mut self) -> CCACORRTHRES_W<'_>

Bits 16:23 - CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode.

pub fn ccacorrcnt(&mut self) -> CCACORRCNT_W<'_>

Bits 24:31 - Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled.

impl W<u32, Reg<u32, _DFEMODE>>

pub fn dfeopmode(&mut self) -> DFEOPMODE_W<'_>

Bits 0:1 - Direction finding operation mode

impl W<u32, Reg<u32, _CTEINLINECONF>>

pub fn cteinlinectrlen(&mut self) -> CTEINLINECTRLEN_W<'_>

Bit 0 - Enable parsing of CTEInfo from received packet in BLE modes

pub fn cteinfoins1(&mut self) -> CTEINFOINS1_W<'_>

Bit 3 - CTEInfo is S1 byte or not

pub fn cteerrorhandling(&mut self) -> CTEERRORHANDLING_W<'_>

Bit 4 - Sampling/switching if CRC is not OK

pub fn ctetimevalidrange(&mut self) -> CTETIMEVALIDRANGE_W<'_>

Bits 6:7 - Max range of CTETime

pub fn cteinlinerxmode1us(&mut self) -> CTEINLINERXMODE1US_W<'_>

Bits 10:12 - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set

pub fn cteinlinerxmode2us(&mut self) -> CTEINLINERXMODE2US_W<'_>

Bits 13:15 - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set

pub fn s0conf(&mut self) -> S0CONF_W<'_>

Bits 16:23 - S0 bit pattern to match

pub fn s0mask(&mut self) -> S0MASK_W<'_>

Bits 24:31 - S0 bit mask to set which bit to match

impl W<u32, Reg<u32, _DFECTRL1>>

pub fn numberof8us(&mut self) -> NUMBEROF8US_W<'_>

Bits 0:5 - Length of the AoA/AoD procedure in number of 8 us units

pub fn dfeinextension(&mut self) -> DFEINEXTENSION_W<'_>

Bit 7 - Add CTE extension and do antenna switching/sampling in this extension

pub fn tswitchspacing(&mut self) -> TSWITCHSPACING_W<'_>

Bits 8:10 - Interval between every time the antenna is changed in the SWITCHING state

pub fn tsamplespacingref(&mut self) -> TSAMPLESPACINGREF_W<'_>

Bits 12:14 - Interval between samples in the REFERENCE period

pub fn sampletype(&mut self) -> SAMPLETYPE_W<'_>

Bit 15 - Whether to sample I/Q or magnitude/phase

pub fn tsamplespacing(&mut self) -> TSAMPLESPACING_W<'_>

Bits 16:18 - Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0

pub fn agcbackoffgain(&mut self) -> AGCBACKOFFGAIN_W<'_>

Bits 24:27 - Gain will be lowered by the specified number of gain steps at the start of CTE

impl W<u32, Reg<u32, _DFECTRL2>>

pub fn tswitchoffset(&mut self) -> TSWITCHOFFSET_W<'_>

Bits 0:12 - Signed value offset after the end of the CRC before starting switching in number of 16M cycles

pub fn tsampleoffset(&mut self) -> TSAMPLEOFFSET_W<'_>

Bits 16:27 - Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start

impl W<u32, Reg<u32, _SWITCHPATTERN>>

pub fn switchpattern(&mut self) -> SWITCHPATTERN_W<'_>

Bits 0:7 - Fill array of GPIO patterns for antenna control

impl W<u32, Reg<u32, _CLEARPATTERN>>

pub fn clearpattern(&mut self) -> CLEARPATTERN_W<'_>

Bit 0 - Clears GPIO pattern array for antenna control

impl W<u32, Reg<u32, _POWER>>

pub fn power(&mut self) -> POWER_W<'_>

Bit 0 - Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.

impl W<u32, Reg<u32, _RTS>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _TXD>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _CTS>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _RXD>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _TASKS_STARTRX>>

pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>

Bit 0 - Start UART receiver

impl W<u32, Reg<u32, _TASKS_STOPRX>>

pub fn tasks_stoprx(&mut self) -> TASKS_STOPRX_W<'_>

Bit 0 - Stop UART receiver

impl W<u32, Reg<u32, _TASKS_STARTTX>>

pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>

Bit 0 - Start UART transmitter

impl W<u32, Reg<u32, _TASKS_STOPTX>>

pub fn tasks_stoptx(&mut self) -> TASKS_STOPTX_W<'_>

Bit 0 - Stop UART transmitter

impl W<u32, Reg<u32, _TASKS_SUSPEND>>

pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>

Bit 0 - Suspend UART

impl W<u32, Reg<u32, _EVENTS_CTS>>

pub fn events_cts(&mut self) -> EVENTS_CTS_W<'_>

Bit 0 - CTS is activated (set low). Clear To Send.

impl W<u32, Reg<u32, _EVENTS_NCTS>>

pub fn events_ncts(&mut self) -> EVENTS_NCTS_W<'_>

Bit 0 - CTS is deactivated (set high). Not Clear To Send.

impl W<u32, Reg<u32, _EVENTS_RXDRDY>>

pub fn events_rxdrdy(&mut self) -> EVENTS_RXDRDY_W<'_>

Bit 0 - Data received in RXD

impl W<u32, Reg<u32, _EVENTS_TXDRDY>>

pub fn events_txdrdy(&mut self) -> EVENTS_TXDRDY_W<'_>

Bit 0 - Data sent from TXD

impl W<u32, Reg<u32, _EVENTS_ERROR>>

pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>

Bit 0 - Error detected

impl W<u32, Reg<u32, _EVENTS_RXTO>>

pub fn events_rxto(&mut self) -> EVENTS_RXTO_W<'_>

Bit 0 - Receiver timeout

impl W<u32, Reg<u32, _SHORTS>>

pub fn cts_startrx(&mut self) -> CTS_STARTRX_W<'_>

Bit 3 - Shortcut between event CTS and task STARTRX

pub fn ncts_stoprx(&mut self) -> NCTS_STOPRX_W<'_>

Bit 4 - Shortcut between event NCTS and task STOPRX

impl W<u32, Reg<u32, _INTENSET>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 0 - Write '1' to enable interrupt for event CTS

pub fn ncts(&mut self) -> NCTS_W<'_>

Bit 1 - Write '1' to enable interrupt for event NCTS

pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>

Bit 2 - Write '1' to enable interrupt for event RXDRDY

pub fn txdrdy(&mut self) -> TXDRDY_W<'_>

Bit 7 - Write '1' to enable interrupt for event TXDRDY

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Write '1' to enable interrupt for event ERROR

pub fn rxto(&mut self) -> RXTO_W<'_>

Bit 17 - Write '1' to enable interrupt for event RXTO

impl W<u32, Reg<u32, _INTENCLR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 0 - Write '1' to disable interrupt for event CTS

pub fn ncts(&mut self) -> NCTS_W<'_>

Bit 1 - Write '1' to disable interrupt for event NCTS

pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>

Bit 2 - Write '1' to disable interrupt for event RXDRDY

pub fn txdrdy(&mut self) -> TXDRDY_W<'_>

Bit 7 - Write '1' to disable interrupt for event TXDRDY

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Write '1' to disable interrupt for event ERROR

pub fn rxto(&mut self) -> RXTO_W<'_>

Bit 17 - Write '1' to disable interrupt for event RXTO

impl W<u32, Reg<u32, _ERRORSRC>>

pub fn overrun(&mut self) -> OVERRUN_W<'_>

Bit 0 - Overrun error

pub fn parity(&mut self) -> PARITY_W<'_>

Bit 1 - Parity error

pub fn framing(&mut self) -> FRAMING_W<'_>

Bit 2 - Framing error occurred

pub fn break_(&mut self) -> BREAK_W<'_>

Bit 3 - Break condition

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:3 - Enable or disable UART

impl W<u32, Reg<u32, _TXD>>

pub fn txd(&mut self) -> TXD_W<'_>

Bits 0:7 - TX data to be transferred

impl W<u32, Reg<u32, _BAUDRATE>>

pub fn baudrate(&mut self) -> BAUDRATE_W<'_>

Bits 0:31 - Baud rate

impl W<u32, Reg<u32, _CONFIG>>

pub fn hwfc(&mut self) -> HWFC_W<'_>

Bit 0 - Hardware flow control

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 1:3 - Parity

pub fn stop(&mut self) -> STOP_W<'_>

Bit 4 - Stop bits

impl W<u32, Reg<u32, _RTS>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _TXD>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _CTS>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _RXD>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - Data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:9 - Maximum number of bytes in receive buffer

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - Data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:9 - Maximum number of bytes in transmit buffer

impl W<u32, Reg<u32, _TASKS_STARTRX>>

pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>

Bit 0 - Start UART receiver

impl W<u32, Reg<u32, _TASKS_STOPRX>>

pub fn tasks_stoprx(&mut self) -> TASKS_STOPRX_W<'_>

Bit 0 - Stop UART receiver

impl W<u32, Reg<u32, _TASKS_STARTTX>>

pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>

Bit 0 - Start UART transmitter

impl W<u32, Reg<u32, _TASKS_STOPTX>>

pub fn tasks_stoptx(&mut self) -> TASKS_STOPTX_W<'_>

Bit 0 - Stop UART transmitter

impl W<u32, Reg<u32, _TASKS_FLUSHRX>>

pub fn tasks_flushrx(&mut self) -> TASKS_FLUSHRX_W<'_>

Bit 0 - Flush RX FIFO into RX buffer

impl W<u32, Reg<u32, _EVENTS_CTS>>

pub fn events_cts(&mut self) -> EVENTS_CTS_W<'_>

Bit 0 - CTS is activated (set low). Clear To Send.

impl W<u32, Reg<u32, _EVENTS_NCTS>>

pub fn events_ncts(&mut self) -> EVENTS_NCTS_W<'_>

Bit 0 - CTS is deactivated (set high). Not Clear To Send.

impl W<u32, Reg<u32, _EVENTS_RXDRDY>>

pub fn events_rxdrdy(&mut self) -> EVENTS_RXDRDY_W<'_>

Bit 0 - Data received in RXD (but potentially not yet transferred to Data RAM)

impl W<u32, Reg<u32, _EVENTS_ENDRX>>

pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>

Bit 0 - Receive buffer is filled up

impl W<u32, Reg<u32, _EVENTS_TXDRDY>>

pub fn events_txdrdy(&mut self) -> EVENTS_TXDRDY_W<'_>

Bit 0 - Data sent from TXD

impl W<u32, Reg<u32, _EVENTS_ENDTX>>

pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<'_>

Bit 0 - Last TX byte transmitted

impl W<u32, Reg<u32, _EVENTS_ERROR>>

pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>

Bit 0 - Error detected

impl W<u32, Reg<u32, _EVENTS_RXTO>>

pub fn events_rxto(&mut self) -> EVENTS_RXTO_W<'_>

Bit 0 - Receiver timeout

impl W<u32, Reg<u32, _EVENTS_RXSTARTED>>

pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<'_>

Bit 0 - UART receiver has started

impl W<u32, Reg<u32, _EVENTS_TXSTARTED>>

pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<'_>

Bit 0 - UART transmitter has started

impl W<u32, Reg<u32, _EVENTS_TXSTOPPED>>

pub fn events_txstopped(&mut self) -> EVENTS_TXSTOPPED_W<'_>

Bit 0 - Transmitter stopped

impl W<u32, Reg<u32, _SHORTS>>

pub fn endrx_startrx(&mut self) -> ENDRX_STARTRX_W<'_>

Bit 5 - Shortcut between event ENDRX and task STARTRX

pub fn endrx_stoprx(&mut self) -> ENDRX_STOPRX_W<'_>

Bit 6 - Shortcut between event ENDRX and task STOPRX

impl W<u32, Reg<u32, _INTEN>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 0 - Enable or disable interrupt for event CTS

pub fn ncts(&mut self) -> NCTS_W<'_>

Bit 1 - Enable or disable interrupt for event NCTS

pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>

Bit 2 - Enable or disable interrupt for event RXDRDY

pub fn endrx(&mut self) -> ENDRX_W<'_>

Bit 4 - Enable or disable interrupt for event ENDRX

pub fn txdrdy(&mut self) -> TXDRDY_W<'_>

Bit 7 - Enable or disable interrupt for event TXDRDY

pub fn endtx(&mut self) -> ENDTX_W<'_>

Bit 8 - Enable or disable interrupt for event ENDTX

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Enable or disable interrupt for event ERROR

pub fn rxto(&mut self) -> RXTO_W<'_>

Bit 17 - Enable or disable interrupt for event RXTO

pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>

Bit 19 - Enable or disable interrupt for event RXSTARTED

pub fn txstarted(&mut self) -> TXSTARTED_W<'_>

Bit 20 - Enable or disable interrupt for event TXSTARTED

pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>

Bit 22 - Enable or disable interrupt for event TXSTOPPED

impl W<u32, Reg<u32, _INTENSET>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 0 - Write '1' to enable interrupt for event CTS

pub fn ncts(&mut self) -> NCTS_W<'_>

Bit 1 - Write '1' to enable interrupt for event NCTS

pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>

Bit 2 - Write '1' to enable interrupt for event RXDRDY

pub fn endrx(&mut self) -> ENDRX_W<'_>

Bit 4 - Write '1' to enable interrupt for event ENDRX

pub fn txdrdy(&mut self) -> TXDRDY_W<'_>

Bit 7 - Write '1' to enable interrupt for event TXDRDY

pub fn endtx(&mut self) -> ENDTX_W<'_>

Bit 8 - Write '1' to enable interrupt for event ENDTX

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Write '1' to enable interrupt for event ERROR

pub fn rxto(&mut self) -> RXTO_W<'_>

Bit 17 - Write '1' to enable interrupt for event RXTO

pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>

Bit 19 - Write '1' to enable interrupt for event RXSTARTED

pub fn txstarted(&mut self) -> TXSTARTED_W<'_>

Bit 20 - Write '1' to enable interrupt for event TXSTARTED

pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>

Bit 22 - Write '1' to enable interrupt for event TXSTOPPED

impl W<u32, Reg<u32, _INTENCLR>>

pub fn cts(&mut self) -> CTS_W<'_>

Bit 0 - Write '1' to disable interrupt for event CTS

pub fn ncts(&mut self) -> NCTS_W<'_>

Bit 1 - Write '1' to disable interrupt for event NCTS

pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>

Bit 2 - Write '1' to disable interrupt for event RXDRDY

pub fn endrx(&mut self) -> ENDRX_W<'_>

Bit 4 - Write '1' to disable interrupt for event ENDRX

pub fn txdrdy(&mut self) -> TXDRDY_W<'_>

Bit 7 - Write '1' to disable interrupt for event TXDRDY

pub fn endtx(&mut self) -> ENDTX_W<'_>

Bit 8 - Write '1' to disable interrupt for event ENDTX

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Write '1' to disable interrupt for event ERROR

pub fn rxto(&mut self) -> RXTO_W<'_>

Bit 17 - Write '1' to disable interrupt for event RXTO

pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>

Bit 19 - Write '1' to disable interrupt for event RXSTARTED

pub fn txstarted(&mut self) -> TXSTARTED_W<'_>

Bit 20 - Write '1' to disable interrupt for event TXSTARTED

pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>

Bit 22 - Write '1' to disable interrupt for event TXSTOPPED

impl W<u32, Reg<u32, _ERRORSRC>>

pub fn overrun(&mut self) -> OVERRUN_W<'_>

Bit 0 - Overrun error

pub fn parity(&mut self) -> PARITY_W<'_>

Bit 1 - Parity error

pub fn framing(&mut self) -> FRAMING_W<'_>

Bit 2 - Framing error occurred

pub fn break_(&mut self) -> BREAK_W<'_>

Bit 3 - Break condition

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:3 - Enable or disable UARTE

impl W<u32, Reg<u32, _BAUDRATE>>

pub fn baudrate(&mut self) -> BAUDRATE_W<'_>

Bits 0:31 - Baud rate

impl W<u32, Reg<u32, _CONFIG>>

pub fn hwfc(&mut self) -> HWFC_W<'_>

Bit 0 - Hardware flow control

pub fn parity(&mut self) -> PARITY_W<'_>

Bits 1:3 - Parity

pub fn stop(&mut self) -> STOP_W<'_>

Bit 4 - Stop bits

impl W<u32, Reg<u32, _SCK>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _MOSI>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _MISO>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _EVENTS_READY>>

pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>

Bit 0 - TXD byte sent and RXD byte received

impl W<u32, Reg<u32, _INTENSET>>

pub fn ready(&mut self) -> READY_W<'_>

Bit 2 - Write '1' to enable interrupt for event READY

impl W<u32, Reg<u32, _INTENCLR>>

pub fn ready(&mut self) -> READY_W<'_>

Bit 2 - Write '1' to disable interrupt for event READY

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:3 - Enable or disable SPI

impl W<u32, Reg<u32, _TXD>>

pub fn txd(&mut self) -> TXD_W<'_>

Bits 0:7 - TX data to send. Double buffered

impl W<u32, Reg<u32, _FREQUENCY>>

pub fn frequency(&mut self) -> FREQUENCY_W<'_>

Bits 0:31 - SPI master data rate

impl W<u32, Reg<u32, _CONFIG>>

pub fn order(&mut self) -> ORDER_W<'_>

Bit 0 - Bit order

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 1 - Serial clock (SCK) phase

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 2 - Serial clock (SCK) polarity

impl W<u32, Reg<u32, _SCK>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _MOSI>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _MISO>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - Data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:13 - Maximum number of bytes in receive buffer

impl W<u32, Reg<u32, _LIST>>

pub fn list(&mut self) -> LIST_W<'_>

Bits 0:1 - List type

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - Data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:13 - Maximum number of bytes in transmit buffer

impl W<u32, Reg<u32, _LIST>>

pub fn list(&mut self) -> LIST_W<'_>

Bits 0:1 - List type

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Start SPI transaction

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop SPI transaction

impl W<u32, Reg<u32, _TASKS_SUSPEND>>

pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>

Bit 0 - Suspend SPI transaction

impl W<u32, Reg<u32, _TASKS_RESUME>>

pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>

Bit 0 - Resume SPI transaction

impl W<u32, Reg<u32, _EVENTS_STOPPED>>

pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>

Bit 0 - SPI transaction has stopped

impl W<u32, Reg<u32, _EVENTS_ENDRX>>

pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>

Bit 0 - End of RXD buffer reached

impl W<u32, Reg<u32, _EVENTS_END>>

pub fn events_end(&mut self) -> EVENTS_END_W<'_>

Bit 0 - End of RXD buffer and TXD buffer reached

impl W<u32, Reg<u32, _EVENTS_ENDTX>>

pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<'_>

Bit 0 - End of TXD buffer reached

impl W<u32, Reg<u32, _EVENTS_STARTED>>

pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>

Bit 0 - Transaction started

impl W<u32, Reg<u32, _SHORTS>>

pub fn end_start(&mut self) -> END_START_W<'_>

Bit 17 - Shortcut between event END and task START

impl W<u32, Reg<u32, _INTENSET>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to enable interrupt for event STOPPED

pub fn endrx(&mut self) -> ENDRX_W<'_>

Bit 4 - Write '1' to enable interrupt for event ENDRX

pub fn end(&mut self) -> END_W<'_>

Bit 6 - Write '1' to enable interrupt for event END

pub fn endtx(&mut self) -> ENDTX_W<'_>

Bit 8 - Write '1' to enable interrupt for event ENDTX

pub fn started(&mut self) -> STARTED_W<'_>

Bit 19 - Write '1' to enable interrupt for event STARTED

impl W<u32, Reg<u32, _INTENCLR>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to disable interrupt for event STOPPED

pub fn endrx(&mut self) -> ENDRX_W<'_>

Bit 4 - Write '1' to disable interrupt for event ENDRX

pub fn end(&mut self) -> END_W<'_>

Bit 6 - Write '1' to disable interrupt for event END

pub fn endtx(&mut self) -> ENDTX_W<'_>

Bit 8 - Write '1' to disable interrupt for event ENDTX

pub fn started(&mut self) -> STARTED_W<'_>

Bit 19 - Write '1' to disable interrupt for event STARTED

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:3 - Enable or disable SPIM

impl W<u32, Reg<u32, _FREQUENCY>>

pub fn frequency(&mut self) -> FREQUENCY_W<'_>

Bits 0:31 - SPI master data rate

impl W<u32, Reg<u32, _CONFIG>>

pub fn order(&mut self) -> ORDER_W<'_>

Bit 0 - Bit order

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 1 - Serial clock (SCK) phase

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 2 - Serial clock (SCK) polarity

impl W<u32, Reg<u32, _ORC>>

pub fn orc(&mut self) -> ORC_W<'_>

Bits 0:7 - Over-read character. Character clocked out in case and over-read of the TXD buffer.

impl W<u32, Reg<u32, _SCK>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _MISO>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _MOSI>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _CSN>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - RXD data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:13 - Maximum number of bytes in receive buffer

impl W<u32, Reg<u32, _LIST>>

pub fn list(&mut self) -> LIST_W<'_>

Bits 0:1 - List type

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - TXD data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:13 - Maximum number of bytes in transmit buffer

impl W<u32, Reg<u32, _LIST>>

pub fn list(&mut self) -> LIST_W<'_>

Bits 0:1 - List type

impl W<u32, Reg<u32, _TASKS_ACQUIRE>>

pub fn tasks_acquire(&mut self) -> TASKS_ACQUIRE_W<'_>

Bit 0 - Acquire SPI semaphore

impl W<u32, Reg<u32, _TASKS_RELEASE>>

pub fn tasks_release(&mut self) -> TASKS_RELEASE_W<'_>

Bit 0 - Release SPI semaphore, enabling the SPI slave to acquire it

impl W<u32, Reg<u32, _EVENTS_END>>

pub fn events_end(&mut self) -> EVENTS_END_W<'_>

Bit 0 - Granted transaction completed

impl W<u32, Reg<u32, _EVENTS_ENDRX>>

pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<'_>

Bit 0 - End of RXD buffer reached

impl W<u32, Reg<u32, _EVENTS_ACQUIRED>>

pub fn events_acquired(&mut self) -> EVENTS_ACQUIRED_W<'_>

Bit 0 - Semaphore acquired

impl W<u32, Reg<u32, _SHORTS>>

pub fn end_acquire(&mut self) -> END_ACQUIRE_W<'_>

Bit 2 - Shortcut between event END and task ACQUIRE

impl W<u32, Reg<u32, _INTENSET>>

pub fn end(&mut self) -> END_W<'_>

Bit 1 - Write '1' to enable interrupt for event END

pub fn endrx(&mut self) -> ENDRX_W<'_>

Bit 4 - Write '1' to enable interrupt for event ENDRX

pub fn acquired(&mut self) -> ACQUIRED_W<'_>

Bit 10 - Write '1' to enable interrupt for event ACQUIRED

impl W<u32, Reg<u32, _INTENCLR>>

pub fn end(&mut self) -> END_W<'_>

Bit 1 - Write '1' to disable interrupt for event END

pub fn endrx(&mut self) -> ENDRX_W<'_>

Bit 4 - Write '1' to disable interrupt for event ENDRX

pub fn acquired(&mut self) -> ACQUIRED_W<'_>

Bit 10 - Write '1' to disable interrupt for event ACQUIRED

impl W<u32, Reg<u32, _STATUS>>

pub fn overread(&mut self) -> OVERREAD_W<'_>

Bit 0 - TX buffer over-read detected, and prevented

pub fn overflow(&mut self) -> OVERFLOW_W<'_>

Bit 1 - RX buffer overflow detected, and prevented

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:3 - Enable or disable SPI slave

impl W<u32, Reg<u32, _CONFIG>>

pub fn order(&mut self) -> ORDER_W<'_>

Bit 0 - Bit order

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 1 - Serial clock (SCK) phase

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 2 - Serial clock (SCK) polarity

impl W<u32, Reg<u32, _DEF>>

pub fn def(&mut self) -> DEF_W<'_>

Bits 0:7 - Default character. Character clocked out in case of an ignored transaction.

impl W<u32, Reg<u32, _ORC>>

pub fn orc(&mut self) -> ORC_W<'_>

Bits 0:7 - Over-read character. Character clocked out after an over-read of the transmit buffer.

impl W<u32, Reg<u32, _SCL>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _SDA>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _TASKS_STARTRX>>

pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>

Bit 0 - Start TWI receive sequence

impl W<u32, Reg<u32, _TASKS_STARTTX>>

pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>

Bit 0 - Start TWI transmit sequence

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop TWI transaction

impl W<u32, Reg<u32, _TASKS_SUSPEND>>

pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>

Bit 0 - Suspend TWI transaction

impl W<u32, Reg<u32, _TASKS_RESUME>>

pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>

Bit 0 - Resume TWI transaction

impl W<u32, Reg<u32, _EVENTS_STOPPED>>

pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>

Bit 0 - TWI stopped

impl W<u32, Reg<u32, _EVENTS_RXDREADY>>

pub fn events_rxdready(&mut self) -> EVENTS_RXDREADY_W<'_>

Bit 0 - TWI RXD byte received

impl W<u32, Reg<u32, _EVENTS_TXDSENT>>

pub fn events_txdsent(&mut self) -> EVENTS_TXDSENT_W<'_>

Bit 0 - TWI TXD byte sent

impl W<u32, Reg<u32, _EVENTS_ERROR>>

pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>

Bit 0 - TWI error

impl W<u32, Reg<u32, _EVENTS_BB>>

pub fn events_bb(&mut self) -> EVENTS_BB_W<'_>

Bit 0 - TWI byte boundary, generated before each byte that is sent or received

impl W<u32, Reg<u32, _EVENTS_SUSPENDED>>

pub fn events_suspended(&mut self) -> EVENTS_SUSPENDED_W<'_>

Bit 0 - TWI entered the suspended state

impl W<u32, Reg<u32, _SHORTS>>

pub fn bb_suspend(&mut self) -> BB_SUSPEND_W<'_>

Bit 0 - Shortcut between event BB and task SUSPEND

pub fn bb_stop(&mut self) -> BB_STOP_W<'_>

Bit 1 - Shortcut between event BB and task STOP

impl W<u32, Reg<u32, _INTENSET>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to enable interrupt for event STOPPED

pub fn rxdready(&mut self) -> RXDREADY_W<'_>

Bit 2 - Write '1' to enable interrupt for event RXDREADY

pub fn txdsent(&mut self) -> TXDSENT_W<'_>

Bit 7 - Write '1' to enable interrupt for event TXDSENT

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Write '1' to enable interrupt for event ERROR

pub fn bb(&mut self) -> BB_W<'_>

Bit 14 - Write '1' to enable interrupt for event BB

pub fn suspended(&mut self) -> SUSPENDED_W<'_>

Bit 18 - Write '1' to enable interrupt for event SUSPENDED

impl W<u32, Reg<u32, _INTENCLR>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to disable interrupt for event STOPPED

pub fn rxdready(&mut self) -> RXDREADY_W<'_>

Bit 2 - Write '1' to disable interrupt for event RXDREADY

pub fn txdsent(&mut self) -> TXDSENT_W<'_>

Bit 7 - Write '1' to disable interrupt for event TXDSENT

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Write '1' to disable interrupt for event ERROR

pub fn bb(&mut self) -> BB_W<'_>

Bit 14 - Write '1' to disable interrupt for event BB

pub fn suspended(&mut self) -> SUSPENDED_W<'_>

Bit 18 - Write '1' to disable interrupt for event SUSPENDED

impl W<u32, Reg<u32, _ERRORSRC>>

pub fn overrun(&mut self) -> OVERRUN_W<'_>

Bit 0 - Overrun error

pub fn anack(&mut self) -> ANACK_W<'_>

Bit 1 - NACK received after sending the address (write '1' to clear)

pub fn dnack(&mut self) -> DNACK_W<'_>

Bit 2 - NACK received after sending a data byte (write '1' to clear)

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:3 - Enable or disable TWI

impl W<u32, Reg<u32, _TXD>>

pub fn txd(&mut self) -> TXD_W<'_>

Bits 0:7 - TXD register

impl W<u32, Reg<u32, _FREQUENCY>>

pub fn frequency(&mut self) -> FREQUENCY_W<'_>

Bits 0:31 - TWI master clock frequency

impl W<u32, Reg<u32, _ADDRESS>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Address used in the TWI transfer

impl W<u32, Reg<u32, _SCL>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _SDA>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - Data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:13 - Maximum number of bytes in receive buffer

impl W<u32, Reg<u32, _LIST>>

pub fn list(&mut self) -> LIST_W<'_>

Bits 0:2 - List type

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - Data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:13 - Maximum number of bytes in transmit buffer

impl W<u32, Reg<u32, _LIST>>

pub fn list(&mut self) -> LIST_W<'_>

Bits 0:2 - List type

impl W<u32, Reg<u32, _TASKS_STARTRX>>

pub fn tasks_startrx(&mut self) -> TASKS_STARTRX_W<'_>

Bit 0 - Start TWI receive sequence

impl W<u32, Reg<u32, _TASKS_STARTTX>>

pub fn tasks_starttx(&mut self) -> TASKS_STARTTX_W<'_>

Bit 0 - Start TWI transmit sequence

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop TWI transaction. Must be issued while the TWI master is not suspended.

impl W<u32, Reg<u32, _TASKS_SUSPEND>>

pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>

Bit 0 - Suspend TWI transaction

impl W<u32, Reg<u32, _TASKS_RESUME>>

pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>

Bit 0 - Resume TWI transaction

impl W<u32, Reg<u32, _EVENTS_STOPPED>>

pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>

Bit 0 - TWI stopped

impl W<u32, Reg<u32, _EVENTS_ERROR>>

pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>

Bit 0 - TWI error

impl W<u32, Reg<u32, _EVENTS_SUSPENDED>>

pub fn events_suspended(&mut self) -> EVENTS_SUSPENDED_W<'_>

Bit 0 - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.

impl W<u32, Reg<u32, _EVENTS_RXSTARTED>>

pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<'_>

Bit 0 - Receive sequence started

impl W<u32, Reg<u32, _EVENTS_TXSTARTED>>

pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<'_>

Bit 0 - Transmit sequence started

impl W<u32, Reg<u32, _EVENTS_LASTRX>>

pub fn events_lastrx(&mut self) -> EVENTS_LASTRX_W<'_>

Bit 0 - Byte boundary, starting to receive the last byte

impl W<u32, Reg<u32, _EVENTS_LASTTX>>

pub fn events_lasttx(&mut self) -> EVENTS_LASTTX_W<'_>

Bit 0 - Byte boundary, starting to transmit the last byte

impl W<u32, Reg<u32, _SHORTS>>

pub fn lasttx_startrx(&mut self) -> LASTTX_STARTRX_W<'_>

Bit 7 - Shortcut between event LASTTX and task STARTRX

pub fn lasttx_suspend(&mut self) -> LASTTX_SUSPEND_W<'_>

Bit 8 - Shortcut between event LASTTX and task SUSPEND

pub fn lasttx_stop(&mut self) -> LASTTX_STOP_W<'_>

Bit 9 - Shortcut between event LASTTX and task STOP

pub fn lastrx_starttx(&mut self) -> LASTRX_STARTTX_W<'_>

Bit 10 - Shortcut between event LASTRX and task STARTTX

pub fn lastrx_suspend(&mut self) -> LASTRX_SUSPEND_W<'_>

Bit 11 - Shortcut between event LASTRX and task SUSPEND

pub fn lastrx_stop(&mut self) -> LASTRX_STOP_W<'_>

Bit 12 - Shortcut between event LASTRX and task STOP

impl W<u32, Reg<u32, _INTEN>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Enable or disable interrupt for event STOPPED

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Enable or disable interrupt for event ERROR

pub fn suspended(&mut self) -> SUSPENDED_W<'_>

Bit 18 - Enable or disable interrupt for event SUSPENDED

pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>

Bit 19 - Enable or disable interrupt for event RXSTARTED

pub fn txstarted(&mut self) -> TXSTARTED_W<'_>

Bit 20 - Enable or disable interrupt for event TXSTARTED

pub fn lastrx(&mut self) -> LASTRX_W<'_>

Bit 23 - Enable or disable interrupt for event LASTRX

pub fn lasttx(&mut self) -> LASTTX_W<'_>

Bit 24 - Enable or disable interrupt for event LASTTX

impl W<u32, Reg<u32, _INTENSET>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to enable interrupt for event STOPPED

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Write '1' to enable interrupt for event ERROR

pub fn suspended(&mut self) -> SUSPENDED_W<'_>

Bit 18 - Write '1' to enable interrupt for event SUSPENDED

pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>

Bit 19 - Write '1' to enable interrupt for event RXSTARTED

pub fn txstarted(&mut self) -> TXSTARTED_W<'_>

Bit 20 - Write '1' to enable interrupt for event TXSTARTED

pub fn lastrx(&mut self) -> LASTRX_W<'_>

Bit 23 - Write '1' to enable interrupt for event LASTRX

pub fn lasttx(&mut self) -> LASTTX_W<'_>

Bit 24 - Write '1' to enable interrupt for event LASTTX

impl W<u32, Reg<u32, _INTENCLR>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to disable interrupt for event STOPPED

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Write '1' to disable interrupt for event ERROR

pub fn suspended(&mut self) -> SUSPENDED_W<'_>

Bit 18 - Write '1' to disable interrupt for event SUSPENDED

pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>

Bit 19 - Write '1' to disable interrupt for event RXSTARTED

pub fn txstarted(&mut self) -> TXSTARTED_W<'_>

Bit 20 - Write '1' to disable interrupt for event TXSTARTED

pub fn lastrx(&mut self) -> LASTRX_W<'_>

Bit 23 - Write '1' to disable interrupt for event LASTRX

pub fn lasttx(&mut self) -> LASTTX_W<'_>

Bit 24 - Write '1' to disable interrupt for event LASTTX

impl W<u32, Reg<u32, _ERRORSRC>>

pub fn overrun(&mut self) -> OVERRUN_W<'_>

Bit 0 - Overrun error

pub fn anack(&mut self) -> ANACK_W<'_>

Bit 1 - NACK received after sending the address (write '1' to clear)

pub fn dnack(&mut self) -> DNACK_W<'_>

Bit 2 - NACK received after sending a data byte (write '1' to clear)

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:3 - Enable or disable TWIM

impl W<u32, Reg<u32, _FREQUENCY>>

pub fn frequency(&mut self) -> FREQUENCY_W<'_>

Bits 0:31 - TWI master clock frequency

impl W<u32, Reg<u32, _ADDRESS>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - Address used in the TWI transfer

impl W<u32, Reg<u32, _SCL>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _SDA>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - RXD Data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:13 - Maximum number of bytes in RXD buffer

impl W<u32, Reg<u32, _LIST>>

pub fn list(&mut self) -> LIST_W<'_>

Bits 0:1 - List type

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - TXD Data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:13 - Maximum number of bytes in TXD buffer

impl W<u32, Reg<u32, _LIST>>

pub fn list(&mut self) -> LIST_W<'_>

Bits 0:1 - List type

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop TWI transaction

impl W<u32, Reg<u32, _TASKS_SUSPEND>>

pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<'_>

Bit 0 - Suspend TWI transaction

impl W<u32, Reg<u32, _TASKS_RESUME>>

pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<'_>

Bit 0 - Resume TWI transaction

impl W<u32, Reg<u32, _TASKS_PREPARERX>>

pub fn tasks_preparerx(&mut self) -> TASKS_PREPARERX_W<'_>

Bit 0 - Prepare the TWI slave to respond to a write command

impl W<u32, Reg<u32, _TASKS_PREPARETX>>

pub fn tasks_preparetx(&mut self) -> TASKS_PREPARETX_W<'_>

Bit 0 - Prepare the TWI slave to respond to a read command

impl W<u32, Reg<u32, _EVENTS_STOPPED>>

pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>

Bit 0 - TWI stopped

impl W<u32, Reg<u32, _EVENTS_ERROR>>

pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>

Bit 0 - TWI error

impl W<u32, Reg<u32, _EVENTS_RXSTARTED>>

pub fn events_rxstarted(&mut self) -> EVENTS_RXSTARTED_W<'_>

Bit 0 - Receive sequence started

impl W<u32, Reg<u32, _EVENTS_TXSTARTED>>

pub fn events_txstarted(&mut self) -> EVENTS_TXSTARTED_W<'_>

Bit 0 - Transmit sequence started

impl W<u32, Reg<u32, _EVENTS_WRITE>>

pub fn events_write(&mut self) -> EVENTS_WRITE_W<'_>

Bit 0 - Write command received

impl W<u32, Reg<u32, _EVENTS_READ>>

pub fn events_read(&mut self) -> EVENTS_READ_W<'_>

Bit 0 - Read command received

impl W<u32, Reg<u32, _SHORTS>>

pub fn write_suspend(&mut self) -> WRITE_SUSPEND_W<'_>

Bit 13 - Shortcut between event WRITE and task SUSPEND

pub fn read_suspend(&mut self) -> READ_SUSPEND_W<'_>

Bit 14 - Shortcut between event READ and task SUSPEND

impl W<u32, Reg<u32, _INTEN>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Enable or disable interrupt for event STOPPED

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Enable or disable interrupt for event ERROR

pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>

Bit 19 - Enable or disable interrupt for event RXSTARTED

pub fn txstarted(&mut self) -> TXSTARTED_W<'_>

Bit 20 - Enable or disable interrupt for event TXSTARTED

pub fn write(&mut self) -> WRITE_W<'_>

Bit 25 - Enable or disable interrupt for event WRITE

pub fn read(&mut self) -> READ_W<'_>

Bit 26 - Enable or disable interrupt for event READ

impl W<u32, Reg<u32, _INTENSET>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to enable interrupt for event STOPPED

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Write '1' to enable interrupt for event ERROR

pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>

Bit 19 - Write '1' to enable interrupt for event RXSTARTED

pub fn txstarted(&mut self) -> TXSTARTED_W<'_>

Bit 20 - Write '1' to enable interrupt for event TXSTARTED

pub fn write(&mut self) -> WRITE_W<'_>

Bit 25 - Write '1' to enable interrupt for event WRITE

pub fn read(&mut self) -> READ_W<'_>

Bit 26 - Write '1' to enable interrupt for event READ

impl W<u32, Reg<u32, _INTENCLR>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to disable interrupt for event STOPPED

pub fn error(&mut self) -> ERROR_W<'_>

Bit 9 - Write '1' to disable interrupt for event ERROR

pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>

Bit 19 - Write '1' to disable interrupt for event RXSTARTED

pub fn txstarted(&mut self) -> TXSTARTED_W<'_>

Bit 20 - Write '1' to disable interrupt for event TXSTARTED

pub fn write(&mut self) -> WRITE_W<'_>

Bit 25 - Write '1' to disable interrupt for event WRITE

pub fn read(&mut self) -> READ_W<'_>

Bit 26 - Write '1' to disable interrupt for event READ

impl W<u32, Reg<u32, _ERRORSRC>>

pub fn overflow(&mut self) -> OVERFLOW_W<'_>

Bit 0 - RX buffer overflow detected, and prevented

pub fn dnack(&mut self) -> DNACK_W<'_>

Bit 2 - NACK sent after receiving a data byte

pub fn overread(&mut self) -> OVERREAD_W<'_>

Bit 3 - TX buffer over-read detected, and prevented

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:3 - Enable or disable TWIS

impl W<u32, Reg<u32, _ADDRESS>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:6 - TWI slave address

impl W<u32, Reg<u32, _CONFIG>>

pub fn address0(&mut self) -> ADDRESS0_W<'_>

Bit 0 - Enable or disable address matching on ADDRESS[0]

pub fn address1(&mut self) -> ADDRESS1_W<'_>

Bit 1 - Enable or disable address matching on ADDRESS[1]

impl W<u32, Reg<u32, _ORC>>

pub fn orc(&mut self) -> ORC_W<'_>

Bits 0:7 - Over-read character. Character sent out in case of an over-read of the transmit buffer.

impl W<u32, Reg<u32, _TASKS_OUT>>

pub fn tasks_out(&mut self) -> TASKS_OUT_W<'_>

Bit 0 - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.

impl W<u32, Reg<u32, _TASKS_SET>>

pub fn tasks_set(&mut self) -> TASKS_SET_W<'_>

Bit 0 - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.

impl W<u32, Reg<u32, _TASKS_CLR>>

pub fn tasks_clr(&mut self) -> TASKS_CLR_W<'_>

Bit 0 - Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.

impl W<u32, Reg<u32, _EVENTS_IN>>

pub fn events_in(&mut self) -> EVENTS_IN_W<'_>

Bit 0 - Event generated from pin specified in CONFIG[n].PSEL

impl W<u32, Reg<u32, _EVENTS_PORT>>

pub fn events_port(&mut self) -> EVENTS_PORT_W<'_>

Bit 0 - Event generated from multiple input GPIO pins with SENSE mechanism enabled

impl W<u32, Reg<u32, _INTENSET>>

pub fn in0(&mut self) -> IN0_W<'_>

Bit 0 - Write '1' to enable interrupt for event IN[0]

pub fn in1(&mut self) -> IN1_W<'_>

Bit 1 - Write '1' to enable interrupt for event IN[1]

pub fn in2(&mut self) -> IN2_W<'_>

Bit 2 - Write '1' to enable interrupt for event IN[2]

pub fn in3(&mut self) -> IN3_W<'_>

Bit 3 - Write '1' to enable interrupt for event IN[3]

pub fn in4(&mut self) -> IN4_W<'_>

Bit 4 - Write '1' to enable interrupt for event IN[4]

pub fn in5(&mut self) -> IN5_W<'_>

Bit 5 - Write '1' to enable interrupt for event IN[5]

pub fn in6(&mut self) -> IN6_W<'_>

Bit 6 - Write '1' to enable interrupt for event IN[6]

pub fn in7(&mut self) -> IN7_W<'_>

Bit 7 - Write '1' to enable interrupt for event IN[7]

pub fn port(&mut self) -> PORT_W<'_>

Bit 31 - Write '1' to enable interrupt for event PORT

impl W<u32, Reg<u32, _INTENCLR>>

pub fn in0(&mut self) -> IN0_W<'_>

Bit 0 - Write '1' to disable interrupt for event IN[0]

pub fn in1(&mut self) -> IN1_W<'_>

Bit 1 - Write '1' to disable interrupt for event IN[1]

pub fn in2(&mut self) -> IN2_W<'_>

Bit 2 - Write '1' to disable interrupt for event IN[2]

pub fn in3(&mut self) -> IN3_W<'_>

Bit 3 - Write '1' to disable interrupt for event IN[3]

pub fn in4(&mut self) -> IN4_W<'_>

Bit 4 - Write '1' to disable interrupt for event IN[4]

pub fn in5(&mut self) -> IN5_W<'_>

Bit 5 - Write '1' to disable interrupt for event IN[5]

pub fn in6(&mut self) -> IN6_W<'_>

Bit 6 - Write '1' to disable interrupt for event IN[6]

pub fn in7(&mut self) -> IN7_W<'_>

Bit 7 - Write '1' to disable interrupt for event IN[7]

pub fn port(&mut self) -> PORT_W<'_>

Bit 31 - Write '1' to disable interrupt for event PORT

impl W<u32, Reg<u32, _CONFIG>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Mode

pub fn psel(&mut self) -> PSEL_W<'_>

Bits 8:12 - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event

pub fn polarity(&mut self) -> POLARITY_W<'_>

Bits 16:17 - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.

pub fn outinit(&mut self) -> OUTINIT_W<'_>

Bit 20 - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.

impl W<u32, Reg<u32, _LIMITH>>

pub fn limith(&mut self) -> LIMITH_W<'_>

Bit 0 - Last results is equal or above CH[n].LIMIT.HIGH

impl W<u32, Reg<u32, _LIMITL>>

pub fn limitl(&mut self) -> LIMITL_W<'_>

Bit 0 - Last results is equal or below CH[n].LIMIT.LOW

impl W<u32, Reg<u32, _PSELP>>

pub fn pselp(&mut self) -> PSELP_W<'_>

Bits 0:4 - Analog positive input channel

impl W<u32, Reg<u32, _PSELN>>

pub fn pseln(&mut self) -> PSELN_W<'_>

Bits 0:4 - Analog negative input, enables differential channel

impl W<u32, Reg<u32, _CONFIG>>

pub fn resp(&mut self) -> RESP_W<'_>

Bits 0:1 - Positive channel resistor control

pub fn resn(&mut self) -> RESN_W<'_>

Bits 4:5 - Negative channel resistor control

pub fn gain(&mut self) -> GAIN_W<'_>

Bits 8:10 - Gain control

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bit 12 - Reference control

pub fn tacq(&mut self) -> TACQ_W<'_>

Bits 16:18 - Acquisition time, the time the ADC uses to sample the input voltage

pub fn mode(&mut self) -> MODE_W<'_>

Bit 20 - Enable differential mode

pub fn burst(&mut self) -> BURST_W<'_>

Bit 24 - Enable burst mode

impl W<u32, Reg<u32, _LIMIT>>

pub fn low(&mut self) -> LOW_W<'_>

Bits 0:15 - Low level limit

pub fn high(&mut self) -> HIGH_W<'_>

Bits 16:31 - High level limit

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - Data pointer

impl W<u32, Reg<u32, _MAXCNT>>

pub fn maxcnt(&mut self) -> MAXCNT_W<'_>

Bits 0:14 - Maximum number of buffer words to transfer

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Start the ADC and prepare the result buffer in RAM

impl W<u32, Reg<u32, _TASKS_SAMPLE>>

pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W<'_>

Bit 0 - Take one ADC sample, if scan is enabled all channels are sampled

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop the ADC and terminate any on-going conversion

impl W<u32, Reg<u32, _TASKS_CALIBRATEOFFSET>>

pub fn tasks_calibrateoffset(&mut self) -> TASKS_CALIBRATEOFFSET_W<'_>

Bit 0 - Starts offset auto-calibration

impl W<u32, Reg<u32, _EVENTS_STARTED>>

pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>

Bit 0 - The ADC has started

impl W<u32, Reg<u32, _EVENTS_END>>

pub fn events_end(&mut self) -> EVENTS_END_W<'_>

Bit 0 - The ADC has filled up the Result buffer

impl W<u32, Reg<u32, _EVENTS_DONE>>

pub fn events_done(&mut self) -> EVENTS_DONE_W<'_>

Bit 0 - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.

impl W<u32, Reg<u32, _EVENTS_RESULTDONE>>

pub fn events_resultdone(&mut self) -> EVENTS_RESULTDONE_W<'_>

Bit 0 - A result is ready to get transferred to RAM.

impl W<u32, Reg<u32, _EVENTS_CALIBRATEDONE>>

pub fn events_calibratedone(&mut self) -> EVENTS_CALIBRATEDONE_W<'_>

Bit 0 - Calibration is complete

impl W<u32, Reg<u32, _EVENTS_STOPPED>>

pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>

Bit 0 - The ADC has stopped

impl W<u32, Reg<u32, _INTEN>>

pub fn started(&mut self) -> STARTED_W<'_>

Bit 0 - Enable or disable interrupt for event STARTED

pub fn end(&mut self) -> END_W<'_>

Bit 1 - Enable or disable interrupt for event END

pub fn done(&mut self) -> DONE_W<'_>

Bit 2 - Enable or disable interrupt for event DONE

pub fn resultdone(&mut self) -> RESULTDONE_W<'_>

Bit 3 - Enable or disable interrupt for event RESULTDONE

pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>

Bit 4 - Enable or disable interrupt for event CALIBRATEDONE

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 5 - Enable or disable interrupt for event STOPPED

pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>

Bit 6 - Enable or disable interrupt for event CH0LIMITH

pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>

Bit 7 - Enable or disable interrupt for event CH0LIMITL

pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>

Bit 8 - Enable or disable interrupt for event CH1LIMITH

pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>

Bit 9 - Enable or disable interrupt for event CH1LIMITL

pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>

Bit 10 - Enable or disable interrupt for event CH2LIMITH

pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>

Bit 11 - Enable or disable interrupt for event CH2LIMITL

pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>

Bit 12 - Enable or disable interrupt for event CH3LIMITH

pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>

Bit 13 - Enable or disable interrupt for event CH3LIMITL

pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>

Bit 14 - Enable or disable interrupt for event CH4LIMITH

pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>

Bit 15 - Enable or disable interrupt for event CH4LIMITL

pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>

Bit 16 - Enable or disable interrupt for event CH5LIMITH

pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>

Bit 17 - Enable or disable interrupt for event CH5LIMITL

pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>

Bit 18 - Enable or disable interrupt for event CH6LIMITH

pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>

Bit 19 - Enable or disable interrupt for event CH6LIMITL

pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>

Bit 20 - Enable or disable interrupt for event CH7LIMITH

pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>

Bit 21 - Enable or disable interrupt for event CH7LIMITL

impl W<u32, Reg<u32, _INTENSET>>

pub fn started(&mut self) -> STARTED_W<'_>

Bit 0 - Write '1' to enable interrupt for event STARTED

pub fn end(&mut self) -> END_W<'_>

Bit 1 - Write '1' to enable interrupt for event END

pub fn done(&mut self) -> DONE_W<'_>

Bit 2 - Write '1' to enable interrupt for event DONE

pub fn resultdone(&mut self) -> RESULTDONE_W<'_>

Bit 3 - Write '1' to enable interrupt for event RESULTDONE

pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>

Bit 4 - Write '1' to enable interrupt for event CALIBRATEDONE

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 5 - Write '1' to enable interrupt for event STOPPED

pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>

Bit 6 - Write '1' to enable interrupt for event CH0LIMITH

pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>

Bit 7 - Write '1' to enable interrupt for event CH0LIMITL

pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>

Bit 8 - Write '1' to enable interrupt for event CH1LIMITH

pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>

Bit 9 - Write '1' to enable interrupt for event CH1LIMITL

pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>

Bit 10 - Write '1' to enable interrupt for event CH2LIMITH

pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>

Bit 11 - Write '1' to enable interrupt for event CH2LIMITL

pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>

Bit 12 - Write '1' to enable interrupt for event CH3LIMITH

pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>

Bit 13 - Write '1' to enable interrupt for event CH3LIMITL

pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>

Bit 14 - Write '1' to enable interrupt for event CH4LIMITH

pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>

Bit 15 - Write '1' to enable interrupt for event CH4LIMITL

pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>

Bit 16 - Write '1' to enable interrupt for event CH5LIMITH

pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>

Bit 17 - Write '1' to enable interrupt for event CH5LIMITL

pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>

Bit 18 - Write '1' to enable interrupt for event CH6LIMITH

pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>

Bit 19 - Write '1' to enable interrupt for event CH6LIMITL

pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>

Bit 20 - Write '1' to enable interrupt for event CH7LIMITH

pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>

Bit 21 - Write '1' to enable interrupt for event CH7LIMITL

impl W<u32, Reg<u32, _INTENCLR>>

pub fn started(&mut self) -> STARTED_W<'_>

Bit 0 - Write '1' to disable interrupt for event STARTED

pub fn end(&mut self) -> END_W<'_>

Bit 1 - Write '1' to disable interrupt for event END

pub fn done(&mut self) -> DONE_W<'_>

Bit 2 - Write '1' to disable interrupt for event DONE

pub fn resultdone(&mut self) -> RESULTDONE_W<'_>

Bit 3 - Write '1' to disable interrupt for event RESULTDONE

pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>

Bit 4 - Write '1' to disable interrupt for event CALIBRATEDONE

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 5 - Write '1' to disable interrupt for event STOPPED

pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>

Bit 6 - Write '1' to disable interrupt for event CH0LIMITH

pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>

Bit 7 - Write '1' to disable interrupt for event CH0LIMITL

pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>

Bit 8 - Write '1' to disable interrupt for event CH1LIMITH

pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>

Bit 9 - Write '1' to disable interrupt for event CH1LIMITL

pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>

Bit 10 - Write '1' to disable interrupt for event CH2LIMITH

pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>

Bit 11 - Write '1' to disable interrupt for event CH2LIMITL

pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>

Bit 12 - Write '1' to disable interrupt for event CH3LIMITH

pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>

Bit 13 - Write '1' to disable interrupt for event CH3LIMITL

pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>

Bit 14 - Write '1' to disable interrupt for event CH4LIMITH

pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>

Bit 15 - Write '1' to disable interrupt for event CH4LIMITL

pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>

Bit 16 - Write '1' to disable interrupt for event CH5LIMITH

pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>

Bit 17 - Write '1' to disable interrupt for event CH5LIMITL

pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>

Bit 18 - Write '1' to disable interrupt for event CH6LIMITH

pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>

Bit 19 - Write '1' to disable interrupt for event CH6LIMITL

pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>

Bit 20 - Write '1' to disable interrupt for event CH7LIMITH

pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>

Bit 21 - Write '1' to disable interrupt for event CH7LIMITL

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enable or disable ADC

impl W<u32, Reg<u32, _RESOLUTION>>

pub fn val(&mut self) -> VAL_W<'_>

Bits 0:2 - Set the resolution

impl W<u32, Reg<u32, _OVERSAMPLE>>

pub fn oversample(&mut self) -> OVERSAMPLE_W<'_>

Bits 0:3 - Oversample control

impl W<u32, Reg<u32, _SAMPLERATE>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:10 - Capture and compare value. Sample rate is 16 MHz/CC

pub fn mode(&mut self) -> MODE_W<'_>

Bit 12 - Select mode for sample rate control

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Start Timer

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop Timer

impl W<u32, Reg<u32, _TASKS_COUNT>>

pub fn tasks_count(&mut self) -> TASKS_COUNT_W<'_>

Bit 0 - Increment Timer (Counter mode only)

impl W<u32, Reg<u32, _TASKS_CLEAR>>

pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W<'_>

Bit 0 - Clear time

impl W<u32, Reg<u32, _TASKS_SHUTDOWN>>

pub fn tasks_shutdown(&mut self) -> TASKS_SHUTDOWN_W<'_>

Bit 0 - Deprecated field - Shut down timer

impl W<u32, Reg<u32, _TASKS_CAPTURE>>

pub fn tasks_capture(&mut self) -> TASKS_CAPTURE_W<'_>

Bit 0 - Capture Timer value to CC[n] register

impl W<u32, Reg<u32, _EVENTS_COMPARE>>

pub fn events_compare(&mut self) -> EVENTS_COMPARE_W<'_>

Bit 0 - Compare event on CC[n] match

impl W<u32, Reg<u32, _SHORTS>>

pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W<'_>

Bit 0 - Shortcut between event COMPARE[0] and task CLEAR

pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W<'_>

Bit 1 - Shortcut between event COMPARE[1] and task CLEAR

pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W<'_>

Bit 2 - Shortcut between event COMPARE[2] and task CLEAR

pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W<'_>

Bit 3 - Shortcut between event COMPARE[3] and task CLEAR

pub fn compare4_clear(&mut self) -> COMPARE4_CLEAR_W<'_>

Bit 4 - Shortcut between event COMPARE[4] and task CLEAR

pub fn compare5_clear(&mut self) -> COMPARE5_CLEAR_W<'_>

Bit 5 - Shortcut between event COMPARE[5] and task CLEAR

pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W<'_>

Bit 8 - Shortcut between event COMPARE[0] and task STOP

pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W<'_>

Bit 9 - Shortcut between event COMPARE[1] and task STOP

pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W<'_>

Bit 10 - Shortcut between event COMPARE[2] and task STOP

pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W<'_>

Bit 11 - Shortcut between event COMPARE[3] and task STOP

pub fn compare4_stop(&mut self) -> COMPARE4_STOP_W<'_>

Bit 12 - Shortcut between event COMPARE[4] and task STOP

pub fn compare5_stop(&mut self) -> COMPARE5_STOP_W<'_>

Bit 13 - Shortcut between event COMPARE[5] and task STOP

impl W<u32, Reg<u32, _INTENSET>>

pub fn compare0(&mut self) -> COMPARE0_W<'_>

Bit 16 - Write '1' to enable interrupt for event COMPARE[0]

pub fn compare1(&mut self) -> COMPARE1_W<'_>

Bit 17 - Write '1' to enable interrupt for event COMPARE[1]

pub fn compare2(&mut self) -> COMPARE2_W<'_>

Bit 18 - Write '1' to enable interrupt for event COMPARE[2]

pub fn compare3(&mut self) -> COMPARE3_W<'_>

Bit 19 - Write '1' to enable interrupt for event COMPARE[3]

pub fn compare4(&mut self) -> COMPARE4_W<'_>

Bit 20 - Write '1' to enable interrupt for event COMPARE[4]

pub fn compare5(&mut self) -> COMPARE5_W<'_>

Bit 21 - Write '1' to enable interrupt for event COMPARE[5]

impl W<u32, Reg<u32, _INTENCLR>>

pub fn compare0(&mut self) -> COMPARE0_W<'_>

Bit 16 - Write '1' to disable interrupt for event COMPARE[0]

pub fn compare1(&mut self) -> COMPARE1_W<'_>

Bit 17 - Write '1' to disable interrupt for event COMPARE[1]

pub fn compare2(&mut self) -> COMPARE2_W<'_>

Bit 18 - Write '1' to disable interrupt for event COMPARE[2]

pub fn compare3(&mut self) -> COMPARE3_W<'_>

Bit 19 - Write '1' to disable interrupt for event COMPARE[3]

pub fn compare4(&mut self) -> COMPARE4_W<'_>

Bit 20 - Write '1' to disable interrupt for event COMPARE[4]

pub fn compare5(&mut self) -> COMPARE5_W<'_>

Bit 21 - Write '1' to disable interrupt for event COMPARE[5]

impl W<u32, Reg<u32, _MODE>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Timer mode

impl W<u32, Reg<u32, _BITMODE>>

pub fn bitmode(&mut self) -> BITMODE_W<'_>

Bits 0:1 - Timer bit width

impl W<u32, Reg<u32, _PRESCALER>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:3 - Prescaler value

impl W<u32, Reg<u32, _CC>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:31 - Capture/Compare value

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Start RTC COUNTER

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop RTC COUNTER

impl W<u32, Reg<u32, _TASKS_CLEAR>>

pub fn tasks_clear(&mut self) -> TASKS_CLEAR_W<'_>

Bit 0 - Clear RTC COUNTER

impl W<u32, Reg<u32, _TASKS_TRIGOVRFLW>>

pub fn tasks_trigovrflw(&mut self) -> TASKS_TRIGOVRFLW_W<'_>

Bit 0 - Set COUNTER to 0xFFFFF0

impl W<u32, Reg<u32, _EVENTS_TICK>>

pub fn events_tick(&mut self) -> EVENTS_TICK_W<'_>

Bit 0 - Event on COUNTER increment

impl W<u32, Reg<u32, _EVENTS_OVRFLW>>

pub fn events_ovrflw(&mut self) -> EVENTS_OVRFLW_W<'_>

Bit 0 - Event on COUNTER overflow

impl W<u32, Reg<u32, _EVENTS_COMPARE>>

pub fn events_compare(&mut self) -> EVENTS_COMPARE_W<'_>

Bit 0 - Compare event on CC[n] match

impl W<u32, Reg<u32, _INTENSET>>

pub fn tick(&mut self) -> TICK_W<'_>

Bit 0 - Write '1' to enable interrupt for event TICK

pub fn ovrflw(&mut self) -> OVRFLW_W<'_>

Bit 1 - Write '1' to enable interrupt for event OVRFLW

pub fn compare0(&mut self) -> COMPARE0_W<'_>

Bit 16 - Write '1' to enable interrupt for event COMPARE[0]

pub fn compare1(&mut self) -> COMPARE1_W<'_>

Bit 17 - Write '1' to enable interrupt for event COMPARE[1]

pub fn compare2(&mut self) -> COMPARE2_W<'_>

Bit 18 - Write '1' to enable interrupt for event COMPARE[2]

pub fn compare3(&mut self) -> COMPARE3_W<'_>

Bit 19 - Write '1' to enable interrupt for event COMPARE[3]

impl W<u32, Reg<u32, _INTENCLR>>

pub fn tick(&mut self) -> TICK_W<'_>

Bit 0 - Write '1' to disable interrupt for event TICK

pub fn ovrflw(&mut self) -> OVRFLW_W<'_>

Bit 1 - Write '1' to disable interrupt for event OVRFLW

pub fn compare0(&mut self) -> COMPARE0_W<'_>

Bit 16 - Write '1' to disable interrupt for event COMPARE[0]

pub fn compare1(&mut self) -> COMPARE1_W<'_>

Bit 17 - Write '1' to disable interrupt for event COMPARE[1]

pub fn compare2(&mut self) -> COMPARE2_W<'_>

Bit 18 - Write '1' to disable interrupt for event COMPARE[2]

pub fn compare3(&mut self) -> COMPARE3_W<'_>

Bit 19 - Write '1' to disable interrupt for event COMPARE[3]

impl W<u32, Reg<u32, _EVTEN>>

pub fn tick(&mut self) -> TICK_W<'_>

Bit 0 - Enable or disable event routing for event TICK

pub fn ovrflw(&mut self) -> OVRFLW_W<'_>

Bit 1 - Enable or disable event routing for event OVRFLW

pub fn compare0(&mut self) -> COMPARE0_W<'_>

Bit 16 - Enable or disable event routing for event COMPARE[0]

pub fn compare1(&mut self) -> COMPARE1_W<'_>

Bit 17 - Enable or disable event routing for event COMPARE[1]

pub fn compare2(&mut self) -> COMPARE2_W<'_>

Bit 18 - Enable or disable event routing for event COMPARE[2]

pub fn compare3(&mut self) -> COMPARE3_W<'_>

Bit 19 - Enable or disable event routing for event COMPARE[3]

impl W<u32, Reg<u32, _EVTENSET>>

pub fn tick(&mut self) -> TICK_W<'_>

Bit 0 - Write '1' to enable event routing for event TICK

pub fn ovrflw(&mut self) -> OVRFLW_W<'_>

Bit 1 - Write '1' to enable event routing for event OVRFLW

pub fn compare0(&mut self) -> COMPARE0_W<'_>

Bit 16 - Write '1' to enable event routing for event COMPARE[0]

pub fn compare1(&mut self) -> COMPARE1_W<'_>

Bit 17 - Write '1' to enable event routing for event COMPARE[1]

pub fn compare2(&mut self) -> COMPARE2_W<'_>

Bit 18 - Write '1' to enable event routing for event COMPARE[2]

pub fn compare3(&mut self) -> COMPARE3_W<'_>

Bit 19 - Write '1' to enable event routing for event COMPARE[3]

impl W<u32, Reg<u32, _EVTENCLR>>

pub fn tick(&mut self) -> TICK_W<'_>

Bit 0 - Write '1' to disable event routing for event TICK

pub fn ovrflw(&mut self) -> OVRFLW_W<'_>

Bit 1 - Write '1' to disable event routing for event OVRFLW

pub fn compare0(&mut self) -> COMPARE0_W<'_>

Bit 16 - Write '1' to disable event routing for event COMPARE[0]

pub fn compare1(&mut self) -> COMPARE1_W<'_>

Bit 17 - Write '1' to disable event routing for event COMPARE[1]

pub fn compare2(&mut self) -> COMPARE2_W<'_>

Bit 18 - Write '1' to disable event routing for event COMPARE[2]

pub fn compare3(&mut self) -> COMPARE3_W<'_>

Bit 19 - Write '1' to disable event routing for event COMPARE[3]

impl W<u32, Reg<u32, _PRESCALER>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:11 - Prescaler value

impl W<u32, Reg<u32, _CC>>

pub fn compare(&mut self) -> COMPARE_W<'_>

Bits 0:23 - Compare value

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Start temperature measurement

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop temperature measurement

impl W<u32, Reg<u32, _EVENTS_DATARDY>>

pub fn events_datardy(&mut self) -> EVENTS_DATARDY_W<'_>

Bit 0 - Temperature measurement complete, data ready

impl W<u32, Reg<u32, _INTENSET>>

pub fn datardy(&mut self) -> DATARDY_W<'_>

Bit 0 - Write '1' to enable interrupt for event DATARDY

impl W<u32, Reg<u32, _INTENCLR>>

pub fn datardy(&mut self) -> DATARDY_W<'_>

Bit 0 - Write '1' to disable interrupt for event DATARDY

impl W<u32, Reg<u32, _A0>>

pub fn a0(&mut self) -> A0_W<'_>

Bits 0:11 - Slope of 1st piece wise linear function

impl W<u32, Reg<u32, _A1>>

pub fn a1(&mut self) -> A1_W<'_>

Bits 0:11 - Slope of 2nd piece wise linear function

impl W<u32, Reg<u32, _A2>>

pub fn a2(&mut self) -> A2_W<'_>

Bits 0:11 - Slope of 3rd piece wise linear function

impl W<u32, Reg<u32, _A3>>

pub fn a3(&mut self) -> A3_W<'_>

Bits 0:11 - Slope of 4th piece wise linear function

impl W<u32, Reg<u32, _A4>>

pub fn a4(&mut self) -> A4_W<'_>

Bits 0:11 - Slope of 5th piece wise linear function

impl W<u32, Reg<u32, _A5>>

pub fn a5(&mut self) -> A5_W<'_>

Bits 0:11 - Slope of 6th piece wise linear function

impl W<u32, Reg<u32, _B0>>

pub fn b0(&mut self) -> B0_W<'_>

Bits 0:13 - y-intercept of 1st piece wise linear function

impl W<u32, Reg<u32, _B1>>

pub fn b1(&mut self) -> B1_W<'_>

Bits 0:13 - y-intercept of 2nd piece wise linear function

impl W<u32, Reg<u32, _B2>>

pub fn b2(&mut self) -> B2_W<'_>

Bits 0:13 - y-intercept of 3rd piece wise linear function

impl W<u32, Reg<u32, _B3>>

pub fn b3(&mut self) -> B3_W<'_>

Bits 0:13 - y-intercept of 4th piece wise linear function

impl W<u32, Reg<u32, _B4>>

pub fn b4(&mut self) -> B4_W<'_>

Bits 0:13 - y-intercept of 5th piece wise linear function

impl W<u32, Reg<u32, _B5>>

pub fn b5(&mut self) -> B5_W<'_>

Bits 0:13 - y-intercept of 6th piece wise linear function

impl W<u32, Reg<u32, _T0>>

pub fn t0(&mut self) -> T0_W<'_>

Bits 0:7 - End point of 1st piece wise linear function

impl W<u32, Reg<u32, _T1>>

pub fn t1(&mut self) -> T1_W<'_>

Bits 0:7 - End point of 2nd piece wise linear function

impl W<u32, Reg<u32, _T2>>

pub fn t2(&mut self) -> T2_W<'_>

Bits 0:7 - End point of 3rd piece wise linear function

impl W<u32, Reg<u32, _T3>>

pub fn t3(&mut self) -> T3_W<'_>

Bits 0:7 - End point of 4th piece wise linear function

impl W<u32, Reg<u32, _T4>>

pub fn t4(&mut self) -> T4_W<'_>

Bits 0:7 - End point of 5th piece wise linear function

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Task starting the random number generator

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Task stopping the random number generator

impl W<u32, Reg<u32, _EVENTS_VALRDY>>

pub fn events_valrdy(&mut self) -> EVENTS_VALRDY_W<'_>

Bit 0 - Event being generated for every new random number written to the VALUE register

impl W<u32, Reg<u32, _SHORTS>>

pub fn valrdy_stop(&mut self) -> VALRDY_STOP_W<'_>

Bit 0 - Shortcut between event VALRDY and task STOP

impl W<u32, Reg<u32, _INTENSET>>

pub fn valrdy(&mut self) -> VALRDY_W<'_>

Bit 0 - Write '1' to enable interrupt for event VALRDY

impl W<u32, Reg<u32, _INTENCLR>>

pub fn valrdy(&mut self) -> VALRDY_W<'_>

Bit 0 - Write '1' to disable interrupt for event VALRDY

impl W<u32, Reg<u32, _CONFIG>>

pub fn dercen(&mut self) -> DERCEN_W<'_>

Bit 0 - Bias correction

impl W<u32, Reg<u32, _TASKS_STARTECB>>

pub fn tasks_startecb(&mut self) -> TASKS_STARTECB_W<'_>

Bit 0 - Start ECB block encrypt

impl W<u32, Reg<u32, _TASKS_STOPECB>>

pub fn tasks_stopecb(&mut self) -> TASKS_STOPECB_W<'_>

Bit 0 - Abort a possible executing ECB operation

impl W<u32, Reg<u32, _EVENTS_ENDECB>>

pub fn events_endecb(&mut self) -> EVENTS_ENDECB_W<'_>

Bit 0 - ECB block encrypt complete

impl W<u32, Reg<u32, _EVENTS_ERRORECB>>

pub fn events_errorecb(&mut self) -> EVENTS_ERRORECB_W<'_>

Bit 0 - ECB block encrypt aborted because of a STOPECB task or due to an error

impl W<u32, Reg<u32, _INTENSET>>

pub fn endecb(&mut self) -> ENDECB_W<'_>

Bit 0 - Write '1' to enable interrupt for event ENDECB

pub fn errorecb(&mut self) -> ERRORECB_W<'_>

Bit 1 - Write '1' to enable interrupt for event ERRORECB

impl W<u32, Reg<u32, _INTENCLR>>

pub fn endecb(&mut self) -> ENDECB_W<'_>

Bit 0 - Write '1' to disable interrupt for event ENDECB

pub fn errorecb(&mut self) -> ERRORECB_W<'_>

Bit 1 - Write '1' to disable interrupt for event ERRORECB

impl W<u32, Reg<u32, _ECBDATAPTR>>

pub fn ecbdataptr(&mut self) -> ECBDATAPTR_W<'_>

Bits 0:31 - Pointer to the ECB data structure (see Table 1 ECB data structure overview)

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Start resolving addresses based on IRKs specified in the IRK data structure

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop resolving addresses

impl W<u32, Reg<u32, _EVENTS_END>>

pub fn events_end(&mut self) -> EVENTS_END_W<'_>

Bit 0 - Address resolution procedure complete

impl W<u32, Reg<u32, _EVENTS_RESOLVED>>

pub fn events_resolved(&mut self) -> EVENTS_RESOLVED_W<'_>

Bit 0 - Address resolved

impl W<u32, Reg<u32, _EVENTS_NOTRESOLVED>>

pub fn events_notresolved(&mut self) -> EVENTS_NOTRESOLVED_W<'_>

Bit 0 - Address not resolved

impl W<u32, Reg<u32, _INTENSET>>

pub fn end(&mut self) -> END_W<'_>

Bit 0 - Write '1' to enable interrupt for event END

pub fn resolved(&mut self) -> RESOLVED_W<'_>

Bit 1 - Write '1' to enable interrupt for event RESOLVED

pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>

Bit 2 - Write '1' to enable interrupt for event NOTRESOLVED

impl W<u32, Reg<u32, _INTENCLR>>

pub fn end(&mut self) -> END_W<'_>

Bit 0 - Write '1' to disable interrupt for event END

pub fn resolved(&mut self) -> RESOLVED_W<'_>

Bit 1 - Write '1' to disable interrupt for event RESOLVED

pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>

Bit 2 - Write '1' to disable interrupt for event NOTRESOLVED

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:1 - Enable or disable AAR

impl W<u32, Reg<u32, _NIRK>>

pub fn nirk(&mut self) -> NIRK_W<'_>

Bits 0:4 - Number of Identity root keys available in the IRK data structure

impl W<u32, Reg<u32, _IRKPTR>>

pub fn irkptr(&mut self) -> IRKPTR_W<'_>

Bits 0:31 - Pointer to the IRK data structure

impl W<u32, Reg<u32, _ADDRPTR>>

pub fn addrptr(&mut self) -> ADDRPTR_W<'_>

Bits 0:31 - Pointer to the resolvable address (6-bytes)

impl W<u32, Reg<u32, _SCRATCHPTR>>

pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>

Bits 0:31 - Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved.

impl W<u32, Reg<u32, _TASKS_KSGEN>>

pub fn tasks_ksgen(&mut self) -> TASKS_KSGEN_W<'_>

Bit 0 - Start generation of key-stream. This operation will stop by itself when completed.

impl W<u32, Reg<u32, _TASKS_CRYPT>>

pub fn tasks_crypt(&mut self) -> TASKS_CRYPT_W<'_>

Bit 0 - Start encryption/decryption. This operation will stop by itself when completed.

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop encryption/decryption

impl W<u32, Reg<u32, _TASKS_RATEOVERRIDE>>

pub fn tasks_rateoverride(&mut self) -> TASKS_RATEOVERRIDE_W<'_>

Bit 0 - Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption

impl W<u32, Reg<u32, _EVENTS_ENDKSGEN>>

pub fn events_endksgen(&mut self) -> EVENTS_ENDKSGEN_W<'_>

Bit 0 - Key-stream generation complete

impl W<u32, Reg<u32, _EVENTS_ENDCRYPT>>

pub fn events_endcrypt(&mut self) -> EVENTS_ENDCRYPT_W<'_>

Bit 0 - Encrypt/decrypt complete

impl W<u32, Reg<u32, _EVENTS_ERROR>>

pub fn events_error(&mut self) -> EVENTS_ERROR_W<'_>

Bit 0 - Deprecated field - CCM error event

impl W<u32, Reg<u32, _SHORTS>>

pub fn endksgen_crypt(&mut self) -> ENDKSGEN_CRYPT_W<'_>

Bit 0 - Shortcut between event ENDKSGEN and task CRYPT

impl W<u32, Reg<u32, _INTENSET>>

pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>

Bit 0 - Write '1' to enable interrupt for event ENDKSGEN

pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>

Bit 1 - Write '1' to enable interrupt for event ENDCRYPT

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Deprecated intsetfield - Write '1' to enable interrupt for event ERROR

impl W<u32, Reg<u32, _INTENCLR>>

pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>

Bit 0 - Write '1' to disable interrupt for event ENDKSGEN

pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>

Bit 1 - Write '1' to disable interrupt for event ENDCRYPT

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Deprecated intclrfield - Write '1' to disable interrupt for event ERROR

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:1 - Enable or disable CCM

impl W<u32, Reg<u32, _MODE>>

pub fn mode(&mut self) -> MODE_W<'_>

Bit 0 - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.

pub fn datarate(&mut self) -> DATARATE_W<'_>

Bits 16:17 - Radio data rate that the CCM shall run synchronous with

pub fn length(&mut self) -> LENGTH_W<'_>

Bit 24 - Packet length configuration

impl W<u32, Reg<u32, _CNFPTR>>

pub fn cnfptr(&mut self) -> CNFPTR_W<'_>

Bits 0:31 - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)

impl W<u32, Reg<u32, _INPTR>>

pub fn inptr(&mut self) -> INPTR_W<'_>

Bits 0:31 - Input pointer

impl W<u32, Reg<u32, _OUTPTR>>

pub fn outptr(&mut self) -> OUTPTR_W<'_>

Bits 0:31 - Output pointer

impl W<u32, Reg<u32, _SCRATCHPTR>>

pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>

Bits 0:31 - Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.

impl W<u32, Reg<u32, _MAXPACKETSIZE>>

pub fn maxpacketsize(&mut self) -> MAXPACKETSIZE_W<'_>

Bits 0:7 - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.

impl W<u32, Reg<u32, _RATEOVERRIDE>>

pub fn rateoverride(&mut self) -> RATEOVERRIDE_W<'_>

Bits 0:1 - Data rate override setting.

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Start the watchdog

impl W<u32, Reg<u32, _EVENTS_TIMEOUT>>

pub fn events_timeout(&mut self) -> EVENTS_TIMEOUT_W<'_>

Bit 0 - Watchdog timeout

impl W<u32, Reg<u32, _INTENSET>>

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 0 - Write '1' to enable interrupt for event TIMEOUT

impl W<u32, Reg<u32, _INTENCLR>>

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bit 0 - Write '1' to disable interrupt for event TIMEOUT

impl W<u32, Reg<u32, _CRV>>

pub fn crv(&mut self) -> CRV_W<'_>

Bits 0:31 - Counter reload value in number of cycles of the 32.768 kHz clock

impl W<u32, Reg<u32, _RREN>>

pub fn rr0(&mut self) -> RR0_W<'_>

Bit 0 - Enable or disable RR[0] register

pub fn rr1(&mut self) -> RR1_W<'_>

Bit 1 - Enable or disable RR[1] register

pub fn rr2(&mut self) -> RR2_W<'_>

Bit 2 - Enable or disable RR[2] register

pub fn rr3(&mut self) -> RR3_W<'_>

Bit 3 - Enable or disable RR[3] register

pub fn rr4(&mut self) -> RR4_W<'_>

Bit 4 - Enable or disable RR[4] register

pub fn rr5(&mut self) -> RR5_W<'_>

Bit 5 - Enable or disable RR[5] register

pub fn rr6(&mut self) -> RR6_W<'_>

Bit 6 - Enable or disable RR[6] register

pub fn rr7(&mut self) -> RR7_W<'_>

Bit 7 - Enable or disable RR[7] register

impl W<u32, Reg<u32, _CONFIG>>

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 0 - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping

pub fn halt(&mut self) -> HALT_W<'_>

Bit 3 - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger

impl W<u32, Reg<u32, _RR>>

pub fn rr(&mut self) -> RR_W<'_>

Bits 0:31 - Reload request register

impl W<u32, Reg<u32, _LED>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _A>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _B>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Task starting the quadrature decoder

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Task stopping the quadrature decoder

impl W<u32, Reg<u32, _TASKS_READCLRACC>>

pub fn tasks_readclracc(&mut self) -> TASKS_READCLRACC_W<'_>

Bit 0 - Read and clear ACC and ACCDBL

impl W<u32, Reg<u32, _TASKS_RDCLRACC>>

pub fn tasks_rdclracc(&mut self) -> TASKS_RDCLRACC_W<'_>

Bit 0 - Read and clear ACC

impl W<u32, Reg<u32, _TASKS_RDCLRDBL>>

pub fn tasks_rdclrdbl(&mut self) -> TASKS_RDCLRDBL_W<'_>

Bit 0 - Read and clear ACCDBL

impl W<u32, Reg<u32, _EVENTS_SAMPLERDY>>

pub fn events_samplerdy(&mut self) -> EVENTS_SAMPLERDY_W<'_>

Bit 0 - Event being generated for every new sample value written to the SAMPLE register

impl W<u32, Reg<u32, _EVENTS_REPORTRDY>>

pub fn events_reportrdy(&mut self) -> EVENTS_REPORTRDY_W<'_>

Bit 0 - Non-null report ready

impl W<u32, Reg<u32, _EVENTS_ACCOF>>

pub fn events_accof(&mut self) -> EVENTS_ACCOF_W<'_>

Bit 0 - ACC or ACCDBL register overflow

impl W<u32, Reg<u32, _EVENTS_DBLRDY>>

pub fn events_dblrdy(&mut self) -> EVENTS_DBLRDY_W<'_>

Bit 0 - Double displacement(s) detected

impl W<u32, Reg<u32, _EVENTS_STOPPED>>

pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>

Bit 0 - QDEC has been stopped

impl W<u32, Reg<u32, _SHORTS>>

pub fn reportrdy_readclracc(&mut self) -> REPORTRDY_READCLRACC_W<'_>

Bit 0 - Shortcut between event REPORTRDY and task READCLRACC

pub fn samplerdy_stop(&mut self) -> SAMPLERDY_STOP_W<'_>

Bit 1 - Shortcut between event SAMPLERDY and task STOP

pub fn reportrdy_rdclracc(&mut self) -> REPORTRDY_RDCLRACC_W<'_>

Bit 2 - Shortcut between event REPORTRDY and task RDCLRACC

pub fn reportrdy_stop(&mut self) -> REPORTRDY_STOP_W<'_>

Bit 3 - Shortcut between event REPORTRDY and task STOP

pub fn dblrdy_rdclrdbl(&mut self) -> DBLRDY_RDCLRDBL_W<'_>

Bit 4 - Shortcut between event DBLRDY and task RDCLRDBL

pub fn dblrdy_stop(&mut self) -> DBLRDY_STOP_W<'_>

Bit 5 - Shortcut between event DBLRDY and task STOP

pub fn samplerdy_readclracc(&mut self) -> SAMPLERDY_READCLRACC_W<'_>

Bit 6 - Shortcut between event SAMPLERDY and task READCLRACC

impl W<u32, Reg<u32, _INTENSET>>

pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>

Bit 0 - Write '1' to enable interrupt for event SAMPLERDY

pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>

Bit 1 - Write '1' to enable interrupt for event REPORTRDY

pub fn accof(&mut self) -> ACCOF_W<'_>

Bit 2 - Write '1' to enable interrupt for event ACCOF

pub fn dblrdy(&mut self) -> DBLRDY_W<'_>

Bit 3 - Write '1' to enable interrupt for event DBLRDY

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 4 - Write '1' to enable interrupt for event STOPPED

impl W<u32, Reg<u32, _INTENCLR>>

pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>

Bit 0 - Write '1' to disable interrupt for event SAMPLERDY

pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>

Bit 1 - Write '1' to disable interrupt for event REPORTRDY

pub fn accof(&mut self) -> ACCOF_W<'_>

Bit 2 - Write '1' to disable interrupt for event ACCOF

pub fn dblrdy(&mut self) -> DBLRDY_W<'_>

Bit 3 - Write '1' to disable interrupt for event DBLRDY

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 4 - Write '1' to disable interrupt for event STOPPED

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enable or disable the quadrature decoder

impl W<u32, Reg<u32, _LEDPOL>>

pub fn ledpol(&mut self) -> LEDPOL_W<'_>

Bit 0 - LED output pin polarity

impl W<u32, Reg<u32, _SAMPLEPER>>

pub fn sampleper(&mut self) -> SAMPLEPER_W<'_>

Bits 0:3 - Sample period. The SAMPLE register will be updated for every new sample

impl W<u32, Reg<u32, _REPORTPER>>

pub fn reportper(&mut self) -> REPORTPER_W<'_>

Bits 0:3 - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated

impl W<u32, Reg<u32, _DBFEN>>

pub fn dbfen(&mut self) -> DBFEN_W<'_>

Bit 0 - Enable input debounce filters

impl W<u32, Reg<u32, _LEDPRE>>

pub fn ledpre(&mut self) -> LEDPRE_W<'_>

Bits 0:8 - Period in us the LED is switched on prior to sampling

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Start comparator

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stop comparator

impl W<u32, Reg<u32, _TASKS_SAMPLE>>

pub fn tasks_sample(&mut self) -> TASKS_SAMPLE_W<'_>

Bit 0 - Sample comparator value

impl W<u32, Reg<u32, _EVENTS_READY>>

pub fn events_ready(&mut self) -> EVENTS_READY_W<'_>

Bit 0 - COMP is ready and output is valid

impl W<u32, Reg<u32, _EVENTS_DOWN>>

pub fn events_down(&mut self) -> EVENTS_DOWN_W<'_>

Bit 0 - Downward crossing

impl W<u32, Reg<u32, _EVENTS_UP>>

pub fn events_up(&mut self) -> EVENTS_UP_W<'_>

Bit 0 - Upward crossing

impl W<u32, Reg<u32, _EVENTS_CROSS>>

pub fn events_cross(&mut self) -> EVENTS_CROSS_W<'_>

Bit 0 - Downward or upward crossing

impl W<u32, Reg<u32, _SHORTS>>

pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>

Bit 0 - Shortcut between event READY and task SAMPLE

pub fn ready_stop(&mut self) -> READY_STOP_W<'_>

Bit 1 - Shortcut between event READY and task STOP

pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>

Bit 2 - Shortcut between event DOWN and task STOP

pub fn up_stop(&mut self) -> UP_STOP_W<'_>

Bit 3 - Shortcut between event UP and task STOP

pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>

Bit 4 - Shortcut between event CROSS and task STOP

impl W<u32, Reg<u32, _INTEN>>

pub fn ready(&mut self) -> READY_W<'_>

Bit 0 - Enable or disable interrupt for event READY

pub fn down(&mut self) -> DOWN_W<'_>

Bit 1 - Enable or disable interrupt for event DOWN

pub fn up(&mut self) -> UP_W<'_>

Bit 2 - Enable or disable interrupt for event UP

pub fn cross(&mut self) -> CROSS_W<'_>

Bit 3 - Enable or disable interrupt for event CROSS

impl W<u32, Reg<u32, _INTENSET>>

pub fn ready(&mut self) -> READY_W<'_>

Bit 0 - Write '1' to enable interrupt for event READY

pub fn down(&mut self) -> DOWN_W<'_>

Bit 1 - Write '1' to enable interrupt for event DOWN

pub fn up(&mut self) -> UP_W<'_>

Bit 2 - Write '1' to enable interrupt for event UP

pub fn cross(&mut self) -> CROSS_W<'_>

Bit 3 - Write '1' to enable interrupt for event CROSS

impl W<u32, Reg<u32, _INTENCLR>>

pub fn ready(&mut self) -> READY_W<'_>

Bit 0 - Write '1' to disable interrupt for event READY

pub fn down(&mut self) -> DOWN_W<'_>

Bit 1 - Write '1' to disable interrupt for event DOWN

pub fn up(&mut self) -> UP_W<'_>

Bit 2 - Write '1' to disable interrupt for event UP

pub fn cross(&mut self) -> CROSS_W<'_>

Bit 3 - Write '1' to disable interrupt for event CROSS

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bits 0:1 - Enable or disable COMP

impl W<u32, Reg<u32, _PSEL>>

pub fn psel(&mut self) -> PSEL_W<'_>

Bits 0:2 - Analog pin select

impl W<u32, Reg<u32, _REFSEL>>

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bits 0:2 - Reference select

impl W<u32, Reg<u32, _EXTREFSEL>>

pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>

Bits 0:2 - External analog reference select

impl W<u32, Reg<u32, _TH>>

pub fn thdown(&mut self) -> THDOWN_W<'_>

Bits 0:5 - VDOWN = (THDOWN+1)/64*VREF

pub fn thup(&mut self) -> THUP_W<'_>

Bits 8:13 - VUP = (THUP+1)/64*VREF

impl W<u32, Reg<u32, _MODE>>

pub fn sp(&mut self) -> SP_W<'_>

Bits 0:1 - Speed and power modes

pub fn main(&mut self) -> MAIN_W<'_>

Bit 8 - Main operation modes

impl W<u32, Reg<u32, _HYST>>

pub fn hyst(&mut self) -> HYST_W<'_>

Bit 0 - Comparator hysteresis

impl W<u32, Reg<u32, _TASKS_TRIGGER>>

pub fn tasks_trigger(&mut self) -> TASKS_TRIGGER_W<'_>

Bit 0 - Trigger n for triggering the corresponding TRIGGERED[n] event

impl W<u32, Reg<u32, _EVENTS_TRIGGERED>>

pub fn events_triggered(&mut self) -> EVENTS_TRIGGERED_W<'_>

Bit 0 - Event number n generated by triggering the corresponding TRIGGER[n] task

impl W<u32, Reg<u32, _INTEN>>

pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>

Bit 0 - Enable or disable interrupt for event TRIGGERED[0]

pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>

Bit 1 - Enable or disable interrupt for event TRIGGERED[1]

pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>

Bit 2 - Enable or disable interrupt for event TRIGGERED[2]

pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>

Bit 3 - Enable or disable interrupt for event TRIGGERED[3]

pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>

Bit 4 - Enable or disable interrupt for event TRIGGERED[4]

pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>

Bit 5 - Enable or disable interrupt for event TRIGGERED[5]

pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>

Bit 6 - Enable or disable interrupt for event TRIGGERED[6]

pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>

Bit 7 - Enable or disable interrupt for event TRIGGERED[7]

pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>

Bit 8 - Enable or disable interrupt for event TRIGGERED[8]

pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>

Bit 9 - Enable or disable interrupt for event TRIGGERED[9]

pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>

Bit 10 - Enable or disable interrupt for event TRIGGERED[10]

pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>

Bit 11 - Enable or disable interrupt for event TRIGGERED[11]

pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>

Bit 12 - Enable or disable interrupt for event TRIGGERED[12]

pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>

Bit 13 - Enable or disable interrupt for event TRIGGERED[13]

pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>

Bit 14 - Enable or disable interrupt for event TRIGGERED[14]

pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>

Bit 15 - Enable or disable interrupt for event TRIGGERED[15]

impl W<u32, Reg<u32, _INTENSET>>

pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>

Bit 0 - Write '1' to enable interrupt for event TRIGGERED[0]

pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>

Bit 1 - Write '1' to enable interrupt for event TRIGGERED[1]

pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>

Bit 2 - Write '1' to enable interrupt for event TRIGGERED[2]

pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>

Bit 3 - Write '1' to enable interrupt for event TRIGGERED[3]

pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>

Bit 4 - Write '1' to enable interrupt for event TRIGGERED[4]

pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>

Bit 5 - Write '1' to enable interrupt for event TRIGGERED[5]

pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>

Bit 6 - Write '1' to enable interrupt for event TRIGGERED[6]

pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>

Bit 7 - Write '1' to enable interrupt for event TRIGGERED[7]

pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>

Bit 8 - Write '1' to enable interrupt for event TRIGGERED[8]

pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>

Bit 9 - Write '1' to enable interrupt for event TRIGGERED[9]

pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>

Bit 10 - Write '1' to enable interrupt for event TRIGGERED[10]

pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>

Bit 11 - Write '1' to enable interrupt for event TRIGGERED[11]

pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>

Bit 12 - Write '1' to enable interrupt for event TRIGGERED[12]

pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>

Bit 13 - Write '1' to enable interrupt for event TRIGGERED[13]

pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>

Bit 14 - Write '1' to enable interrupt for event TRIGGERED[14]

pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>

Bit 15 - Write '1' to enable interrupt for event TRIGGERED[15]

impl W<u32, Reg<u32, _INTENCLR>>

pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>

Bit 0 - Write '1' to disable interrupt for event TRIGGERED[0]

pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>

Bit 1 - Write '1' to disable interrupt for event TRIGGERED[1]

pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>

Bit 2 - Write '1' to disable interrupt for event TRIGGERED[2]

pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>

Bit 3 - Write '1' to disable interrupt for event TRIGGERED[3]

pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>

Bit 4 - Write '1' to disable interrupt for event TRIGGERED[4]

pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>

Bit 5 - Write '1' to disable interrupt for event TRIGGERED[5]

pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>

Bit 6 - Write '1' to disable interrupt for event TRIGGERED[6]

pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>

Bit 7 - Write '1' to disable interrupt for event TRIGGERED[7]

pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>

Bit 8 - Write '1' to disable interrupt for event TRIGGERED[8]

pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>

Bit 9 - Write '1' to disable interrupt for event TRIGGERED[9]

pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>

Bit 10 - Write '1' to disable interrupt for event TRIGGERED[10]

pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>

Bit 11 - Write '1' to disable interrupt for event TRIGGERED[11]

pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>

Bit 12 - Write '1' to disable interrupt for event TRIGGERED[12]

pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>

Bit 13 - Write '1' to disable interrupt for event TRIGGERED[13]

pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>

Bit 14 - Write '1' to disable interrupt for event TRIGGERED[14]

pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>

Bit 15 - Write '1' to disable interrupt for event TRIGGERED[15]

impl W<u32, Reg<u32, _PTR>>

pub fn ptr(&mut self) -> PTR_W<'_>

Bits 0:31 - Beginning address in RAM of this sequence

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:14 - Number of values (duty cycles) in this sequence

impl W<u32, Reg<u32, _REFRESH>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:23 - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)

impl W<u32, Reg<u32, _ENDDELAY>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:23 - Time added after the sequence in PWM periods

impl W<u32, Reg<u32, _OUT>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback

impl W<u32, Reg<u32, _TASKS_SEQSTART>>

pub fn tasks_seqstart(&mut self) -> TASKS_SEQSTART_W<'_>

Bit 0 - Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.

impl W<u32, Reg<u32, _TASKS_NEXTSTEP>>

pub fn tasks_nextstep(&mut self) -> TASKS_NEXTSTEP_W<'_>

Bit 0 - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.

impl W<u32, Reg<u32, _EVENTS_STOPPED>>

pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>

Bit 0 - Response to STOP task, emitted when PWM pulses are no longer generated

impl W<u32, Reg<u32, _EVENTS_SEQSTARTED>>

pub fn events_seqstarted(&mut self) -> EVENTS_SEQSTARTED_W<'_>

Bit 0 - First PWM period started on sequence n

impl W<u32, Reg<u32, _EVENTS_SEQEND>>

pub fn events_seqend(&mut self) -> EVENTS_SEQEND_W<'_>

Bit 0 - Emitted at end of every sequence n, when last value from RAM has been applied to wave counter

impl W<u32, Reg<u32, _EVENTS_PWMPERIODEND>>

pub fn events_pwmperiodend(&mut self) -> EVENTS_PWMPERIODEND_W<'_>

Bit 0 - Emitted at the end of each PWM period

impl W<u32, Reg<u32, _EVENTS_LOOPSDONE>>

pub fn events_loopsdone(&mut self) -> EVENTS_LOOPSDONE_W<'_>

Bit 0 - Concatenated sequences have been played the amount of times defined in LOOP.CNT

impl W<u32, Reg<u32, _SHORTS>>

pub fn seqend0_stop(&mut self) -> SEQEND0_STOP_W<'_>

Bit 0 - Shortcut between event SEQEND[0] and task STOP

pub fn seqend1_stop(&mut self) -> SEQEND1_STOP_W<'_>

Bit 1 - Shortcut between event SEQEND[1] and task STOP

pub fn loopsdone_seqstart0(&mut self) -> LOOPSDONE_SEQSTART0_W<'_>

Bit 2 - Shortcut between event LOOPSDONE and task SEQSTART[0]

pub fn loopsdone_seqstart1(&mut self) -> LOOPSDONE_SEQSTART1_W<'_>

Bit 3 - Shortcut between event LOOPSDONE and task SEQSTART[1]

pub fn loopsdone_stop(&mut self) -> LOOPSDONE_STOP_W<'_>

Bit 4 - Shortcut between event LOOPSDONE and task STOP

impl W<u32, Reg<u32, _INTEN>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Enable or disable interrupt for event STOPPED

pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>

Bit 2 - Enable or disable interrupt for event SEQSTARTED[0]

pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>

Bit 3 - Enable or disable interrupt for event SEQSTARTED[1]

pub fn seqend0(&mut self) -> SEQEND0_W<'_>

Bit 4 - Enable or disable interrupt for event SEQEND[0]

pub fn seqend1(&mut self) -> SEQEND1_W<'_>

Bit 5 - Enable or disable interrupt for event SEQEND[1]

pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>

Bit 6 - Enable or disable interrupt for event PWMPERIODEND

pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>

Bit 7 - Enable or disable interrupt for event LOOPSDONE

impl W<u32, Reg<u32, _INTENSET>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to enable interrupt for event STOPPED

pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>

Bit 2 - Write '1' to enable interrupt for event SEQSTARTED[0]

pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>

Bit 3 - Write '1' to enable interrupt for event SEQSTARTED[1]

pub fn seqend0(&mut self) -> SEQEND0_W<'_>

Bit 4 - Write '1' to enable interrupt for event SEQEND[0]

pub fn seqend1(&mut self) -> SEQEND1_W<'_>

Bit 5 - Write '1' to enable interrupt for event SEQEND[1]

pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>

Bit 6 - Write '1' to enable interrupt for event PWMPERIODEND

pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>

Bit 7 - Write '1' to enable interrupt for event LOOPSDONE

impl W<u32, Reg<u32, _INTENCLR>>

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to disable interrupt for event STOPPED

pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>

Bit 2 - Write '1' to disable interrupt for event SEQSTARTED[0]

pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>

Bit 3 - Write '1' to disable interrupt for event SEQSTARTED[1]

pub fn seqend0(&mut self) -> SEQEND0_W<'_>

Bit 4 - Write '1' to disable interrupt for event SEQEND[0]

pub fn seqend1(&mut self) -> SEQEND1_W<'_>

Bit 5 - Write '1' to disable interrupt for event SEQEND[1]

pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>

Bit 6 - Write '1' to disable interrupt for event PWMPERIODEND

pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>

Bit 7 - Write '1' to disable interrupt for event LOOPSDONE

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enable or disable PWM module

impl W<u32, Reg<u32, _MODE>>

pub fn updown(&mut self) -> UPDOWN_W<'_>

Bit 0 - Selects up mode or up-and-down mode for the counter

impl W<u32, Reg<u32, _COUNTERTOP>>

pub fn countertop(&mut self) -> COUNTERTOP_W<'_>

Bits 0:14 - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used.

impl W<u32, Reg<u32, _PRESCALER>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 0:2 - Prescaler of PWM_CLK

impl W<u32, Reg<u32, _DECODER>>

pub fn load(&mut self) -> LOAD_W<'_>

Bits 0:1 - How a sequence is read from RAM and spread to the compare register

pub fn mode(&mut self) -> MODE_W<'_>

Bit 8 - Selects source for advancing the active sequence

impl W<u32, Reg<u32, _LOOP>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Number of playbacks of pattern cycles

impl W<u32, Reg<u32, _CLK>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _DIN>>

pub fn pin(&mut self) -> PIN_W<'_>

Bits 0:4 - Pin number

pub fn connect(&mut self) -> CONNECT_W<'_>

Bit 31 - Connection

impl W<u32, Reg<u32, _PTR>>

pub fn sampleptr(&mut self) -> SAMPLEPTR_W<'_>

Bits 0:31 - Address to write PDM samples to over DMA

impl W<u32, Reg<u32, _MAXCNT>>

pub fn buffsize(&mut self) -> BUFFSIZE_W<'_>

Bits 0:14 - Length of DMA RAM allocation in number of samples

impl W<u32, Reg<u32, _TASKS_START>>

pub fn tasks_start(&mut self) -> TASKS_START_W<'_>

Bit 0 - Starts continuous PDM transfer

impl W<u32, Reg<u32, _TASKS_STOP>>

pub fn tasks_stop(&mut self) -> TASKS_STOP_W<'_>

Bit 0 - Stops PDM transfer

impl W<u32, Reg<u32, _EVENTS_STARTED>>

pub fn events_started(&mut self) -> EVENTS_STARTED_W<'_>

Bit 0 - PDM transfer has started

impl W<u32, Reg<u32, _EVENTS_STOPPED>>

pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<'_>

Bit 0 - PDM transfer has finished

impl W<u32, Reg<u32, _EVENTS_END>>

pub fn events_end(&mut self) -> EVENTS_END_W<'_>

Bit 0 - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM

impl W<u32, Reg<u32, _INTEN>>

pub fn started(&mut self) -> STARTED_W<'_>

Bit 0 - Enable or disable interrupt for event STARTED

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Enable or disable interrupt for event STOPPED

pub fn end(&mut self) -> END_W<'_>

Bit 2 - Enable or disable interrupt for event END

impl W<u32, Reg<u32, _INTENSET>>

pub fn started(&mut self) -> STARTED_W<'_>

Bit 0 - Write '1' to enable interrupt for event STARTED

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to enable interrupt for event STOPPED

pub fn end(&mut self) -> END_W<'_>

Bit 2 - Write '1' to enable interrupt for event END

impl W<u32, Reg<u32, _INTENCLR>>

pub fn started(&mut self) -> STARTED_W<'_>

Bit 0 - Write '1' to disable interrupt for event STARTED

pub fn stopped(&mut self) -> STOPPED_W<'_>

Bit 1 - Write '1' to disable interrupt for event STOPPED

pub fn end(&mut self) -> END_W<'_>

Bit 2 - Write '1' to disable interrupt for event END

impl W<u32, Reg<u32, _ENABLE>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enable or disable PDM module

impl W<u32, Reg<u32, _PDMCLKCTRL>>

pub fn freq(&mut self) -> FREQ_W<'_>

Bits 0:31 - PDM_CLK frequency

impl W<u32, Reg<u32, _MODE>>

pub fn operation(&mut self) -> OPERATION_W<'_>

Bit 0 - Mono or stereo operation

pub fn edge(&mut self) -> EDGE_W<'_>

Bit 1 - Defines on which PDM_CLK edge Left (or mono) is sampled

impl W<u32, Reg<u32, _GAINL>>

pub fn gainl(&mut self) -> GAINL_W<'_>

Bits 0:6 - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust

impl W<u32, Reg<u32, _GAINR>>

pub fn gainr(&mut self) -> GAINR_W<'_>

Bits 0:7 - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)

impl W<u32, Reg<u32, _CONFIG>>

pub fn wen(&mut self) -> WEN_W<'_>

Bits 0:1 - Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used.

impl W<u32, Reg<u32, _ERASEPAGE>>

pub fn erasepage(&mut self) -> ERASEPAGE_W<'_>

Bits 0:31 - Register for starting erase of a page in code area.

impl W<u32, Reg<u32, _ERASEPCR1>>

pub fn erasepcr1(&mut self) -> ERASEPCR1_W<'_>

Bits 0:31 - Register for erasing a page in code area. Equivalent to ERASEPAGE.

impl W<u32, Reg<u32, _ERASEALL>>

pub fn eraseall(&mut self) -> ERASEALL_W<'_>

Bit 0 - Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.

impl W<u32, Reg<u32, _ERASEPCR0>>

pub fn erasepcr0(&mut self) -> ERASEPCR0_W<'_>

Bits 0:31 - Register for starting erase of a page in code area. Equivalent to ERASEPAGE.

impl W<u32, Reg<u32, _ERASEUICR>>

pub fn eraseuicr(&mut self) -> ERASEUICR_W<'_>

Bit 0 - Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.

impl W<u32, Reg<u32, _ERASEPAGEPARTIAL>>

pub fn erasepagepartial(&mut self) -> ERASEPAGEPARTIAL_W<'_>

Bits 0:31 - Register for starting partial erase of a page in code area

impl W<u32, Reg<u32, _ERASEPAGEPARTIALCFG>>

pub fn duration(&mut self) -> DURATION_W<'_>

Bits 0:6 - Duration of the partial erase in milliseconds

impl W<u32, Reg<u32, _EN>>

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable channel group n

impl W<u32, Reg<u32, _DIS>>

pub fn dis(&mut self) -> DIS_W<'_>

Bit 0 - Disable channel group n

impl W<u32, Reg<u32, _EEP>>

pub fn eep(&mut self) -> EEP_W<'_>

Bits 0:31 - Pointer to event register. Accepts only addresses to registers from the Event group.

impl W<u32, Reg<u32, _TEP>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:31 - Pointer to task register. Accepts only addresses to registers from the Task group.

impl W<u32, Reg<u32, _TEP>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:31 - Pointer to task register

impl W<u32, Reg<u32, _CHEN>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Enable or disable channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Enable or disable channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Enable or disable channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Enable or disable channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Enable or disable channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Enable or disable channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Enable or disable channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Enable or disable channel 7

pub fn ch8(&mut self) -> CH8_W<'_>

Bit 8 - Enable or disable channel 8

pub fn ch9(&mut self) -> CH9_W<'_>

Bit 9 - Enable or disable channel 9

pub fn ch10(&mut self) -> CH10_W<'_>

Bit 10 - Enable or disable channel 10

pub fn ch11(&mut self) -> CH11_W<'_>

Bit 11 - Enable or disable channel 11

pub fn ch12(&mut self) -> CH12_W<'_>

Bit 12 - Enable or disable channel 12

pub fn ch13(&mut self) -> CH13_W<'_>

Bit 13 - Enable or disable channel 13

pub fn ch14(&mut self) -> CH14_W<'_>

Bit 14 - Enable or disable channel 14

pub fn ch15(&mut self) -> CH15_W<'_>

Bit 15 - Enable or disable channel 15

pub fn ch16(&mut self) -> CH16_W<'_>

Bit 16 - Enable or disable channel 16

pub fn ch17(&mut self) -> CH17_W<'_>

Bit 17 - Enable or disable channel 17

pub fn ch18(&mut self) -> CH18_W<'_>

Bit 18 - Enable or disable channel 18

pub fn ch19(&mut self) -> CH19_W<'_>

Bit 19 - Enable or disable channel 19

pub fn ch20(&mut self) -> CH20_W<'_>

Bit 20 - Enable or disable channel 20

pub fn ch21(&mut self) -> CH21_W<'_>

Bit 21 - Enable or disable channel 21

pub fn ch22(&mut self) -> CH22_W<'_>

Bit 22 - Enable or disable channel 22

pub fn ch23(&mut self) -> CH23_W<'_>

Bit 23 - Enable or disable channel 23

pub fn ch24(&mut self) -> CH24_W<'_>

Bit 24 - Enable or disable channel 24

pub fn ch25(&mut self) -> CH25_W<'_>

Bit 25 - Enable or disable channel 25

pub fn ch26(&mut self) -> CH26_W<'_>

Bit 26 - Enable or disable channel 26

pub fn ch27(&mut self) -> CH27_W<'_>

Bit 27 - Enable or disable channel 27

pub fn ch28(&mut self) -> CH28_W<'_>

Bit 28 - Enable or disable channel 28

pub fn ch29(&mut self) -> CH29_W<'_>

Bit 29 - Enable or disable channel 29

pub fn ch30(&mut self) -> CH30_W<'_>

Bit 30 - Enable or disable channel 30

pub fn ch31(&mut self) -> CH31_W<'_>

Bit 31 - Enable or disable channel 31

impl W<u32, Reg<u32, _CHENSET>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Channel 0 enable set register. Writing '0' has no effect

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Channel 1 enable set register. Writing '0' has no effect

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Channel 2 enable set register. Writing '0' has no effect

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Channel 3 enable set register. Writing '0' has no effect

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Channel 4 enable set register. Writing '0' has no effect

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Channel 5 enable set register. Writing '0' has no effect

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Channel 6 enable set register. Writing '0' has no effect

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Channel 7 enable set register. Writing '0' has no effect

pub fn ch8(&mut self) -> CH8_W<'_>

Bit 8 - Channel 8 enable set register. Writing '0' has no effect

pub fn ch9(&mut self) -> CH9_W<'_>

Bit 9 - Channel 9 enable set register. Writing '0' has no effect

pub fn ch10(&mut self) -> CH10_W<'_>

Bit 10 - Channel 10 enable set register. Writing '0' has no effect

pub fn ch11(&mut self) -> CH11_W<'_>

Bit 11 - Channel 11 enable set register. Writing '0' has no effect

pub fn ch12(&mut self) -> CH12_W<'_>

Bit 12 - Channel 12 enable set register. Writing '0' has no effect

pub fn ch13(&mut self) -> CH13_W<'_>

Bit 13 - Channel 13 enable set register. Writing '0' has no effect

pub fn ch14(&mut self) -> CH14_W<'_>

Bit 14 - Channel 14 enable set register. Writing '0' has no effect

pub fn ch15(&mut self) -> CH15_W<'_>

Bit 15 - Channel 15 enable set register. Writing '0' has no effect

pub fn ch16(&mut self) -> CH16_W<'_>

Bit 16 - Channel 16 enable set register. Writing '0' has no effect

pub fn ch17(&mut self) -> CH17_W<'_>

Bit 17 - Channel 17 enable set register. Writing '0' has no effect

pub fn ch18(&mut self) -> CH18_W<'_>

Bit 18 - Channel 18 enable set register. Writing '0' has no effect

pub fn ch19(&mut self) -> CH19_W<'_>

Bit 19 - Channel 19 enable set register. Writing '0' has no effect

pub fn ch20(&mut self) -> CH20_W<'_>

Bit 20 - Channel 20 enable set register. Writing '0' has no effect

pub fn ch21(&mut self) -> CH21_W<'_>

Bit 21 - Channel 21 enable set register. Writing '0' has no effect

pub fn ch22(&mut self) -> CH22_W<'_>

Bit 22 - Channel 22 enable set register. Writing '0' has no effect

pub fn ch23(&mut self) -> CH23_W<'_>

Bit 23 - Channel 23 enable set register. Writing '0' has no effect

pub fn ch24(&mut self) -> CH24_W<'_>

Bit 24 - Channel 24 enable set register. Writing '0' has no effect

pub fn ch25(&mut self) -> CH25_W<'_>

Bit 25 - Channel 25 enable set register. Writing '0' has no effect

pub fn ch26(&mut self) -> CH26_W<'_>

Bit 26 - Channel 26 enable set register. Writing '0' has no effect

pub fn ch27(&mut self) -> CH27_W<'_>

Bit 27 - Channel 27 enable set register. Writing '0' has no effect

pub fn ch28(&mut self) -> CH28_W<'_>

Bit 28 - Channel 28 enable set register. Writing '0' has no effect

pub fn ch29(&mut self) -> CH29_W<'_>

Bit 29 - Channel 29 enable set register. Writing '0' has no effect

pub fn ch30(&mut self) -> CH30_W<'_>

Bit 30 - Channel 30 enable set register. Writing '0' has no effect

pub fn ch31(&mut self) -> CH31_W<'_>

Bit 31 - Channel 31 enable set register. Writing '0' has no effect

impl W<u32, Reg<u32, _CHENCLR>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Channel 0 enable clear register. Writing '0' has no effect

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Channel 1 enable clear register. Writing '0' has no effect

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Channel 2 enable clear register. Writing '0' has no effect

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Channel 3 enable clear register. Writing '0' has no effect

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Channel 4 enable clear register. Writing '0' has no effect

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Channel 5 enable clear register. Writing '0' has no effect

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Channel 6 enable clear register. Writing '0' has no effect

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Channel 7 enable clear register. Writing '0' has no effect

pub fn ch8(&mut self) -> CH8_W<'_>

Bit 8 - Channel 8 enable clear register. Writing '0' has no effect

pub fn ch9(&mut self) -> CH9_W<'_>

Bit 9 - Channel 9 enable clear register. Writing '0' has no effect

pub fn ch10(&mut self) -> CH10_W<'_>

Bit 10 - Channel 10 enable clear register. Writing '0' has no effect

pub fn ch11(&mut self) -> CH11_W<'_>

Bit 11 - Channel 11 enable clear register. Writing '0' has no effect

pub fn ch12(&mut self) -> CH12_W<'_>

Bit 12 - Channel 12 enable clear register. Writing '0' has no effect

pub fn ch13(&mut self) -> CH13_W<'_>

Bit 13 - Channel 13 enable clear register. Writing '0' has no effect

pub fn ch14(&mut self) -> CH14_W<'_>

Bit 14 - Channel 14 enable clear register. Writing '0' has no effect

pub fn ch15(&mut self) -> CH15_W<'_>

Bit 15 - Channel 15 enable clear register. Writing '0' has no effect

pub fn ch16(&mut self) -> CH16_W<'_>

Bit 16 - Channel 16 enable clear register. Writing '0' has no effect

pub fn ch17(&mut self) -> CH17_W<'_>

Bit 17 - Channel 17 enable clear register. Writing '0' has no effect

pub fn ch18(&mut self) -> CH18_W<'_>

Bit 18 - Channel 18 enable clear register. Writing '0' has no effect

pub fn ch19(&mut self) -> CH19_W<'_>

Bit 19 - Channel 19 enable clear register. Writing '0' has no effect

pub fn ch20(&mut self) -> CH20_W<'_>

Bit 20 - Channel 20 enable clear register. Writing '0' has no effect

pub fn ch21(&mut self) -> CH21_W<'_>

Bit 21 - Channel 21 enable clear register. Writing '0' has no effect

pub fn ch22(&mut self) -> CH22_W<'_>

Bit 22 - Channel 22 enable clear register. Writing '0' has no effect

pub fn ch23(&mut self) -> CH23_W<'_>

Bit 23 - Channel 23 enable clear register. Writing '0' has no effect

pub fn ch24(&mut self) -> CH24_W<'_>

Bit 24 - Channel 24 enable clear register. Writing '0' has no effect

pub fn ch25(&mut self) -> CH25_W<'_>

Bit 25 - Channel 25 enable clear register. Writing '0' has no effect

pub fn ch26(&mut self) -> CH26_W<'_>

Bit 26 - Channel 26 enable clear register. Writing '0' has no effect

pub fn ch27(&mut self) -> CH27_W<'_>

Bit 27 - Channel 27 enable clear register. Writing '0' has no effect

pub fn ch28(&mut self) -> CH28_W<'_>

Bit 28 - Channel 28 enable clear register. Writing '0' has no effect

pub fn ch29(&mut self) -> CH29_W<'_>

Bit 29 - Channel 29 enable clear register. Writing '0' has no effect

pub fn ch30(&mut self) -> CH30_W<'_>

Bit 30 - Channel 30 enable clear register. Writing '0' has no effect

pub fn ch31(&mut self) -> CH31_W<'_>

Bit 31 - Channel 31 enable clear register. Writing '0' has no effect

impl W<u32, Reg<u32, _CHG>>

pub fn ch0(&mut self) -> CH0_W<'_>

Bit 0 - Include or exclude channel 0

pub fn ch1(&mut self) -> CH1_W<'_>

Bit 1 - Include or exclude channel 1

pub fn ch2(&mut self) -> CH2_W<'_>

Bit 2 - Include or exclude channel 2

pub fn ch3(&mut self) -> CH3_W<'_>

Bit 3 - Include or exclude channel 3

pub fn ch4(&mut self) -> CH4_W<'_>

Bit 4 - Include or exclude channel 4

pub fn ch5(&mut self) -> CH5_W<'_>

Bit 5 - Include or exclude channel 5

pub fn ch6(&mut self) -> CH6_W<'_>

Bit 6 - Include or exclude channel 6

pub fn ch7(&mut self) -> CH7_W<'_>

Bit 7 - Include or exclude channel 7

pub fn ch8(&mut self) -> CH8_W<'_>

Bit 8 - Include or exclude channel 8

pub fn ch9(&mut self) -> CH9_W<'_>

Bit 9 - Include or exclude channel 9

pub fn ch10(&mut self) -> CH10_W<'_>

Bit 10 - Include or exclude channel 10

pub fn ch11(&mut self) -> CH11_W<'_>

Bit 11 - Include or exclude channel 11

pub fn ch12(&mut self) -> CH12_W<'_>

Bit 12 - Include or exclude channel 12

pub fn ch13(&mut self) -> CH13_W<'_>

Bit 13 - Include or exclude channel 13

pub fn ch14(&mut self) -> CH14_W<'_>

Bit 14 - Include or exclude channel 14

pub fn ch15(&mut self) -> CH15_W<'_>

Bit 15 - Include or exclude channel 15

pub fn ch16(&mut self) -> CH16_W<'_>

Bit 16 - Include or exclude channel 16

pub fn ch17(&mut self) -> CH17_W<'_>

Bit 17 - Include or exclude channel 17

pub fn ch18(&mut self) -> CH18_W<'_>

Bit 18 - Include or exclude channel 18

pub fn ch19(&mut self) -> CH19_W<'_>

Bit 19 - Include or exclude channel 19

pub fn ch20(&mut self) -> CH20_W<'_>

Bit 20 - Include or exclude channel 20

pub fn ch21(&mut self) -> CH21_W<'_>

Bit 21 - Include or exclude channel 21

pub fn ch22(&mut self) -> CH22_W<'_>

Bit 22 - Include or exclude channel 22

pub fn ch23(&mut self) -> CH23_W<'_>

Bit 23 - Include or exclude channel 23

pub fn ch24(&mut self) -> CH24_W<'_>

Bit 24 - Include or exclude channel 24

pub fn ch25(&mut self) -> CH25_W<'_>

Bit 25 - Include or exclude channel 25

pub fn ch26(&mut self) -> CH26_W<'_>

Bit 26 - Include or exclude channel 26

pub fn ch27(&mut self) -> CH27_W<'_>

Bit 27 - Include or exclude channel 27

pub fn ch28(&mut self) -> CH28_W<'_>

Bit 28 - Include or exclude channel 28

pub fn ch29(&mut self) -> CH29_W<'_>

Bit 29 - Include or exclude channel 29

pub fn ch30(&mut self) -> CH30_W<'_>

Bit 30 - Include or exclude channel 30

pub fn ch31(&mut self) -> CH31_W<'_>

Bit 31 - Include or exclude channel 31