nrf52811_pac/pwm0/
tasks_seqstart.rs

1#[doc = "Register `TASKS_SEQSTART[%s]` writer"]
2pub struct W(crate::W<TASKS_SEQSTART_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<TASKS_SEQSTART_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<TASKS_SEQSTART_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<TASKS_SEQSTART_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq)]
24pub enum TASKS_SEQSTART_AW {
25    #[doc = "1: Trigger task"]
26    TRIGGER = 1,
27}
28impl From<TASKS_SEQSTART_AW> for bool {
29    #[inline(always)]
30    fn from(variant: TASKS_SEQSTART_AW) -> Self {
31        variant as u8 != 0
32    }
33}
34#[doc = "Field `TASKS_SEQSTART` writer - Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running."]
35pub type TASKS_SEQSTART_W<'a, const O: u8> =
36    crate::BitWriter<'a, u32, TASKS_SEQSTART_SPEC, TASKS_SEQSTART_AW, O>;
37impl<'a, const O: u8> TASKS_SEQSTART_W<'a, O> {
38    #[doc = "Trigger task"]
39    #[inline(always)]
40    pub fn trigger(self) -> &'a mut W {
41        self.variant(TASKS_SEQSTART_AW::TRIGGER)
42    }
43}
44impl W {
45    #[doc = "Bit 0 - Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running."]
46    #[inline(always)]
47    pub fn tasks_seqstart(&mut self) -> TASKS_SEQSTART_W<0> {
48        TASKS_SEQSTART_W::new(self)
49    }
50    #[doc = "Writes raw bits to the register."]
51    #[inline(always)]
52    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
53        self.0.bits(bits);
54        self
55    }
56}
57#[doc = "Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ\\[n\\]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_seqstart](index.html) module"]
58pub struct TASKS_SEQSTART_SPEC;
59impl crate::RegisterSpec for TASKS_SEQSTART_SPEC {
60    type Ux = u32;
61}
62#[doc = "`write(|w| ..)` method takes [tasks_seqstart::W](W) writer structure"]
63impl crate::Writable for TASKS_SEQSTART_SPEC {
64    type Writer = W;
65}
66#[doc = "`reset()` method sets TASKS_SEQSTART[%s]
67to value 0"]
68impl crate::Resettable for TASKS_SEQSTART_SPEC {
69    #[inline(always)]
70    fn reset_value() -> Self::Ux {
71        0
72    }
73}
nrf52811_pac/pwm0/tasks_seqstart.rs

nrf52811_pac/pwm0/
tasks_seqstart.rs
