[−][src]Struct nrf51::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

Writes raw bits to the register

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn pofwarn(&mut self) -> POFWARN_W`[src]

Bit 2 - Enable interrupt on POFWARN event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn pofwarn(&mut self) -> POFWARN_W`[src]

Bit 2 - Disable interrupt on POFWARN event.

`impl W<u32, Reg<u32, _RESETREAS>>`[src]

`pub fn resetpin(&mut self) -> RESETPIN_W`[src]

Bit 0 - Reset from pin-reset detected.

`pub fn dog(&mut self) -> DOG_W`[src]

Bit 1 - Reset from watchdog detected.

`pub fn sreq(&mut self) -> SREQ_W`[src]

Bit 2 - Reset from AIRCR.SYSRESETREQ detected.

`pub fn lockup(&mut self) -> LOCKUP_W`[src]

Bit 3 - Reset from CPU lock-up detected.

`pub fn off(&mut self) -> OFF_W`[src]

Bit 16 - Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO.

`pub fn lpcomp(&mut self) -> LPCOMP_W`[src]

Bit 17 - Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP.

`pub fn dif(&mut self) -> DIF_W`[src]

Bit 18 - Reset from wake-up from OFF mode detected by entering into debug interface mode.

`impl W<u32, Reg<u32, _SYSTEMOFF>>`[src]

`pub fn systemoff(&mut self) -> SYSTEMOFF_W`[src]

Bit 0 - Enter system off mode.

`impl W<u32, Reg<u32, _POFCON>>`[src]

`pub fn pof(&mut self) -> POF_W`[src]

Bit 0 - Power failure comparator enable.

`pub fn threshold(&mut self) -> THRESHOLD_W`[src]

Bits 1:2 - Set threshold level.

`impl W<u32, Reg<u32, _GPREGRET>>`[src]

`pub fn gpregret(&mut self) -> GPREGRET_W`[src]

Bits 0:7 - General purpose retention register.

`impl W<u32, Reg<u32, _RAMON>>`[src]

`pub fn onram0(&mut self) -> ONRAM0_W`[src]

Bit 0 - RAM block 0 behaviour in ON mode.

`pub fn onram1(&mut self) -> ONRAM1_W`[src]

Bit 1 - RAM block 1 behaviour in ON mode.

`pub fn offram0(&mut self) -> OFFRAM0_W`[src]

Bit 16 - RAM block 0 behaviour in OFF mode.

`pub fn offram1(&mut self) -> OFFRAM1_W`[src]

Bit 17 - RAM block 1 behaviour in OFF mode.

`impl W<u32, Reg<u32, _RESET>>`[src]

`pub fn reset(&mut self) -> RESET_W`[src]

Bit 0 - Enable or disable pin reset in debug interface mode.

`impl W<u32, Reg<u32, _RAMONB>>`[src]

`pub fn onram2(&mut self) -> ONRAM2_W`[src]

Bit 0 - RAM block 2 behaviour in ON mode.

`pub fn onram3(&mut self) -> ONRAM3_W`[src]

Bit 1 - RAM block 3 behaviour in ON mode.

`pub fn offram2(&mut self) -> OFFRAM2_W`[src]

Bit 16 - RAM block 2 behaviour in OFF mode.

`pub fn offram3(&mut self) -> OFFRAM3_W`[src]

Bit 17 - RAM block 3 behaviour in OFF mode.

`impl W<u32, Reg<u32, _DCDCEN>>`[src]

`pub fn dcdcen(&mut self) -> DCDCEN_W`[src]

Bit 0 - Enable DCDC converter.

`impl W<u32, Reg<u32, _DCDCFORCE>>`[src]

`pub fn forceoff(&mut self) -> FORCEOFF_W`[src]

Bit 0 - DCDC power-up force off.

`pub fn forceon(&mut self) -> FORCEON_W`[src]

Bit 1 - DCDC power-up force on.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W`[src]

Bit 0 - Enable interrupt on HFCLKSTARTED event.

`pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W`[src]

Bit 1 - Enable interrupt on LFCLKSTARTED event.

`pub fn done(&mut self) -> DONE_W`[src]

Bit 3 - Enable interrupt on DONE event.

`pub fn ctto(&mut self) -> CTTO_W`[src]

Bit 4 - Enable interrupt on CTTO event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W`[src]

Bit 0 - Disable interrupt on HFCLKSTARTED event.

`pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W`[src]

Bit 1 - Disable interrupt on LFCLKSTARTED event.

`pub fn done(&mut self) -> DONE_W`[src]

Bit 3 - Disable interrupt on DONE event.

`pub fn ctto(&mut self) -> CTTO_W`[src]

Bit 4 - Disable interrupt on CTTO event.

`impl W<u32, Reg<u32, _LFCLKSRC>>`[src]

`pub fn src(&mut self) -> SRC_W`[src]

Bits 0:1 - Clock source.

`impl W<u32, Reg<u32, _CTIV>>`[src]

`pub fn ctiv(&mut self) -> CTIV_W`[src]

Bits 0:6 - Calibration timer interval in 0.25s resolution.

`impl W<u32, Reg<u32, _XTALFREQ>>`[src]

`pub fn xtalfreq(&mut self) -> XTALFREQ_W`[src]

Bits 0:7 - External Xtal frequency selection.

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn ready_start(&mut self) -> READY_START_W`[src]

Bit 0 - Shortcut between READY event and START task.

`pub fn end_disable(&mut self) -> END_DISABLE_W`[src]

Bit 1 - Shortcut between END event and DISABLE task.

`pub fn disabled_txen(&mut self) -> DISABLED_TXEN_W`[src]

Bit 2 - Shortcut between DISABLED event and TXEN task.

`pub fn disabled_rxen(&mut self) -> DISABLED_RXEN_W`[src]

Bit 3 - Shortcut between DISABLED event and RXEN task.

`pub fn address_rssistart(&mut self) -> ADDRESS_RSSISTART_W`[src]

Bit 4 - Shortcut between ADDRESS event and RSSISTART task.

`pub fn end_start(&mut self) -> END_START_W`[src]

Bit 5 - Shortcut between END event and START task.

`pub fn address_bcstart(&mut self) -> ADDRESS_BCSTART_W`[src]

Bit 6 - Shortcut between ADDRESS event and BCSTART task.

`pub fn disabled_rssistop(&mut self) -> DISABLED_RSSISTOP_W`[src]

Bit 8 - Shortcut between DISABLED event and RSSISTOP task.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Enable interrupt on READY event.

`pub fn address(&mut self) -> ADDRESS_W`[src]

Bit 1 - Enable interrupt on ADDRESS event.

`pub fn payload(&mut self) -> PAYLOAD_W`[src]

Bit 2 - Enable interrupt on PAYLOAD event.

`pub fn end(&mut self) -> END_W`[src]

Bit 3 - Enable interrupt on END event.

`pub fn disabled(&mut self) -> DISABLED_W`[src]

Bit 4 - Enable interrupt on DISABLED event.

`pub fn devmatch(&mut self) -> DEVMATCH_W`[src]

Bit 5 - Enable interrupt on DEVMATCH event.

`pub fn devmiss(&mut self) -> DEVMISS_W`[src]

Bit 6 - Enable interrupt on DEVMISS event.

`pub fn rssiend(&mut self) -> RSSIEND_W`[src]

Bit 7 - Enable interrupt on RSSIEND event.

`pub fn bcmatch(&mut self) -> BCMATCH_W`[src]

Bit 10 - Enable interrupt on BCMATCH event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Disable interrupt on READY event.

`pub fn address(&mut self) -> ADDRESS_W`[src]

Bit 1 - Disable interrupt on ADDRESS event.

`pub fn payload(&mut self) -> PAYLOAD_W`[src]

Bit 2 - Disable interrupt on PAYLOAD event.

`pub fn end(&mut self) -> END_W`[src]

Bit 3 - Disable interrupt on END event.

`pub fn disabled(&mut self) -> DISABLED_W`[src]

Bit 4 - Disable interrupt on DISABLED event.

`pub fn devmatch(&mut self) -> DEVMATCH_W`[src]

Bit 5 - Disable interrupt on DEVMATCH event.

`pub fn devmiss(&mut self) -> DEVMISS_W`[src]

Bit 6 - Disable interrupt on DEVMISS event.

`pub fn rssiend(&mut self) -> RSSIEND_W`[src]

Bit 7 - Disable interrupt on RSSIEND event.

`pub fn bcmatch(&mut self) -> BCMATCH_W`[src]

Bit 10 - Disable interrupt on BCMATCH event.

`impl W<u32, Reg<u32, _FREQUENCY>>`[src]

`pub fn frequency(&mut self) -> FREQUENCY_W`[src]

Bits 0:6 - Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task.

`impl W<u32, Reg<u32, _TXPOWER>>`[src]

`pub fn txpower(&mut self) -> TXPOWER_W`[src]

Bits 0:7 - Radio output power. Decision point: TXEN task.

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - Radio data rate and modulation setting. Decision point: TXEN or RXEN task.

`impl W<u32, Reg<u32, _PCNF0>>`[src]

`pub fn lflen(&mut self) -> LFLEN_W`[src]

Bits 0:3 - Length of length field in number of bits. Decision point: START task.

`pub fn s0len(&mut self) -> S0LEN_W`[src]

Bit 8 - Length of S0 field in number of bytes. Decision point: START task.

`pub fn s1len(&mut self) -> S1LEN_W`[src]

Bits 16:19 - Length of S1 field in number of bits. Decision point: START task.

`impl W<u32, Reg<u32, _PCNF1>>`[src]

`pub fn maxlen(&mut self) -> MAXLEN_W`[src]

Bits 0:7 - Maximum length of packet payload in number of bytes.

`pub fn statlen(&mut self) -> STATLEN_W`[src]

Bits 8:15 - Static length in number of bytes. Decision point: START task.

`pub fn balen(&mut self) -> BALEN_W`[src]

Bits 16:18 - Base address length in number of bytes. Decision point: START task.

`pub fn endian(&mut self) -> ENDIAN_W`[src]

Bit 24 - On air endianness of packet length field. Decision point: START task.

`pub fn whiteen(&mut self) -> WHITEEN_W`[src]

Bit 25 - Packet whitening enable.

`impl W<u32, Reg<u32, _PREFIX0>>`[src]

`pub fn ap0(&mut self) -> AP0_W`[src]

Bits 0:7 - Address prefix 0. Decision point: START task.

`pub fn ap1(&mut self) -> AP1_W`[src]

Bits 8:15 - Address prefix 1. Decision point: START task.

`pub fn ap2(&mut self) -> AP2_W`[src]

Bits 16:23 - Address prefix 2. Decision point: START task.

`pub fn ap3(&mut self) -> AP3_W`[src]

Bits 24:31 - Address prefix 3. Decision point: START task.

`impl W<u32, Reg<u32, _PREFIX1>>`[src]

`pub fn ap4(&mut self) -> AP4_W`[src]

Bits 0:7 - Address prefix 4. Decision point: START task.

`pub fn ap5(&mut self) -> AP5_W`[src]

Bits 8:15 - Address prefix 5. Decision point: START task.

`pub fn ap6(&mut self) -> AP6_W`[src]

Bits 16:23 - Address prefix 6. Decision point: START task.

`pub fn ap7(&mut self) -> AP7_W`[src]

Bits 24:31 - Address prefix 7. Decision point: START task.

`impl W<u32, Reg<u32, _TXADDRESS>>`[src]

`pub fn txaddress(&mut self) -> TXADDRESS_W`[src]

Bits 0:2 - Logical address to be used when transmitting a packet. Decision point: START task.

`impl W<u32, Reg<u32, _RXADDRESSES>>`[src]

`pub fn addr0(&mut self) -> ADDR0_W`[src]

Bit 0 - Enable reception on logical address 0. Decision point: START task.

`pub fn addr1(&mut self) -> ADDR1_W`[src]

Bit 1 - Enable reception on logical address 1. Decision point: START task.

`pub fn addr2(&mut self) -> ADDR2_W`[src]

Bit 2 - Enable reception on logical address 2. Decision point: START task.

`pub fn addr3(&mut self) -> ADDR3_W`[src]

Bit 3 - Enable reception on logical address 3. Decision point: START task.

`pub fn addr4(&mut self) -> ADDR4_W`[src]

Bit 4 - Enable reception on logical address 4. Decision point: START task.

`pub fn addr5(&mut self) -> ADDR5_W`[src]

Bit 5 - Enable reception on logical address 5. Decision point: START task.

`pub fn addr6(&mut self) -> ADDR6_W`[src]

Bit 6 - Enable reception on logical address 6. Decision point: START task.

`pub fn addr7(&mut self) -> ADDR7_W`[src]

Bit 7 - Enable reception on logical address 7. Decision point: START task.

`impl W<u32, Reg<u32, _CRCCNF>>`[src]

`pub fn len(&mut self) -> LEN_W`[src]

Bits 0:1 - CRC length. Decision point: START task.

`pub fn skipaddr(&mut self) -> SKIPADDR_W`[src]

Bit 8 - Leave packet address field out of the CRC calculation. Decision point: START task.

`impl W<u32, Reg<u32, _CRCPOLY>>`[src]

`pub fn crcpoly(&mut self) -> CRCPOLY_W`[src]

Bits 0:23 - CRC polynomial. Decision point: START task.

`impl W<u32, Reg<u32, _CRCINIT>>`[src]

`pub fn crcinit(&mut self) -> CRCINIT_W`[src]

Bits 0:23 - Initial value for CRC calculation. Decision point: START task.

`impl W<u32, Reg<u32, _TEST>>`[src]

`pub fn constcarrier(&mut self) -> CONSTCARRIER_W`[src]

Bit 0 - Constant carrier. Decision point: TXEN task.

`pub fn plllock(&mut self) -> PLLLOCK_W`[src]

Bit 1 - PLL lock. Decision point: TXEN or RXEN task.

`impl W<u32, Reg<u32, _TIFS>>`[src]

`pub fn tifs(&mut self) -> TIFS_W`[src]

Bits 0:7 - Inter frame spacing in microseconds. Decision point: START rask

`impl W<u32, Reg<u32, _DATAWHITEIV>>`[src]

`pub fn datawhiteiv(&mut self) -> DATAWHITEIV_W`[src]

Bits 0:6 - Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task.

`impl W<u32, Reg<u32, _DAP>>`[src]

`pub fn dap(&mut self) -> DAP_W`[src]

Bits 0:15 - Device address prefix.

`impl W<u32, Reg<u32, _DACNF>>`[src]

`pub fn ena0(&mut self) -> ENA0_W`[src]

Bit 0 - Enable or disable device address matching using device address 0.

`pub fn ena1(&mut self) -> ENA1_W`[src]

Bit 1 - Enable or disable device address matching using device address 1.

`pub fn ena2(&mut self) -> ENA2_W`[src]

Bit 2 - Enable or disable device address matching using device address 2.

`pub fn ena3(&mut self) -> ENA3_W`[src]

Bit 3 - Enable or disable device address matching using device address 3.

`pub fn ena4(&mut self) -> ENA4_W`[src]

Bit 4 - Enable or disable device address matching using device address 4.

`pub fn ena5(&mut self) -> ENA5_W`[src]

Bit 5 - Enable or disable device address matching using device address 5.

`pub fn ena6(&mut self) -> ENA6_W`[src]

Bit 6 - Enable or disable device address matching using device address 6.

`pub fn ena7(&mut self) -> ENA7_W`[src]

Bit 7 - Enable or disable device address matching using device address 7.

`pub fn txadd0(&mut self) -> TXADD0_W`[src]

Bit 8 - TxAdd for device address 0.

`pub fn txadd1(&mut self) -> TXADD1_W`[src]

Bit 9 - TxAdd for device address 1.

`pub fn txadd2(&mut self) -> TXADD2_W`[src]

Bit 10 - TxAdd for device address 2.

`pub fn txadd3(&mut self) -> TXADD3_W`[src]

Bit 11 - TxAdd for device address 3.

`pub fn txadd4(&mut self) -> TXADD4_W`[src]

Bit 12 - TxAdd for device address 4.

`pub fn txadd5(&mut self) -> TXADD5_W`[src]

Bit 13 - TxAdd for device address 5.

`pub fn txadd6(&mut self) -> TXADD6_W`[src]

Bit 14 - TxAdd for device address 6.

`pub fn txadd7(&mut self) -> TXADD7_W`[src]

Bit 15 - TxAdd for device address 7.

`impl W<u32, Reg<u32, _OVERRIDE0>>`[src]

`pub fn override0(&mut self) -> OVERRIDE0_W`[src]

Bits 0:31 - Trim value override 0.

`impl W<u32, Reg<u32, _OVERRIDE1>>`[src]

`pub fn override1(&mut self) -> OVERRIDE1_W`[src]

Bits 0:31 - Trim value override 1.

`impl W<u32, Reg<u32, _OVERRIDE2>>`[src]

`pub fn override2(&mut self) -> OVERRIDE2_W`[src]

Bits 0:31 - Trim value override 2.

`impl W<u32, Reg<u32, _OVERRIDE3>>`[src]

`pub fn override3(&mut self) -> OVERRIDE3_W`[src]

Bits 0:31 - Trim value override 3.

`impl W<u32, Reg<u32, _OVERRIDE4>>`[src]

`pub fn override4(&mut self) -> OVERRIDE4_W`[src]

Bits 0:27 - Trim value override 4.

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 31 - Enable or disable override of default trim values.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn cts_startrx(&mut self) -> CTS_STARTRX_W`[src]

Bit 3 - Shortcut between CTS event and STARTRX task.

`pub fn ncts_stoprx(&mut self) -> NCTS_STOPRX_W`[src]

Bit 4 - Shortcut between NCTS event and STOPRX task.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn cts(&mut self) -> CTS_W`[src]

Bit 0 - Enable interrupt on CTS event.

`pub fn ncts(&mut self) -> NCTS_W`[src]

Bit 1 - Enable interrupt on NCTS event.

`pub fn rxdrdy(&mut self) -> RXDRDY_W`[src]

Bit 2 - Enable interrupt on RXRDY event.

`pub fn txdrdy(&mut self) -> TXDRDY_W`[src]

Bit 7 - Enable interrupt on TXRDY event.

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Enable interrupt on ERROR event.

`pub fn rxto(&mut self) -> RXTO_W`[src]

Bit 17 - Enable interrupt on RXTO event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn cts(&mut self) -> CTS_W`[src]

Bit 0 - Disable interrupt on CTS event.

`pub fn ncts(&mut self) -> NCTS_W`[src]

Bit 1 - Disable interrupt on NCTS event.

`pub fn rxdrdy(&mut self) -> RXDRDY_W`[src]

Bit 2 - Disable interrupt on RXRDY event.

`pub fn txdrdy(&mut self) -> TXDRDY_W`[src]

Bit 7 - Disable interrupt on TXRDY event.

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Disable interrupt on ERROR event.

`pub fn rxto(&mut self) -> RXTO_W`[src]

Bit 17 - Disable interrupt on RXTO event.

`impl W<u32, Reg<u32, _ERRORSRC>>`[src]

`pub fn overrun(&mut self) -> OVERRUN_W`[src]

Bit 0 - A start bit is received while the previous data still lies in RXD. (Data loss).

`pub fn parity(&mut self) -> PARITY_W`[src]

Bit 1 - A character with bad parity is received. Only checked if HW parity control is enabled.

`pub fn framing(&mut self) -> FRAMING_W`[src]

Bit 2 - A valid stop bit is not detected on the serial data input after all bits in a character have been received.

`pub fn break_(&mut self) -> BREAK_W`[src]

Bit 3 - The serial data input is '0' for longer than the length of a data frame.

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:2 - Enable or disable UART and acquire IOs.

`impl W<u32, Reg<u32, _TXD>>`[src]

`pub fn txd(&mut self) -> TXD_W`[src]

Bits 0:7 - TX data for transfer.

`impl W<u32, Reg<u32, _BAUDRATE>>`[src]

`pub fn baudrate(&mut self) -> BAUDRATE_W`[src]

Bits 0:31 - UART baudrate.

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn hwfc(&mut self) -> HWFC_W`[src]

Bit 0 - Hardware flow control.

`pub fn parity(&mut self) -> PARITY_W`[src]

Bits 1:3 - Include parity bit.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 2 - Enable interrupt on READY event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 2 - Disable interrupt on READY event.

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:2 - Enable or disable SPI.

`impl W<u32, Reg<u32, _TXD>>`[src]

`pub fn txd(&mut self) -> TXD_W`[src]

Bits 0:7 - TX data for next transfer.

`impl W<u32, Reg<u32, _FREQUENCY>>`[src]

`pub fn frequency(&mut self) -> FREQUENCY_W`[src]

Bits 0:31 - SPI data rate.

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn order(&mut self) -> ORDER_W`[src]

Bit 0 - Bit order.

`pub fn cpha(&mut self) -> CPHA_W`[src]

Bit 1 - Serial clock (SCK) phase.

`pub fn cpol(&mut self) -> CPOL_W`[src]

Bit 2 - Serial clock (SCK) polarity.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn bb_suspend(&mut self) -> BB_SUSPEND_W`[src]

Bit 0 - Shortcut between BB event and the SUSPEND task.

`pub fn bb_stop(&mut self) -> BB_STOP_W`[src]

Bit 1 - Shortcut between BB event and the STOP task.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Enable interrupt on STOPPED event.

`pub fn rxdready(&mut self) -> RXDREADY_W`[src]

Bit 2 - Enable interrupt on READY event.

`pub fn txdsent(&mut self) -> TXDSENT_W`[src]

Bit 7 - Enable interrupt on TXDSENT event.

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Enable interrupt on ERROR event.

`pub fn bb(&mut self) -> BB_W`[src]

Bit 14 - Enable interrupt on BB event.

`pub fn suspended(&mut self) -> SUSPENDED_W`[src]

Bit 18 - Enable interrupt on SUSPENDED event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn stopped(&mut self) -> STOPPED_W`[src]

Bit 1 - Disable interrupt on STOPPED event.

`pub fn rxdready(&mut self) -> RXDREADY_W`[src]

Bit 2 - Disable interrupt on RXDREADY event.

`pub fn txdsent(&mut self) -> TXDSENT_W`[src]

Bit 7 - Disable interrupt on TXDSENT event.

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 9 - Disable interrupt on ERROR event.

`pub fn bb(&mut self) -> BB_W`[src]

Bit 14 - Disable interrupt on BB event.

`pub fn suspended(&mut self) -> SUSPENDED_W`[src]

Bit 18 - Disable interrupt on SUSPENDED event.

`impl W<u32, Reg<u32, _ERRORSRC>>`[src]

`pub fn overrun(&mut self) -> OVERRUN_W`[src]

Bit 0 - Byte received in RXD register before read of the last received byte (data loss).

`pub fn anack(&mut self) -> ANACK_W`[src]

Bit 1 - NACK received after sending the address.

`pub fn dnack(&mut self) -> DNACK_W`[src]

Bit 2 - NACK received after sending a data byte.

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:2 - Enable or disable W2M

`impl W<u32, Reg<u32, _TXD>>`[src]

`pub fn txd(&mut self) -> TXD_W`[src]

Bits 0:7 - TX data for next transfer.

`impl W<u32, Reg<u32, _FREQUENCY>>`[src]

`pub fn frequency(&mut self) -> FREQUENCY_W`[src]

Bits 0:31 - Two-wire master clock frequency.

`impl W<u32, Reg<u32, _ADDRESS>>`[src]

`pub fn address(&mut self) -> ADDRESS_W`[src]

Bits 0:6 - Two-wire address.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn end_acquire(&mut self) -> END_ACQUIRE_W`[src]

Bit 2 - Shortcut between END event and the ACQUIRE task.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn end(&mut self) -> END_W`[src]

Bit 1 - Enable interrupt on END event.

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 4 - enable interrupt on ENDRX event.

`pub fn acquired(&mut self) -> ACQUIRED_W`[src]

Bit 10 - Enable interrupt on ACQUIRED event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn end(&mut self) -> END_W`[src]

Bit 1 - Disable interrupt on END event.

`pub fn endrx(&mut self) -> ENDRX_W`[src]

Bit 4 - Disable interrupt on ENDRX event.

`pub fn acquired(&mut self) -> ACQUIRED_W`[src]

Bit 10 - Disable interrupt on ACQUIRED event.

`impl W<u32, Reg<u32, _STATUS>>`[src]

`pub fn overread(&mut self) -> OVERREAD_W`[src]

Bit 0 - TX buffer overread detected, and prevented.

`pub fn overflow(&mut self) -> OVERFLOW_W`[src]

Bit 1 - RX buffer overflow detected, and prevented.

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:2 - Enable or disable SPIS.

`impl W<u32, Reg<u32, _MAXRX>>`[src]

`pub fn maxrx(&mut self) -> MAXRX_W`[src]

Bits 0:7 - Maximum number of bytes in the receive buffer.

`impl W<u32, Reg<u32, _MAXTX>>`[src]

`pub fn maxtx(&mut self) -> MAXTX_W`[src]

Bits 0:7 - Maximum number of bytes in the transmit buffer.

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn order(&mut self) -> ORDER_W`[src]

Bit 0 - Bit order.

`pub fn cpha(&mut self) -> CPHA_W`[src]

Bit 1 - Serial clock (SCK) phase.

`pub fn cpol(&mut self) -> CPOL_W`[src]

Bit 2 - Serial clock (SCK) polarity.

`impl W<u32, Reg<u32, _DEF>>`[src]

`pub fn def(&mut self) -> DEF_W`[src]

Bits 0:7 - Default character.

`impl W<u32, Reg<u32, _ORC>>`[src]

`pub fn orc(&mut self) -> ORC_W`[src]

Bits 0:7 - Over-read character.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn in0(&mut self) -> IN0_W`[src]

Bit 0 - Enable interrupt on IN[0] event.

`pub fn in1(&mut self) -> IN1_W`[src]

Bit 1 - Enable interrupt on IN[1] event.

`pub fn in2(&mut self) -> IN2_W`[src]

Bit 2 - Enable interrupt on IN[2] event.

`pub fn in3(&mut self) -> IN3_W`[src]

Bit 3 - Enable interrupt on IN[3] event.

`pub fn port(&mut self) -> PORT_W`[src]

Bit 31 - Enable interrupt on PORT event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn in0(&mut self) -> IN0_W`[src]

Bit 0 - Disable interrupt on IN[0] event.

`pub fn in1(&mut self) -> IN1_W`[src]

Bit 1 - Disable interrupt on IN[1] event.

`pub fn in2(&mut self) -> IN2_W`[src]

Bit 2 - Disable interrupt on IN[2] event.

`pub fn in3(&mut self) -> IN3_W`[src]

Bit 3 - Disable interrupt on IN[3] event.

`pub fn port(&mut self) -> PORT_W`[src]

Bit 31 - Disable interrupt on PORT event.

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bits 0:1 - Mode

`pub fn psel(&mut self) -> PSEL_W`[src]

Bits 8:12 - Pin select.

`pub fn polarity(&mut self) -> POLARITY_W`[src]

Bits 16:17 - Effects on output when in Task mode, or events on input that generates an event.

`pub fn outinit(&mut self) -> OUTINIT_W`[src]

Bit 20 - Initial value of the output when the GPIOTE channel is configured as a Task.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn end(&mut self) -> END_W`[src]

Bit 0 - Enable interrupt on END event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn end(&mut self) -> END_W`[src]

Bit 0 - Disable interrupt on END event.

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:1 - ADC enable.

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn res(&mut self) -> RES_W`[src]

Bits 0:1 - ADC resolution.

`pub fn inpsel(&mut self) -> INPSEL_W`[src]

Bits 2:4 - ADC input selection.

`pub fn refsel(&mut self) -> REFSEL_W`[src]

Bits 5:6 - ADC reference selection.

`pub fn psel(&mut self) -> PSEL_W`[src]

Bits 8:15 - ADC analog pin selection.

`pub fn extrefsel(&mut self) -> EXTREFSEL_W`[src]

Bits 16:17 - ADC external reference pin selection.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W`[src]

Bit 0 - Shortcut between CC[0] event and the CLEAR task.

`pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W`[src]

Bit 1 - Shortcut between CC[1] event and the CLEAR task.

`pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W`[src]

Bit 2 - Shortcut between CC[2] event and the CLEAR task.

`pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W`[src]

Bit 3 - Shortcut between CC[3] event and the CLEAR task.

`pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W`[src]

Bit 8 - Shortcut between CC[0] event and the STOP task.

`pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W`[src]

Bit 9 - Shortcut between CC[1] event and the STOP task.

`pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W`[src]

Bit 10 - Shortcut between CC[2] event and the STOP task.

`pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W`[src]

Bit 11 - Shortcut between CC[3] event and the STOP task.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Enable interrupt on COMPARE[0]

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Enable interrupt on COMPARE[1]

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Enable interrupt on COMPARE[2]

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Enable interrupt on COMPARE[3]

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Disable interrupt on COMPARE[0]

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Disable interrupt on COMPARE[1]

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Disable interrupt on COMPARE[2]

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Disable interrupt on COMPARE[3]

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bit 0 - Select Normal or Counter mode.

`impl W<u32, Reg<u32, _BITMODE>>`[src]

`pub fn bitmode(&mut self) -> BITMODE_W`[src]

Bits 0:1 - Sets timer behaviour ro be like the implementation of a timer with width as indicated.

`impl W<u32, Reg<u32, _PRESCALER>>`[src]

`pub fn prescaler(&mut self) -> PRESCALER_W`[src]

Bits 0:3 - Timer PRESCALER value. Max value is 9.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn tick(&mut self) -> TICK_W`[src]

Bit 0 - Enable interrupt on TICK event.

`pub fn ovrflw(&mut self) -> OVRFLW_W`[src]

Bit 1 - Enable interrupt on OVRFLW event.

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Enable interrupt on COMPARE[0] event.

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Enable interrupt on COMPARE[1] event.

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Enable interrupt on COMPARE[2] event.

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Enable interrupt on COMPARE[3] event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn tick(&mut self) -> TICK_W`[src]

Bit 0 - Disable interrupt on TICK event.

`pub fn ovrflw(&mut self) -> OVRFLW_W`[src]

Bit 1 - Disable interrupt on OVRFLW event.

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Disable interrupt on COMPARE[0] event.

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Disable interrupt on COMPARE[1] event.

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Disable interrupt on COMPARE[2] event.

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Disable interrupt on COMPARE[3] event.

`impl W<u32, Reg<u32, _EVTEN>>`[src]

`pub fn tick(&mut self) -> TICK_W`[src]

Bit 0 - TICK event enable.

`pub fn ovrflw(&mut self) -> OVRFLW_W`[src]

Bit 1 - OVRFLW event enable.

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - COMPARE[0] event enable.

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - COMPARE[1] event enable.

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - COMPARE[2] event enable.

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - COMPARE[3] event enable.

`impl W<u32, Reg<u32, _EVTENSET>>`[src]

`pub fn tick(&mut self) -> TICK_W`[src]

Bit 0 - Enable routing to PPI of TICK event.

`pub fn ovrflw(&mut self) -> OVRFLW_W`[src]

Bit 1 - Enable routing to PPI of OVRFLW event.

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Enable routing to PPI of COMPARE[0] event.

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Enable routing to PPI of COMPARE[1] event.

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Enable routing to PPI of COMPARE[2] event.

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Enable routing to PPI of COMPARE[3] event.

`impl W<u32, Reg<u32, _EVTENCLR>>`[src]

`pub fn tick(&mut self) -> TICK_W`[src]

Bit 0 - Disable routing to PPI of TICK event.

`pub fn ovrflw(&mut self) -> OVRFLW_W`[src]

Bit 1 - Disable routing to PPI of OVRFLW event.

`pub fn compare0(&mut self) -> COMPARE0_W`[src]

Bit 16 - Disable routing to PPI of COMPARE[0] event.

`pub fn compare1(&mut self) -> COMPARE1_W`[src]

Bit 17 - Disable routing to PPI of COMPARE[1] event.

`pub fn compare2(&mut self) -> COMPARE2_W`[src]

Bit 18 - Disable routing to PPI of COMPARE[2] event.

`pub fn compare3(&mut self) -> COMPARE3_W`[src]

Bit 19 - Disable routing to PPI of COMPARE[3] event.

`impl W<u32, Reg<u32, _PRESCALER>>`[src]

`pub fn prescaler(&mut self) -> PRESCALER_W`[src]

Bits 0:11 - RTC PRESCALER value.

`impl W<u32, Reg<u32, _CC>>`[src]

`pub fn compare(&mut self) -> COMPARE_W`[src]

Bits 0:23 - Compare value.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn datardy(&mut self) -> DATARDY_W`[src]

Bit 0 - Enable interrupt on DATARDY event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn datardy(&mut self) -> DATARDY_W`[src]

Bit 0 - Disable interrupt on DATARDY event.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn valrdy_stop(&mut self) -> VALRDY_STOP_W`[src]

Bit 0 - Shortcut between VALRDY event and STOP task.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn valrdy(&mut self) -> VALRDY_W`[src]

Bit 0 - Enable interrupt on VALRDY event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn valrdy(&mut self) -> VALRDY_W`[src]

Bit 0 - Disable interrupt on VALRDY event.

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn dercen(&mut self) -> DERCEN_W`[src]

Bit 0 - Digital error correction enable.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn endecb(&mut self) -> ENDECB_W`[src]

Bit 0 - Enable interrupt on ENDECB event.

`pub fn errorecb(&mut self) -> ERRORECB_W`[src]

Bit 1 - Enable interrupt on ERRORECB event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn endecb(&mut self) -> ENDECB_W`[src]

Bit 0 - Disable interrupt on ENDECB event.

`pub fn errorecb(&mut self) -> ERRORECB_W`[src]

Bit 1 - Disable interrupt on ERRORECB event.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn end(&mut self) -> END_W`[src]

Bit 0 - Enable interrupt on END event.

`pub fn resolved(&mut self) -> RESOLVED_W`[src]

Bit 1 - Enable interrupt on RESOLVED event.

`pub fn notresolved(&mut self) -> NOTRESOLVED_W`[src]

Bit 2 - Enable interrupt on NOTRESOLVED event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn end(&mut self) -> END_W`[src]

Bit 0 - Disable interrupt on ENDKSGEN event.

`pub fn resolved(&mut self) -> RESOLVED_W`[src]

Bit 1 - Disable interrupt on RESOLVED event.

`pub fn notresolved(&mut self) -> NOTRESOLVED_W`[src]

Bit 2 - Disable interrupt on NOTRESOLVED event.

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:1 - Enable AAR.

`impl W<u32, Reg<u32, _NIRK>>`[src]

`pub fn nirk(&mut self) -> NIRK_W`[src]

Bits 0:4 - Number of Identity root Keys in the IRK data structure.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn endksgen_crypt(&mut self) -> ENDKSGEN_CRYPT_W`[src]

Bit 0 - Shortcut between ENDKSGEN event and CRYPT task.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn endksgen(&mut self) -> ENDKSGEN_W`[src]

Bit 0 - Enable interrupt on ENDKSGEN event.

`pub fn endcrypt(&mut self) -> ENDCRYPT_W`[src]

Bit 1 - Enable interrupt on ENDCRYPT event.

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 2 - Enable interrupt on ERROR event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn endksgen(&mut self) -> ENDKSGEN_W`[src]

Bit 0 - Disable interrupt on ENDKSGEN event.

`pub fn endcrypt(&mut self) -> ENDCRYPT_W`[src]

Bit 1 - Disable interrupt on ENDCRYPT event.

`pub fn error(&mut self) -> ERROR_W`[src]

Bit 2 - Disable interrupt on ERROR event.

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:1 - CCM enable.

`impl W<u32, Reg<u32, _MODE>>`[src]

`pub fn mode(&mut self) -> MODE_W`[src]

Bit 0 - CCM mode operation.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn timeout(&mut self) -> TIMEOUT_W`[src]

Bit 0 - Enable interrupt on TIMEOUT event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn timeout(&mut self) -> TIMEOUT_W`[src]

Bit 0 - Disable interrupt on TIMEOUT event.

`impl W<u32, Reg<u32, _RREN>>`[src]

`pub fn rr0(&mut self) -> RR0_W`[src]

Bit 0 - Enable or disable RR[0] register.

`pub fn rr1(&mut self) -> RR1_W`[src]

Bit 1 - Enable or disable RR[1] register.

`pub fn rr2(&mut self) -> RR2_W`[src]

Bit 2 - Enable or disable RR[2] register.

`pub fn rr3(&mut self) -> RR3_W`[src]

Bit 3 - Enable or disable RR[3] register.

`pub fn rr4(&mut self) -> RR4_W`[src]

Bit 4 - Enable or disable RR[4] register.

`pub fn rr5(&mut self) -> RR5_W`[src]

Bit 5 - Enable or disable RR[5] register.

`pub fn rr6(&mut self) -> RR6_W`[src]

Bit 6 - Enable or disable RR[6] register.

`pub fn rr7(&mut self) -> RR7_W`[src]

Bit 7 - Enable or disable RR[7] register.

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn sleep(&mut self) -> SLEEP_W`[src]

Bit 0 - Configure the watchdog to pause or not while the CPU is sleeping.

`pub fn halt(&mut self) -> HALT_W`[src]

Bit 3 - Configure the watchdog to pause or not while the CPU is halted by the debugger.

`impl W<u32, Reg<u32, _RR>>`[src]

`pub fn rr(&mut self) -> RR_W`[src]

Bits 0:31 - Reload register.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn reportrdy_readclracc(&mut self) -> REPORTRDY_READCLRACC_W`[src]

Bit 0 - Shortcut between REPORTRDY event and READCLRACC task.

`pub fn samplerdy_stop(&mut self) -> SAMPLERDY_STOP_W`[src]

Bit 1 - Shortcut between SAMPLERDY event and STOP task.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn samplerdy(&mut self) -> SAMPLERDY_W`[src]

Bit 0 - Enable interrupt on SAMPLERDY event.

`pub fn reportrdy(&mut self) -> REPORTRDY_W`[src]

Bit 1 - Enable interrupt on REPORTRDY event.

`pub fn accof(&mut self) -> ACCOF_W`[src]

Bit 2 - Enable interrupt on ACCOF event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn samplerdy(&mut self) -> SAMPLERDY_W`[src]

Bit 0 - Disable interrupt on SAMPLERDY event.

`pub fn reportrdy(&mut self) -> REPORTRDY_W`[src]

Bit 1 - Disable interrupt on REPORTRDY event.

`pub fn accof(&mut self) -> ACCOF_W`[src]

Bit 2 - Disable interrupt on ACCOF event.

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bit 0 - Enable or disable QDEC.

`impl W<u32, Reg<u32, _LEDPOL>>`[src]

`pub fn ledpol(&mut self) -> LEDPOL_W`[src]

Bit 0 - LED output pin polarity.

`impl W<u32, Reg<u32, _SAMPLEPER>>`[src]

`pub fn sampleper(&mut self) -> SAMPLEPER_W`[src]

Bits 0:2 - Sample period.

`impl W<u32, Reg<u32, _REPORTPER>>`[src]

`pub fn reportper(&mut self) -> REPORTPER_W`[src]

Bits 0:2 - Number of samples to generate an EVENT_REPORTRDY.

`impl W<u32, Reg<u32, _DBFEN>>`[src]

`pub fn dbfen(&mut self) -> DBFEN_W`[src]

Bit 0 - Enable debounce input filters.

`impl W<u32, Reg<u32, _LEDPRE>>`[src]

`pub fn ledpre(&mut self) -> LEDPRE_W`[src]

Bits 0:8 - Period in us the LED in switched on prior to sampling.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn ready_sample(&mut self) -> READY_SAMPLE_W`[src]

Bit 0 - Shortcut between READY event and SAMPLE task.

`pub fn ready_stop(&mut self) -> READY_STOP_W`[src]

Bit 1 - Shortcut between RADY event and STOP task.

`pub fn down_stop(&mut self) -> DOWN_STOP_W`[src]

Bit 2 - Shortcut between DOWN event and STOP task.

`pub fn up_stop(&mut self) -> UP_STOP_W`[src]

Bit 3 - Shortcut between UP event and STOP task.

`pub fn cross_stop(&mut self) -> CROSS_STOP_W`[src]

Bit 4 - Shortcut between CROSS event and STOP task.

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Enable interrupt on READY event.

`pub fn down(&mut self) -> DOWN_W`[src]

Bit 1 - Enable interrupt on DOWN event.

`pub fn up(&mut self) -> UP_W`[src]

Bit 2 - Enable interrupt on UP event.

`pub fn cross(&mut self) -> CROSS_W`[src]

Bit 3 - Enable interrupt on CROSS event.

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

Bit 0 - Disable interrupt on READY event.

`pub fn down(&mut self) -> DOWN_W`[src]

Bit 1 - Disable interrupt on DOWN event.

`pub fn up(&mut self) -> UP_W`[src]

Bit 2 - Disable interrupt on UP event.

`pub fn cross(&mut self) -> CROSS_W`[src]

Bit 3 - Disable interrupt on CROSS event.

`impl W<u32, Reg<u32, _ENABLE>>`[src]

`pub fn enable(&mut self) -> ENABLE_W`[src]

Bits 0:1 - Enable or disable LPCOMP.

`impl W<u32, Reg<u32, _PSEL>>`[src]

`pub fn psel(&mut self) -> PSEL_W`[src]

Bits 0:2 - Analog input pin select.

`impl W<u32, Reg<u32, _REFSEL>>`[src]

`pub fn refsel(&mut self) -> REFSEL_W`[src]

Bits 0:2 - Reference select.

`impl W<u32, Reg<u32, _EXTREFSEL>>`[src]

`pub fn extrefsel(&mut self) -> EXTREFSEL_W`[src]

Bit 0 - External analog reference pin selection.

`impl W<u32, Reg<u32, _ANADETECT>>`[src]

`pub fn anadetect(&mut self) -> ANADETECT_W`[src]

Bits 0:1 - Analog detect configuration.

`impl W<u32, Reg<u32, _POWER>>`[src]

`pub fn power(&mut self) -> POWER_W`[src]

Bit 0 - Peripheral power control.

`impl W<u32, Reg<u32, _CONFIG>>`[src]

`pub fn wen(&mut self) -> WEN_W`[src]

Bits 0:1 - Program write enable.

`impl W<u32, Reg<u32, _ERASEALL>>`[src]

`pub fn eraseall(&mut self) -> ERASEALL_W`[src]

Bit 0 - Starts the erasing of all user NVM (code region 0/1 and UICR registers).

`impl W<u32, Reg<u32, _ERASEUICR>>`[src]

`pub fn eraseuicr(&mut self) -> ERASEUICR_W`[src]

Bit 0 - It can only be used when all contents of code region 1 are erased.

`impl W<u32, Reg<u32, _CHEN>>`[src]

`pub fn ch0(&mut self) -> CH0_W`[src]

Bit 0 - Enable PPI channel 0.

`pub fn ch1(&mut self) -> CH1_W`[src]

Bit 1 - Enable PPI channel 1.

`pub fn ch2(&mut self) -> CH2_W`[src]

Bit 2 - Enable PPI channel 2.

`pub fn ch3(&mut self) -> CH3_W`[src]

Bit 3 - Enable PPI channel 3.

`pub fn ch4(&mut self) -> CH4_W`[src]

Bit 4 - Enable PPI channel 4.

`pub fn ch5(&mut self) -> CH5_W`[src]

Bit 5 - Enable PPI channel 5.

`pub fn ch6(&mut self) -> CH6_W`[src]

Bit 6 - Enable PPI channel 6.

`pub fn ch7(&mut self) -> CH7_W`[src]

Bit 7 - Enable PPI channel 7.

`pub fn ch8(&mut self) -> CH8_W`[src]

Bit 8 - Enable PPI channel 8.

`pub fn ch9(&mut self) -> CH9_W`[src]

Bit 9 - Enable PPI channel 9.

`pub fn ch10(&mut self) -> CH10_W`[src]

Bit 10 - Enable PPI channel 10.

`pub fn ch11(&mut self) -> CH11_W`[src]

Bit 11 - Enable PPI channel 11.

`pub fn ch12(&mut self) -> CH12_W`[src]

Bit 12 - Enable PPI channel 12.

`pub fn ch13(&mut self) -> CH13_W`[src]

Bit 13 - Enable PPI channel 13.

`pub fn ch14(&mut self) -> CH14_W`[src]

Bit 14 - Enable PPI channel 14.

`pub fn ch15(&mut self) -> CH15_W`[src]

Bit 15 - Enable PPI channel 15.

`pub fn ch20(&mut self) -> CH20_W`[src]

Bit 20 - Enable PPI channel 20.

`pub fn ch21(&mut self) -> CH21_W`[src]

Bit 21 - Enable PPI channel 21.

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Enable PPI channel 22.

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Enable PPI channel 23.

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Enable PPI channel 24.

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Enable PPI channel 25.

`pub fn ch26(&mut self) -> CH26_W`[src]

Bit 26 - Enable PPI channel 26.

`pub fn ch27(&mut self) -> CH27_W`[src]

Bit 27 - Enable PPI channel 27.

`pub fn ch28(&mut self) -> CH28_W`[src]

Bit 28 - Enable PPI channel 28.

`pub fn ch29(&mut self) -> CH29_W`[src]

Bit 29 - Enable PPI channel 29.

`pub fn ch30(&mut self) -> CH30_W`[src]

Bit 30 - Enable PPI channel 30.

`pub fn ch31(&mut self) -> CH31_W`[src]

Bit 31 - Enable PPI channel 31.

`impl W<u32, Reg<u32, _CHENSET>>`[src]

`pub fn ch0(&mut self) -> CH0_W`[src]

Bit 0 - Enable PPI channel 0.

`pub fn ch1(&mut self) -> CH1_W`[src]

Bit 1 - Enable PPI channel 1.

`pub fn ch2(&mut self) -> CH2_W`[src]

Bit 2 - Enable PPI channel 2.

`pub fn ch3(&mut self) -> CH3_W`[src]

Bit 3 - Enable PPI channel 3.

`pub fn ch4(&mut self) -> CH4_W`[src]

Bit 4 - Enable PPI channel 4.

`pub fn ch5(&mut self) -> CH5_W`[src]

Bit 5 - Enable PPI channel 5.

`pub fn ch6(&mut self) -> CH6_W`[src]

Bit 6 - Enable PPI channel 6.

`pub fn ch7(&mut self) -> CH7_W`[src]

Bit 7 - Enable PPI channel 7.

`pub fn ch8(&mut self) -> CH8_W`[src]

Bit 8 - Enable PPI channel 8.

`pub fn ch9(&mut self) -> CH9_W`[src]

Bit 9 - Enable PPI channel 9.

`pub fn ch10(&mut self) -> CH10_W`[src]

Bit 10 - Enable PPI channel 10.

`pub fn ch11(&mut self) -> CH11_W`[src]

Bit 11 - Enable PPI channel 11.

`pub fn ch12(&mut self) -> CH12_W`[src]

Bit 12 - Enable PPI channel 12.

`pub fn ch13(&mut self) -> CH13_W`[src]

Bit 13 - Enable PPI channel 13.

`pub fn ch14(&mut self) -> CH14_W`[src]

Bit 14 - Enable PPI channel 14.

`pub fn ch15(&mut self) -> CH15_W`[src]

Bit 15 - Enable PPI channel 15.

`pub fn ch20(&mut self) -> CH20_W`[src]

Bit 20 - Enable PPI channel 20.

`pub fn ch21(&mut self) -> CH21_W`[src]

Bit 21 - Enable PPI channel 21.

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Enable PPI channel 22.

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Enable PPI channel 23.

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Enable PPI channel 24.

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Enable PPI channel 25.

`pub fn ch26(&mut self) -> CH26_W`[src]

Bit 26 - Enable PPI channel 26.

`pub fn ch27(&mut self) -> CH27_W`[src]

Bit 27 - Enable PPI channel 27.

`pub fn ch28(&mut self) -> CH28_W`[src]

Bit 28 - Enable PPI channel 28.

`pub fn ch29(&mut self) -> CH29_W`[src]

Bit 29 - Enable PPI channel 29.

`pub fn ch30(&mut self) -> CH30_W`[src]

Bit 30 - Enable PPI channel 30.

`pub fn ch31(&mut self) -> CH31_W`[src]

Bit 31 - Enable PPI channel 31.

`impl W<u32, Reg<u32, _CHENCLR>>`[src]

`pub fn ch0(&mut self) -> CH0_W`[src]

Bit 0 - Disable PPI channel 0.

`pub fn ch1(&mut self) -> CH1_W`[src]

Bit 1 - Disable PPI channel 1.

`pub fn ch2(&mut self) -> CH2_W`[src]

Bit 2 - Disable PPI channel 2.

`pub fn ch3(&mut self) -> CH3_W`[src]

Bit 3 - Disable PPI channel 3.

`pub fn ch4(&mut self) -> CH4_W`[src]

Bit 4 - Disable PPI channel 4.

`pub fn ch5(&mut self) -> CH5_W`[src]

Bit 5 - Disable PPI channel 5.

`pub fn ch6(&mut self) -> CH6_W`[src]

Bit 6 - Disable PPI channel 6.

`pub fn ch7(&mut self) -> CH7_W`[src]

Bit 7 - Disable PPI channel 7.

`pub fn ch8(&mut self) -> CH8_W`[src]

Bit 8 - Disable PPI channel 8.

`pub fn ch9(&mut self) -> CH9_W`[src]

Bit 9 - Disable PPI channel 9.

`pub fn ch10(&mut self) -> CH10_W`[src]

Bit 10 - Disable PPI channel 10.

`pub fn ch11(&mut self) -> CH11_W`[src]

Bit 11 - Disable PPI channel 11.

`pub fn ch12(&mut self) -> CH12_W`[src]

Bit 12 - Disable PPI channel 12.

`pub fn ch13(&mut self) -> CH13_W`[src]

Bit 13 - Disable PPI channel 13.

`pub fn ch14(&mut self) -> CH14_W`[src]

Bit 14 - Disable PPI channel 14.

`pub fn ch15(&mut self) -> CH15_W`[src]

Bit 15 - Disable PPI channel 15.

`pub fn ch20(&mut self) -> CH20_W`[src]

Bit 20 - Disable PPI channel 20.

`pub fn ch21(&mut self) -> CH21_W`[src]

Bit 21 - Disable PPI channel 21.

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Disable PPI channel 22.

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Disable PPI channel 23.

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Disable PPI channel 24.

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Disable PPI channel 25.

`pub fn ch26(&mut self) -> CH26_W`[src]

Bit 26 - Disable PPI channel 26.

`pub fn ch27(&mut self) -> CH27_W`[src]

Bit 27 - Disable PPI channel 27.

`pub fn ch28(&mut self) -> CH28_W`[src]

Bit 28 - Disable PPI channel 28.

`pub fn ch29(&mut self) -> CH29_W`[src]

Bit 29 - Disable PPI channel 29.

`pub fn ch30(&mut self) -> CH30_W`[src]

Bit 30 - Disable PPI channel 30.

`pub fn ch31(&mut self) -> CH31_W`[src]

Bit 31 - Disable PPI channel 31.

`impl W<u32, Reg<u32, _CHG>>`[src]

`pub fn ch0(&mut self) -> CH0_W`[src]

Bit 0 - Include CH0 in channel group.

`pub fn ch1(&mut self) -> CH1_W`[src]

Bit 1 - Include CH1 in channel group.

`pub fn ch2(&mut self) -> CH2_W`[src]

Bit 2 - Include CH2 in channel group.

`pub fn ch3(&mut self) -> CH3_W`[src]

Bit 3 - Include CH3 in channel group.

`pub fn ch4(&mut self) -> CH4_W`[src]

Bit 4 - Include CH4 in channel group.

`pub fn ch5(&mut self) -> CH5_W`[src]

Bit 5 - Include CH5 in channel group.

`pub fn ch6(&mut self) -> CH6_W`[src]

Bit 6 - Include CH6 in channel group.

`pub fn ch7(&mut self) -> CH7_W`[src]

Bit 7 - Include CH7 in channel group.

`pub fn ch8(&mut self) -> CH8_W`[src]

Bit 8 - Include CH8 in channel group.

`pub fn ch9(&mut self) -> CH9_W`[src]

Bit 9 - Include CH9 in channel group.

`pub fn ch10(&mut self) -> CH10_W`[src]

Bit 10 - Include CH10 in channel group.

`pub fn ch11(&mut self) -> CH11_W`[src]

Bit 11 - Include CH11 in channel group.

`pub fn ch12(&mut self) -> CH12_W`[src]

Bit 12 - Include CH12 in channel group.

`pub fn ch13(&mut self) -> CH13_W`[src]

Bit 13 - Include CH13 in channel group.

`pub fn ch14(&mut self) -> CH14_W`[src]

Bit 14 - Include CH14 in channel group.

`pub fn ch15(&mut self) -> CH15_W`[src]

Bit 15 - Include CH15 in channel group.

`pub fn ch20(&mut self) -> CH20_W`[src]

Bit 20 - Include CH20 in channel group.

`pub fn ch21(&mut self) -> CH21_W`[src]

Bit 21 - Include CH21 in channel group.

`pub fn ch22(&mut self) -> CH22_W`[src]

Bit 22 - Include CH22 in channel group.

`pub fn ch23(&mut self) -> CH23_W`[src]

Bit 23 - Include CH23 in channel group.

`pub fn ch24(&mut self) -> CH24_W`[src]

Bit 24 - Include CH24 in channel group.

`pub fn ch25(&mut self) -> CH25_W`[src]

Bit 25 - Include CH25 in channel group.

`pub fn ch26(&mut self) -> CH26_W`[src]

Bit 26 - Include CH26 in channel group.

`pub fn ch27(&mut self) -> CH27_W`[src]

Bit 27 - Include CH27 in channel group.

`pub fn ch28(&mut self) -> CH28_W`[src]

Bit 28 - Include CH28 in channel group.

`pub fn ch29(&mut self) -> CH29_W`[src]

Bit 29 - Include CH29 in channel group.

`pub fn ch30(&mut self) -> CH30_W`[src]

Bit 30 - Include CH30 in channel group.

`pub fn ch31(&mut self) -> CH31_W`[src]

Bit 31 - Include CH31 in channel group.

`impl W<u32, Reg<u32, _PPFC>>`[src]

`pub fn ppfc(&mut self) -> PPFC_W`[src]

Bits 0:7 - Pre-programmed factory code present.

`impl W<u32, Reg<u32, _CONFIGID>>`[src]

`pub fn hwid(&mut self) -> HWID_W`[src]

Bits 0:15 - Hardware Identification Number.

`pub fn fwid(&mut self) -> FWID_W`[src]

Bits 16:31 - Firmware Identification Number pre-loaded into the flash.

`impl W<u32, Reg<u32, _DEVICEADDRTYPE>>`[src]

`pub fn deviceaddrtype(&mut self) -> DEVICEADDRTYPE_W`[src]

Bit 0 - Device address type.

`impl W<u32, Reg<u32, _OVERRIDEEN>>`[src]

`pub fn nrf_1mbit(&mut self) -> NRF_1MBIT_W`[src]

Bit 0 - Override default values for NRF_1Mbit mode.

`pub fn ble_1mbit(&mut self) -> BLE_1MBIT_W`[src]

Bit 3 - Override default values for BLE_1Mbit mode.

`impl W<u32, Reg<u32, _RBPCONF>>`[src]

`pub fn pr0(&mut self) -> PR0_W`[src]

Bits 0:7 - Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip.

`pub fn pall(&mut self) -> PALL_W`[src]

Bits 8:15 - Readback protect all code in the device.

`impl W<u32, Reg<u32, _XTALFREQ>>`[src]

`pub fn xtalfreq(&mut self) -> XTALFREQ_W`[src]

Bits 0:7 - Reset value for CLOCK XTALFREQ register.

`impl W<u32, Reg<u32, _OUT>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Pin 0.

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Pin 1.

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Pin 2.

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Pin 3.

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Pin 4.

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Pin 5.

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Pin 6.

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Pin 7.

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Pin 8.

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Pin 9.

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Pin 10.

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Pin 11.

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Pin 12.

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Pin 13.

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Pin 14.

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Pin 15.

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Pin 16.

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Pin 17.

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Pin 18.

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Pin 19.

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Pin 20.

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Pin 21.

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Pin 22.

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Pin 23.

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Pin 24.

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Pin 25.

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Pin 26.

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Pin 27.

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Pin 28.

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Pin 29.

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Pin 30.

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Pin 31.

`impl W<u32, Reg<u32, _OUTSET>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Pin 0.

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Pin 1.

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Pin 2.

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Pin 3.

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Pin 4.

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Pin 5.

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Pin 6.

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Pin 7.

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Pin 8.

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Pin 9.

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Pin 10.

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Pin 11.

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Pin 12.

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Pin 13.

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Pin 14.

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Pin 15.

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Pin 16.

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Pin 17.

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Pin 18.

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Pin 19.

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Pin 20.

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Pin 21.

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Pin 22.

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Pin 23.

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Pin 24.

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Pin 25.

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Pin 26.

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Pin 27.

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Pin 28.

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Pin 29.

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Pin 30.

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Pin 31.

`impl W<u32, Reg<u32, _OUTCLR>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Pin 0.

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Pin 1.

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Pin 2.

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Pin 3.

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Pin 4.

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Pin 5.

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Pin 6.

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Pin 7.

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Pin 8.

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Pin 9.

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Pin 10.

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Pin 11.

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Pin 12.

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Pin 13.

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Pin 14.

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Pin 15.

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Pin 16.

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Pin 17.

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Pin 18.

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Pin 19.

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Pin 20.

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Pin 21.

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Pin 22.

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Pin 23.

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Pin 24.

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Pin 25.

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Pin 26.

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Pin 27.

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Pin 28.

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Pin 29.

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Pin 30.

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Pin 31.

`impl W<u32, Reg<u32, _DIR>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Pin 0.

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Pin 1.

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Pin 2.

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Pin 3.

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Pin 4.

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Pin 5.

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Pin 6.

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Pin 7.

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Pin 8.

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Pin 9.

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Pin 10.

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Pin 11.

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Pin 12.

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Pin 13.

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Pin 14.

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Pin 15.

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Pin 16.

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Pin 17.

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Pin 18.

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Pin 19.

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Pin 20.

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Pin 21.

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Pin 22.

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Pin 23.

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Pin 24.

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Pin 25.

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Pin 26.

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Pin 27.

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Pin 28.

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Pin 29.

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Pin 30.

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Pin 31.

`impl W<u32, Reg<u32, _DIRSET>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Set as output pin 0.

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Set as output pin 1.

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Set as output pin 2.

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Set as output pin 3.

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Set as output pin 4.

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Set as output pin 5.

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Set as output pin 6.

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Set as output pin 7.

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Set as output pin 8.

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Set as output pin 9.

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Set as output pin 10.

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Set as output pin 11.

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Set as output pin 12.

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Set as output pin 13.

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Set as output pin 14.

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Set as output pin 15.

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Set as output pin 16.

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Set as output pin 17.

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Set as output pin 18.

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Set as output pin 19.

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Set as output pin 20.

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Set as output pin 21.

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Set as output pin 22.

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Set as output pin 23.

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Set as output pin 24.

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Set as output pin 25.

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Set as output pin 26.

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Set as output pin 27.

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Set as output pin 28.

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Set as output pin 29.

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Set as output pin 30.

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Set as output pin 31.

`impl W<u32, Reg<u32, _DIRCLR>>`[src]

`pub fn pin0(&mut self) -> PIN0_W`[src]

Bit 0 - Set as input pin 0.

`pub fn pin1(&mut self) -> PIN1_W`[src]

Bit 1 - Set as input pin 1.

`pub fn pin2(&mut self) -> PIN2_W`[src]

Bit 2 - Set as input pin 2.

`pub fn pin3(&mut self) -> PIN3_W`[src]

Bit 3 - Set as input pin 3.

`pub fn pin4(&mut self) -> PIN4_W`[src]

Bit 4 - Set as input pin 4.

`pub fn pin5(&mut self) -> PIN5_W`[src]

Bit 5 - Set as input pin 5.

`pub fn pin6(&mut self) -> PIN6_W`[src]

Bit 6 - Set as input pin 6.

`pub fn pin7(&mut self) -> PIN7_W`[src]

Bit 7 - Set as input pin 7.

`pub fn pin8(&mut self) -> PIN8_W`[src]

Bit 8 - Set as input pin 8.

`pub fn pin9(&mut self) -> PIN9_W`[src]

Bit 9 - Set as input pin 9.

`pub fn pin10(&mut self) -> PIN10_W`[src]

Bit 10 - Set as input pin 10.

`pub fn pin11(&mut self) -> PIN11_W`[src]

Bit 11 - Set as input pin 11.

`pub fn pin12(&mut self) -> PIN12_W`[src]

Bit 12 - Set as input pin 12.

`pub fn pin13(&mut self) -> PIN13_W`[src]

Bit 13 - Set as input pin 13.

`pub fn pin14(&mut self) -> PIN14_W`[src]

Bit 14 - Set as input pin 14.

`pub fn pin15(&mut self) -> PIN15_W`[src]

Bit 15 - Set as input pin 15.

`pub fn pin16(&mut self) -> PIN16_W`[src]

Bit 16 - Set as input pin 16.

`pub fn pin17(&mut self) -> PIN17_W`[src]

Bit 17 - Set as input pin 17.

`pub fn pin18(&mut self) -> PIN18_W`[src]

Bit 18 - Set as input pin 18.

`pub fn pin19(&mut self) -> PIN19_W`[src]

Bit 19 - Set as input pin 19.

`pub fn pin20(&mut self) -> PIN20_W`[src]

Bit 20 - Set as input pin 20.

`pub fn pin21(&mut self) -> PIN21_W`[src]

Bit 21 - Set as input pin 21.

`pub fn pin22(&mut self) -> PIN22_W`[src]

Bit 22 - Set as input pin 22.

`pub fn pin23(&mut self) -> PIN23_W`[src]

Bit 23 - Set as input pin 23.

`pub fn pin24(&mut self) -> PIN24_W`[src]

Bit 24 - Set as input pin 24.

`pub fn pin25(&mut self) -> PIN25_W`[src]

Bit 25 - Set as input pin 25.

`pub fn pin26(&mut self) -> PIN26_W`[src]

Bit 26 - Set as input pin 26.

`pub fn pin27(&mut self) -> PIN27_W`[src]

Bit 27 - Set as input pin 27.

`pub fn pin28(&mut self) -> PIN28_W`[src]

Bit 28 - Set as input pin 28.

`pub fn pin29(&mut self) -> PIN29_W`[src]

Bit 29 - Set as input pin 29.

`pub fn pin30(&mut self) -> PIN30_W`[src]

Bit 30 - Set as input pin 30.

`pub fn pin31(&mut self) -> PIN31_W`[src]

Bit 31 - Set as input pin 31.

`impl W<u32, Reg<u32, _PIN_CNF>>`[src]

`pub fn dir(&mut self) -> DIR_W`[src]

Bit 0 - Pin direction.

`pub fn input(&mut self) -> INPUT_W`[src]

Bit 1 - Connect or disconnect input path.

`pub fn pull(&mut self) -> PULL_W`[src]

Bits 2:3 - Pull-up or -down configuration.

`pub fn drive(&mut self) -> DRIVE_W`[src]

Bits 8:10 - Drive configuration.

`pub fn sense(&mut self) -> SENSE_W`[src]

Bits 16:17 - Pin sensing mechanism.

Auto Trait Implementations

`impl<U, REG> Send for W<U, REG> where REG: Send, U: Send,`

`impl<U, REG> Sync for W<U, REG> where REG: Sync, U: Sync,`

`impl<U, REG> Unpin for W<U, REG> where REG: Unpin, U: Unpin,`

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T> Same<T> for T`

`type Output = T`

Should always be Self

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Struct nrf51::generic::W

Methods

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut Self[src]

impl W<u32, Reg<u32, _INTENSET>>[src]

pub fn pofwarn(&mut self) -> POFWARN_W[src]

impl W<u32, Reg<u32, _INTENCLR>>[src]

pub fn pofwarn(&mut self) -> POFWARN_W[src]

impl W<u32, Reg<u32, _RESETREAS>>[src]

pub fn resetpin(&mut self) -> RESETPIN_W[src]

pub fn dog(&mut self) -> DOG_W[src]

pub fn sreq(&mut self) -> SREQ_W[src]

pub fn lockup(&mut self) -> LOCKUP_W[src]

pub fn off(&mut self) -> OFF_W[src]

pub fn lpcomp(&mut self) -> LPCOMP_W[src]

pub fn dif(&mut self) -> DIF_W[src]

impl W<u32, Reg<u32, _SYSTEMOFF>>[src]

pub fn systemoff(&mut self) -> SYSTEMOFF_W[src]

impl W<u32, Reg<u32, _POFCON>>[src]

pub fn pof(&mut self) -> POF_W[src]

pub fn threshold(&mut self) -> THRESHOLD_W[src]

impl W<u32, Reg<u32, _GPREGRET>>[src]

pub fn gpregret(&mut self) -> GPREGRET_W[src]

impl W<u32, Reg<u32, _RAMON>>[src]

pub fn onram0(&mut self) -> ONRAM0_W[src]

pub fn onram1(&mut self) -> ONRAM1_W[src]

pub fn offram0(&mut self) -> OFFRAM0_W[src]

pub fn offram1(&mut self) -> OFFRAM1_W[src]

impl W<u32, Reg<u32, _RESET>>[src]

pub fn reset(&mut self) -> RESET_W[src]

impl W<u32, Reg<u32, _RAMONB>>[src]

pub fn onram2(&mut self) -> ONRAM2_W[src]

pub fn onram3(&mut self) -> ONRAM3_W[src]

pub fn offram2(&mut self) -> OFFRAM2_W[src]

pub fn offram3(&mut self) -> OFFRAM3_W[src]

impl W<u32, Reg<u32, _DCDCEN>>[src]

pub fn dcdcen(&mut self) -> DCDCEN_W[src]

impl W<u32, Reg<u32, _DCDCFORCE>>[src]

pub fn forceoff(&mut self) -> FORCEOFF_W[src]

pub fn forceon(&mut self) -> FORCEON_W[src]

impl W<u32, Reg<u32, _INTENSET>>[src]

pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W[src]

pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W[src]

pub fn done(&mut self) -> DONE_W[src]

pub fn ctto(&mut self) -> CTTO_W[src]

impl W<u32, Reg<u32, _INTENCLR>>[src]

pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W[src]

pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W[src]

pub fn done(&mut self) -> DONE_W[src]

pub fn ctto(&mut self) -> CTTO_W[src]

impl W<u32, Reg<u32, _LFCLKSRC>>[src]

pub fn src(&mut self) -> SRC_W[src]

impl W<u32, Reg<u32, _CTIV>>[src]

pub fn ctiv(&mut self) -> CTIV_W[src]

impl W<u32, Reg<u32, _XTALFREQ>>[src]

pub fn xtalfreq(&mut self) -> XTALFREQ_W[src]

impl W<u32, Reg<u32, _SHORTS>>[src]

pub fn ready_start(&mut self) -> READY_START_W[src]

pub fn end_disable(&mut self) -> END_DISABLE_W[src]

pub fn disabled_txen(&mut self) -> DISABLED_TXEN_W[src]

pub fn disabled_rxen(&mut self) -> DISABLED_RXEN_W[src]

pub fn address_rssistart(&mut self) -> ADDRESS_RSSISTART_W[src]

pub fn end_start(&mut self) -> END_START_W[src]

pub fn address_bcstart(&mut self) -> ADDRESS_BCSTART_W[src]

pub fn disabled_rssistop(&mut self) -> DISABLED_RSSISTOP_W[src]

impl W<u32, Reg<u32, _INTENSET>>[src]

pub fn ready(&mut self) -> READY_W[src]

pub fn address(&mut self) -> ADDRESS_W[src]

pub fn payload(&mut self) -> PAYLOAD_W[src]

pub fn end(&mut self) -> END_W[src]

pub fn disabled(&mut self) -> DISABLED_W[src]

pub fn devmatch(&mut self) -> DEVMATCH_W[src]

pub fn devmiss(&mut self) -> DEVMISS_W[src]

pub fn rssiend(&mut self) -> RSSIEND_W[src]

pub fn bcmatch(&mut self) -> BCMATCH_W[src]

impl W<u32, Reg<u32, _INTENCLR>>[src]

pub fn ready(&mut self) -> READY_W[src]

pub fn address(&mut self) -> ADDRESS_W[src]

pub fn payload(&mut self) -> PAYLOAD_W[src]

pub fn end(&mut self) -> END_W[src]

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn pofwarn(&mut self) -> POFWARN_W`[src]

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn pofwarn(&mut self) -> POFWARN_W`[src]

`impl W<u32, Reg<u32, _RESETREAS>>`[src]

`pub fn resetpin(&mut self) -> RESETPIN_W`[src]

`pub fn dog(&mut self) -> DOG_W`[src]

`pub fn sreq(&mut self) -> SREQ_W`[src]

`pub fn lockup(&mut self) -> LOCKUP_W`[src]

`pub fn off(&mut self) -> OFF_W`[src]

`pub fn lpcomp(&mut self) -> LPCOMP_W`[src]

`pub fn dif(&mut self) -> DIF_W`[src]

`impl W<u32, Reg<u32, _SYSTEMOFF>>`[src]

`pub fn systemoff(&mut self) -> SYSTEMOFF_W`[src]

`impl W<u32, Reg<u32, _POFCON>>`[src]

`pub fn pof(&mut self) -> POF_W`[src]

`pub fn threshold(&mut self) -> THRESHOLD_W`[src]

`impl W<u32, Reg<u32, _GPREGRET>>`[src]

`pub fn gpregret(&mut self) -> GPREGRET_W`[src]

`impl W<u32, Reg<u32, _RAMON>>`[src]

`pub fn onram0(&mut self) -> ONRAM0_W`[src]

`pub fn onram1(&mut self) -> ONRAM1_W`[src]

`pub fn offram0(&mut self) -> OFFRAM0_W`[src]

`pub fn offram1(&mut self) -> OFFRAM1_W`[src]

`impl W<u32, Reg<u32, _RESET>>`[src]

`pub fn reset(&mut self) -> RESET_W`[src]

`impl W<u32, Reg<u32, _RAMONB>>`[src]

`pub fn onram2(&mut self) -> ONRAM2_W`[src]

`pub fn onram3(&mut self) -> ONRAM3_W`[src]

`pub fn offram2(&mut self) -> OFFRAM2_W`[src]

`pub fn offram3(&mut self) -> OFFRAM3_W`[src]

`impl W<u32, Reg<u32, _DCDCEN>>`[src]

`pub fn dcdcen(&mut self) -> DCDCEN_W`[src]

`impl W<u32, Reg<u32, _DCDCFORCE>>`[src]

`pub fn forceoff(&mut self) -> FORCEOFF_W`[src]

`pub fn forceon(&mut self) -> FORCEON_W`[src]

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W`[src]

`pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W`[src]

`pub fn done(&mut self) -> DONE_W`[src]

`pub fn ctto(&mut self) -> CTTO_W`[src]

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W`[src]

`pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W`[src]

`pub fn done(&mut self) -> DONE_W`[src]

`pub fn ctto(&mut self) -> CTTO_W`[src]

`impl W<u32, Reg<u32, _LFCLKSRC>>`[src]

`pub fn src(&mut self) -> SRC_W`[src]

`impl W<u32, Reg<u32, _CTIV>>`[src]

`pub fn ctiv(&mut self) -> CTIV_W`[src]

`impl W<u32, Reg<u32, _XTALFREQ>>`[src]

`pub fn xtalfreq(&mut self) -> XTALFREQ_W`[src]

`impl W<u32, Reg<u32, _SHORTS>>`[src]

`pub fn ready_start(&mut self) -> READY_START_W`[src]

`pub fn end_disable(&mut self) -> END_DISABLE_W`[src]

`pub fn disabled_txen(&mut self) -> DISABLED_TXEN_W`[src]

`pub fn disabled_rxen(&mut self) -> DISABLED_RXEN_W`[src]

`pub fn address_rssistart(&mut self) -> ADDRESS_RSSISTART_W`[src]

`pub fn end_start(&mut self) -> END_START_W`[src]

`pub fn address_bcstart(&mut self) -> ADDRESS_BCSTART_W`[src]

`pub fn disabled_rssistop(&mut self) -> DISABLED_RSSISTOP_W`[src]

`impl W<u32, Reg<u32, _INTENSET>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

`pub fn address(&mut self) -> ADDRESS_W`[src]

`pub fn payload(&mut self) -> PAYLOAD_W`[src]

`pub fn end(&mut self) -> END_W`[src]

`pub fn disabled(&mut self) -> DISABLED_W`[src]

`pub fn devmatch(&mut self) -> DEVMATCH_W`[src]

`pub fn devmiss(&mut self) -> DEVMISS_W`[src]

`pub fn rssiend(&mut self) -> RSSIEND_W`[src]

`pub fn bcmatch(&mut self) -> BCMATCH_W`[src]

`impl W<u32, Reg<u32, _INTENCLR>>`[src]

`pub fn ready(&mut self) -> READY_W`[src]

`pub fn address(&mut self) -> ADDRESS_W`[src]

`pub fn payload(&mut self) -> PAYLOAD_W`[src]

`pub fn end(&mut self) -> END_W`[src]

`pub fn disabled(&mut self) -> DISABLED_W`[src]

`pub fn devmatch(&mut self) -> DEVMATCH_W`[src]